Emulation of unaligned LDXC1/SDXC1 instructions

Emulation of unaligned LDXC1/SDXC1 instructions

[Aurelien Jarno]

Hi all,

Debian recently got access to Cavium III machines which have an FPU,
before we were using Cavium II machines with the kernel FPU emulation.

It appears some code (at least openjdk and lcms2, probably more) use the
LDXC1 and SDXC1 instructions with word aligned addresses instead of
double-word aligned addresses as required by the specification. This
causes a SIGILL. The kernel emulation is more relaxed and allow word
aligned addresses.

First of all I am surprised to get a SIGILL in that case instead of a
SIGBUS, and secondly I think the behavior with and without FPU should be
consistent. The kernel currently emulates unaligned LDC1 and SDC1
instructions even with an FPU, so I wonder if the kernel should also
emulate unaligned LDXC1 and SDXC1 instructions.

Any opinion?

Thanks,
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

[PATCH] MIPS: Allow emulation for unaligned [LS]DXC1 instructions

[Paul Burton]

If an address error exception occurs for a LDXC1 or SDXC1 instruction,
within the cop1x opcode space, allow it to be passed through to the FPU
emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to
be handled in a manner consistent with the more common LDC1 & SDC1
instructions.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
---
Hi Aurelien,

Thanks for tracking that down. Does this simple patch fix your problem?

Thanks,
    Paul
---
 arch/mips/kernel/unaligned.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 5c62065..28b3af7 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -1191,6 +1191,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
 	case ldc1_op:
 	case swc1_op:
 	case sdc1_op:
+	case cop1x_op:
 		die_if_kernel("Unaligned FP access in kernel code", regs);
 		BUG_ON(!used_math());
 
-- 
2.8.0

[PATCH] MIPS: Allow emulation for unaligned [LS]DXC1 instructions

[Paul Burton]

If an address error exception occurs for a LDXC1 or SDXC1 instruction,
within the cop1x opcode space, allow it to be passed through to the FPU
emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to
be handled in a manner consistent with the more common LDC1 & SDC1
instructions.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
---
Hi Aurelien,

Thanks for tracking that down. Does this simple patch fix your problem?

Thanks,
    Paul
---
 arch/mips/kernel/unaligned.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 5c62065..28b3af7 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -1191,6 +1191,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
 	case ldc1_op:
 	case swc1_op:
 	case sdc1_op:
+	case cop1x_op:
 		die_if_kernel("Unaligned FP access in kernel code", regs);
 		BUG_ON(!used_math());
 
-- 
2.8.0

Re: [PATCH] MIPS: Allow emulation for unaligned [LS]DXC1 instructions

[Aurelien Jarno]

On 2016-04-21 12:25, Paul Burton wrote:
> If an address error exception occurs for a LDXC1 or SDXC1 instruction,
> within the cop1x opcode space, allow it to be passed through to the FPU
> emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to
> be handled in a manner consistent with the more common LDC1 & SDC1
> instructions.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> ---
> Hi Aurelien,
> 
> Thanks for tracking that down. Does this simple patch fix your problem?
> 

Thanks for the quick patch. I confirm this fixes the issue, so you can
add a:

Tested-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net