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From: James Hogan <james.hogan@imgtec.com>
To: <linux-mips@linux-mips.org>
Cc: Guenter Roeck <linux@roeck-us.net>,
	James Hogan <james.hogan@imgtec.com>,
	Ralf Baechle <ralf@linux-mips.org>,
	Justin Chen <justin.chen@broadcom.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	<bcm-kernel-feedback-list@broadcom.com>
Subject: [PATCH] MIPS: Fix cacheinfo overflow
Date: Fri, 10 Feb 2017 23:01:20 +0000	[thread overview]
Message-ID: <20170210230120.21588-1-james.hogan@imgtec.com> (raw)
In-Reply-To: <20170208234523.GA13263@roeck-us.net>

The recently added MIPS cacheinfo support used a macro populate_cache()
to populate the cacheinfo structures depending on which caches are
present. However the macro contains multiple statements without
enclosing them in a do {} while (0) loop, so the L2 and L3 cache
conditionals in populate_cache_leaves() only conditionalised the first
statement in the macro.

This overflows the buffer allocated by detect_cache_attributes(),
resulting in boot failures under QEMU where neither the L2 or L2 caches
are present.

Enclose the macro statements in a do {} while (0) block to keep the
whole macro inside the conditionals.

Fixes: ef462f3b64e9 ("MIPS: Add cacheinfo support")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Justin Chen <justin.chen@broadcom.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: bcm-kernel-feedback-list@broadcom.com
---
 arch/mips/kernel/cacheinfo.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index a92bbbae969b..97d5239ca47b 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -17,6 +17,7 @@
 
 /* Populates leaf and increments to next leaf */
 #define populate_cache(cache, leaf, c_level, c_type)		\
+do {								\
 	leaf->type = c_type;					\
 	leaf->level = c_level;					\
 	leaf->coherency_line_size = c->cache.linesz;		\
@@ -24,7 +25,8 @@
 	leaf->ways_of_associativity = c->cache.ways;		\
 	leaf->size = c->cache.linesz * c->cache.sets *		\
 		c->cache.ways;					\
-	leaf++;
+	leaf++;							\
+} while (0)
 
 static int __init_cache_level(unsigned int cpu)
 {
-- 
2.11.0

WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@imgtec.com>
To: linux-mips@linux-mips.org
Cc: Guenter Roeck <linux@roeck-us.net>,
	James Hogan <james.hogan@imgtec.com>,
	Ralf Baechle <ralf@linux-mips.org>,
	Justin Chen <justin.chen@broadcom.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	bcm-kernel-feedback-list@broadcom.com
Subject: [PATCH] MIPS: Fix cacheinfo overflow
Date: Fri, 10 Feb 2017 23:01:20 +0000	[thread overview]
Message-ID: <20170210230120.21588-1-james.hogan@imgtec.com> (raw)
Message-ID: <20170210230120.egCf57m0byJQ68kqkT4P-YI5J7L5FX_rjzcfcp6jTkE@z> (raw)
In-Reply-To: <20170208234523.GA13263@roeck-us.net>

The recently added MIPS cacheinfo support used a macro populate_cache()
to populate the cacheinfo structures depending on which caches are
present. However the macro contains multiple statements without
enclosing them in a do {} while (0) loop, so the L2 and L3 cache
conditionals in populate_cache_leaves() only conditionalised the first
statement in the macro.

This overflows the buffer allocated by detect_cache_attributes(),
resulting in boot failures under QEMU where neither the L2 or L2 caches
are present.

Enclose the macro statements in a do {} while (0) block to keep the
whole macro inside the conditionals.

Fixes: ef462f3b64e9 ("MIPS: Add cacheinfo support")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Justin Chen <justin.chen@broadcom.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: bcm-kernel-feedback-list@broadcom.com
---
 arch/mips/kernel/cacheinfo.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index a92bbbae969b..97d5239ca47b 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -17,6 +17,7 @@
 
 /* Populates leaf and increments to next leaf */
 #define populate_cache(cache, leaf, c_level, c_type)		\
+do {								\
 	leaf->type = c_type;					\
 	leaf->level = c_level;					\
 	leaf->coherency_line_size = c->cache.linesz;		\
@@ -24,7 +25,8 @@
 	leaf->ways_of_associativity = c->cache.ways;		\
 	leaf->size = c->cache.linesz * c->cache.sets *		\
 		c->cache.ways;					\
-	leaf++;
+	leaf++;							\
+} while (0)
 
 static int __init_cache_level(unsigned int cpu)
 {
-- 
2.11.0

  parent reply	other threads:[~2017-02-10 23:01 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-08 23:45 Crash in -next due to 'MIPS: Add cacheinfo support' Guenter Roeck
2017-02-10  0:01 ` Justin Chen
2017-02-10  4:50   ` Guenter Roeck
2017-02-10  9:40     ` James Hogan
2017-02-10  9:40       ` James Hogan
2017-02-10 10:39       ` James Hogan
2017-02-10 10:39         ` James Hogan
2017-02-10 17:46         ` Guenter Roeck
2017-02-10 19:15           ` Florian Fainelli
2017-02-10 22:11             ` Guenter Roeck
2017-02-10 22:39               ` James Hogan
2017-02-10 22:39                 ` James Hogan
2017-02-10 22:43                 ` Florian Fainelli
2017-02-10 22:48                 ` Guenter Roeck
2017-02-10 13:30       ` Guenter Roeck
2017-02-10 23:01 ` James Hogan [this message]
2017-02-10 23:01   ` [PATCH] MIPS: Fix cacheinfo overflow James Hogan
2017-02-10 23:10   ` Justin Chen
2017-02-10 23:44     ` James Hogan
2017-02-10 23:44       ` James Hogan
2017-02-10 23:48       ` Justin Chen
2017-02-11  1:25   ` Guenter Roeck

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