Re: [PATCH 1/4] MIPS16e2: Identify ASE presence

[James Hogan <james.hogan@imgtec.com>]

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On Tue, May 23, 2017 at 01:37:05PM +0100, Maciej W. Rozycki wrote:
> Identify the presence of the MIPS16e2 ASE as per the architecture 
> specification[1], by checking for CP0 Config5.CA2 bit being 1[2].
> 
> References:
> 
> [1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
>     Extension Technical Reference Manual", Imagination Technologies
>     Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016,
>     Section 1.2 "Software Detection of the ASE", p. 5
> 
> [2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
>     Imagination Technologies Ltd., Document Number: MD00904, Revision 
>     02.01, June 15, 2016, Section 2.2.1.6 "Device Configuration 5 -- 
>     Config5 (CP0 Register 16, Select 5)", pp. 71-72
> 
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>

Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> ---
>  NB the designation of the CP0 Config5.CA2 bit has not yet made it to a 
> published release of the architecture specification, so the definition in 
> the interAptiv MR2 core manual will have to do for the time being.
> 
>   Maciej
> 
> linux-mips16e2-ase-ident.diff
> Index: linux-sfr-test/arch/mips/include/asm/cpu-features.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/cpu-features.h	2017-05-22 22:42:15.904852000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/cpu-features.h	2017-05-22 22:48:43.819622000 +0100
> @@ -138,6 +138,9 @@
>  #ifndef cpu_has_mips16
>  #define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
>  #endif
> +#ifndef cpu_has_mips16e2
> +#define cpu_has_mips16e2	(cpu_data[0].ases & MIPS_ASE_MIPS16E2)
> +#endif
>  #ifndef cpu_has_mdmx
>  #define cpu_has_mdmx		(cpu_data[0].ases & MIPS_ASE_MDMX)
>  #endif
> Index: linux-sfr-test/arch/mips/include/asm/cpu.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/cpu.h	2017-05-22 22:42:15.905865000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/cpu.h	2017-05-22 22:48:43.827611000 +0100
> @@ -430,5 +430,6 @@ enum cpu_type_enum {
>  #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
>  #define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
>  #define MIPS_ASE_DSP3		0x00000200 /* Signal Processing ASE Rev 3*/
> +#define MIPS_ASE_MIPS16E2	0x00000400 /* MIPS16e2 */
>  
>  #endif /* _ASM_CPU_H */
> Index: linux-sfr-test/arch/mips/include/asm/mipsregs.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mipsregs.h	2017-05-22 22:42:16.046860000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mipsregs.h	2017-05-22 22:48:43.766613000 +0100
> @@ -652,6 +652,7 @@
>  #define MIPS_CONF5_SBRI		(_ULCAST_(1) << 6)
>  #define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
>  #define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
> +#define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
>  #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
>  #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
>  #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
> Index: linux-sfr-test/arch/mips/kernel/cpu-probe.c
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/cpu-probe.c	2017-05-22 22:41:59.908735000 +0100
> +++ linux-sfr-test/arch/mips/kernel/cpu-probe.c	2017-05-22 22:48:43.798611000 +0100
> @@ -861,6 +861,8 @@ static inline unsigned int decode_config
>  		c->options |= MIPS_CPU_MVH;
>  	if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
>  		c->options |= MIPS_CPU_VP;
> +	if (config5 & MIPS_CONF5_CA2)
> +		c->ases |= MIPS_ASE_MIPS16E2;
>  
>  	return config5 & MIPS_CONF_M;
>  }

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