From: John Crispin <john@phrozen.org>
To: James Hogan <jhogan@kernel.org>, Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, Felix Fietkau <nbd@nbd.name>
Subject: [PATCH 17/25] MIPS: ath79: make specifying the reference clock in DT optional
Date: Mon, 25 Jun 2018 19:15:41 +0200 [thread overview]
Message-ID: <20180625171549.4618-18-john@phrozen.org> (raw)
In-Reply-To: <20180625171549.4618-1-john@phrozen.org>
From: Felix Fietkau <nbd@nbd.name>
It can be autodetected for many SoCs using the strapping options.
If the clock is specified in DT, the autodetected value is ignored
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++--------------------------
1 file changed, 40 insertions(+), 44 deletions(-)
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 984b3cdebd22..6262253622b3 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
return clk;
}
+static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
+{
+ struct clk *clk = clks[ATH79_CLK_REF];
+
+ if (clk)
+ rate = clk_get_rate(clk);
+ else
+ clk = ath79_set_clk(ATH79_CLK_REF, rate);
+
+ return rate;
+}
+
static void __init ar71xx_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(void __iomem *pll_base)
u32 freq;
u32 div;
- ref_rate = AR71XX_BASE_FREQ;
+ ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(void __iomem *pll_base)
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
ahb_rate = cpu_rate / div;
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
}
-static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+static void __init ar724x_clocks_init(void __iomem *pll_base)
{
- u32 pll;
u32 mult, div, ddr_div, ahb_div;
+ u32 pll;
+
+ ath79_setup_ref_clk(AR71XX_BASE_FREQ);
pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
}
-static void __init ar724x_clocks_init(void __iomem *pll_base)
-{
- struct clk *ref_clk;
-
- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
-
- ar724x_clk_init(ref_clk, pll_base);
-}
-
-static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+static void __init ar933x_clocks_init(void __iomem *pll_base)
{
+ unsigned long ref_rate;
u32 clock_ctrl;
u32 ref_div;
u32 ninit_mul;
@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
u32 cpu_div;
u32 ddr_div;
u32 ahb_div;
+ u32 t;
+
+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+ ref_rate = (40 * 1000 * 1000);
+ else
+ ref_rate = (25 * 1000 * 1000);
+
+ ath79_setup_ref_clk(ref_rate);
clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
ref_div * out_div * ahb_div);
}
-static void __init ar933x_clocks_init(void __iomem *pll_base)
-{
- struct clk *ref_clk;
- unsigned long ref_rate;
- u32 t;
-
- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
- ref_rate = (40 * 1000 * 1000);
- else
- ref_rate = (25 * 1000 * 1000);
-
- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
-
- ar9330_clk_init(ref_clk, ath79_pll_base);
-}
-
static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
u32 frac, u32 out_div)
{
@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(void __iomem *pll_base)
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(void __iomem *pll_base)
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(void __iomem *pll_base)
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(void __iomem *pll_base)
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
void __iomem *pll_base;
ref_clk = of_clk_get(np, 0);
- if (IS_ERR(ref_clk)) {
- pr_err("%pOF: of_clk_get failed\n", np);
- goto err;
- }
+ if (!IS_ERR(ref_clk))
+ clks[ATH79_CLK_REF] = ref_clk;
pll_base = of_iomap(np, 0);
if (!pll_base) {
@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
}
if (of_device_is_compatible(np, "qca,ar9130-pll"))
- ar724x_clk_init(ref_clk, pll_base);
+ ar724x_clocks_init(pll_base);
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
- ar9330_clk_init(ref_clk, pll_base);
+ ar933x_clocks_init(pll_base);
else {
pr_err("%pOF: could not find any appropriate clk_init()\n", np);
goto err_iounmap;
@@ -714,9 +713,6 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
err_clk:
clk_put(ref_clk);
-
-err:
- return;
}
CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
--
2.11.0
next prev parent reply other threads:[~2018-06-25 17:27 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-25 17:15 [PATCH 00/25] MIPS: ath79: convert target to pure OF John Crispin
2018-06-25 17:15 ` [PATCH 01/25] MIPS: ath79: add lots of missing registers John Crispin
2018-06-27 22:57 ` Paul Burton
2018-06-25 17:15 ` [PATCH 02/25] MIPS: ath79: add support for QCA953x QCA956x TP9343 John Crispin
2018-06-27 22:55 ` Paul Burton
2018-06-25 17:15 ` [PATCH 03/25] MIPS: ath79: select the PINCTRL subsystem John Crispin
2018-06-25 17:15 ` [PATCH 04/25] MIPS: ath79: fix register address in ath79_ddr_wb_flush() John Crispin
2018-06-28 18:51 ` Paul Burton
2018-06-28 20:03 ` John Crispin
2018-06-25 17:15 ` [PATCH 05/25] MIPS: ath79: Avoid using unitialized 'reg' variable John Crispin
2018-06-27 23:05 ` Paul Burton
2018-06-25 17:15 ` [PATCH 06/25] MIPS: ath79: fix system restart John Crispin
2018-06-25 17:15 ` [PATCH 07/25] MIPS: ath79: finetune cpu-overrides John Crispin
2018-06-25 17:15 ` [PATCH 08/25] MIPS: ath79: enable uart during early_prink John Crispin
2018-06-25 17:15 ` [PATCH 09/25] MIPS: ath79: get PCIe controller out of reset John Crispin
2018-06-25 17:15 ` [PATCH 10/25] dt-bindings: PCI: qcom,ar7100: adds binding doc John Crispin
2018-06-25 18:06 ` Sergei Shtylyov
2018-06-26 7:13 ` John Crispin
2018-07-03 22:05 ` Rob Herring
2018-06-25 17:15 ` [PATCH 11/25] MIPS: pci-ar71xx: convert to OF John Crispin
2018-06-25 17:15 ` [PATCH 12/25] dt-bindings: PCI: qcom,ar7240: adds binding doc John Crispin
2018-07-03 22:08 ` Rob Herring
2018-06-25 17:15 ` [PATCH 13/25] MIPS: pci-ar724x: convert to OF John Crispin
2018-06-25 17:15 ` [PATCH 14/25] MIPS: ath79: add helpers for setting clocks and expose the ref clock John Crispin
2018-06-25 17:15 ` [PATCH 15/25] MIPS: ath79: move legacy "wdt" and "uart" clock aliases out of soc init John Crispin
2018-06-25 17:15 ` [PATCH 16/25] MIPS: ath79: pass PLL base to clock init functions John Crispin
2018-06-25 17:15 ` John Crispin [this message]
2018-06-25 17:15 ` [PATCH 18/25] MIPS: ath79: support setting up clock via DT on all SoC types John Crispin
2018-06-25 17:15 ` [PATCH 19/25] MIPS: ath79: export switch MDIO reference clock John Crispin
2018-06-25 17:15 ` [PATCH 20/25] MIPS: ath79: drop legacy IRQ code John Crispin
2018-06-25 17:15 ` [PATCH 21/25] MIPS: ath79: drop machfiles John Crispin
2018-06-25 17:15 ` [PATCH 22/25] MIPS: ath79: drop legacy pci code John Crispin
2018-06-25 17:15 ` [PATCH 23/25] MIPS: ath79: drop platform device registration code John Crispin
2018-06-25 17:15 ` [PATCH 24/25] MIPS: ath79: drop !OF clock code John Crispin
2018-06-25 17:15 ` [PATCH 25/25] MIPS: ath79: sanitize symbols John Crispin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180625171549.4618-18-john@phrozen.org \
--to=john@phrozen.org \
--cc=jhogan@kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=nbd@nbd.name \
--cc=ralf@linux-mips.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox