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* [PATCH 0/5] MIPS: LLVM toolchain support for more CPUs
@ 2023-04-07 10:27 Jiaxun Yang
  2023-04-07 10:27 ` [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
                   ` (4 more replies)
  0 siblings, 5 replies; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-07 10:27 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

This patchset is to add toolchain feature detection for most MIPS CPUs
by adding more toolchain feature detections and fixing -march CFLAGS.

Thanks
Jiaxun

Jiaxun Yang (5):
  MIPS: Move various toolchain ASE check to Kconfig
  MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  MIPS: Detect toolchain support of workarounds in Kconfig
  MIPS: Detect toolchain support of o32 ABI with 64 bit CPU
  MIPS: Fallback CPU -march CFLAG to ISA level if unsupported

 arch/mips/Kconfig                | 66 +++++++++++++++++++++++++++++---
 arch/mips/Makefile               | 65 +++++++++++--------------------
 arch/mips/cavium-octeon/Kconfig  |  1 +
 arch/mips/crypto/crc32-mips.c    |  4 +-
 arch/mips/include/asm/asmmacro.h |  8 ++--
 arch/mips/include/asm/ginvt.h    |  2 +-
 arch/mips/include/asm/mipsregs.h | 10 ++---
 arch/mips/include/asm/msa.h      |  4 +-
 8 files changed, 98 insertions(+), 62 deletions(-)

-- 
2.39.2 (Apple Git-143)


^ permalink raw reply	[flat|nested] 15+ messages in thread
* [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig
  2023-04-07 10:27 [PATCH 0/5] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
@ 2023-04-07 10:27 ` Jiaxun Yang
  2023-04-07 18:57   ` Nathan Chancellor
  2023-04-07 10:27 ` [PATCH 2/5] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Jiaxun Yang
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-07 10:27 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

Use Kconfig to perform Kconfig toolchain feature check, so we will
be able to have toolchain feature availablility information in Kconfig
to guard relevant options.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig                | 27 +++++++++++++++++++++++++++
 arch/mips/Makefile               | 29 +++--------------------------
 arch/mips/crypto/crc32-mips.c    |  4 ++--
 arch/mips/include/asm/asmmacro.h |  8 ++++----
 arch/mips/include/asm/ginvt.h    |  2 +-
 arch/mips/include/asm/mipsregs.h | 10 +++++-----
 arch/mips/include/asm/msa.h      |  4 ++--
 7 files changed, 44 insertions(+), 40 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 770d098b11bf..c52401c155a4 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3157,6 +3157,12 @@ config MIPS32_N32
 
 	  If unsure, say N.
 
+config CC_HAS_SMARTMIPS
+	def_bool $(cc-option,-mmicromips)
+
+config CC_HAS_MICROMIPS
+	def_bool $(cc-option,-mmicromips)
+
 config CC_HAS_MNO_BRANCH_LIKELY
 	def_bool y
 	depends on $(cc-option,-mno-branch-likely)
@@ -3165,6 +3171,27 @@ config CC_HAS_MNO_BRANCH_LIKELY
 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
 	def_bool y if CC_IS_CLANG
 
+config AS_HAS_MSA
+	def_bool $(cc-option,-Wa$(comma)-mmsa)
+
+config AS_HAS_VIRT
+	def_bool $(cc-option,-Wa$(comma)-mvirt)
+
+# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which
+# only warns
+config AS_HAS_XPA
+	def_bool $(cc-option,-Wa$(comma)-mxpa) if !CPU_MICROMIPS
+	def_bool $(cc-option,-mmicromips -Wa$(comma)-fatal-warnings -Wa$(comma)-mxpa) if CPU_MICROMIPS
+
+config AS_HAS_CRC
+	def_bool $(cc-option,-Wa$(comma)-mcrc)
+
+config AS_HAS_DSP
+	def_bool $(cc-option,-Wa$(comma)-mdsp)
+
+config AS_HAS_GINV
+	def_bool $(cc-option,-Wa$(comma)-mginv)
+
 menu "Power management options"
 
 config ARCH_HIBERNATION_POSSIBLE
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index a7a4ee66a9d3..3aa0f9d4ceb6 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -233,32 +233,9 @@ cflags-$(CONFIG_CPU_LOONGSON64)	+= $(call as-option,-Wa$(comma)-mno-fix-loongson
 # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
 # been fixed properly.
 mips-cflags				:= $(cflags-y)
-ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y)
-smartmips-ase				:= $(call cc-option-yn,$(mips-cflags) -msmartmips)
-cflags-$(smartmips-ase)			+= -msmartmips -Wa,--no-warn
-endif
-ifeq ($(CONFIG_CPU_MICROMIPS),y)
-micromips-ase				:= $(call cc-option-yn,$(mips-cflags) -mmicromips)
-cflags-$(micromips-ase)			+= -mmicromips
-endif
-ifeq ($(CONFIG_CPU_HAS_MSA),y)
-toolchain-msa				:= $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa)
-cflags-$(toolchain-msa)			+= -DTOOLCHAIN_SUPPORTS_MSA
-endif
-toolchain-virt				:= $(call cc-option-yn,$(mips-cflags) -mvirt)
-cflags-$(toolchain-virt)		+= -DTOOLCHAIN_SUPPORTS_VIRT
-# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which
-# only warns
-xpa-cflags-y				:= $(mips-cflags)
-xpa-cflags-$(micromips-ase)		+= -mmicromips -Wa$(comma)-fatal-warnings
-toolchain-xpa				:= $(call cc-option-yn,$(xpa-cflags-y) -mxpa)
-cflags-$(toolchain-xpa)			+= -DTOOLCHAIN_SUPPORTS_XPA
-toolchain-crc				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)
-cflags-$(toolchain-crc)			+= -DTOOLCHAIN_SUPPORTS_CRC
-toolchain-dsp				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mdsp)
-cflags-$(toolchain-dsp)			+= -DTOOLCHAIN_SUPPORTS_DSP
-toolchain-ginv				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mginv)
-cflags-$(toolchain-ginv)		+= -DTOOLCHAIN_SUPPORTS_GINV
+
+cflags-$(CONFIG_CPU_HAS_SMARTMIPS)	+= -msmartmips -Wa,--no-warn
+cflags-$(CONFIG_CPU_MICROMIPS)		+= -mmicromips
 
 #
 # Firmware support
diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c
index 3e4f5ba104f8..54bbcfae06d5 100644
--- a/arch/mips/crypto/crc32-mips.c
+++ b/arch/mips/crypto/crc32-mips.c
@@ -27,7 +27,7 @@ enum crc_type {
 	crc32c,
 };
 
-#ifndef TOOLCHAIN_SUPPORTS_CRC
+#ifndef CONFIG_AS_HAS_CRC
 #define _ASM_SET_CRC(OP, SZ, TYPE)					  \
 _ASM_MACRO_3R(OP, rt, rs, rt2,						  \
 	".ifnc	\\rt, \\rt2\n\t"					  \
@@ -38,7 +38,7 @@ _ASM_MACRO_3R(OP, rt, rs, rt2,						  \
 	_ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) |	  \
 			  ((SZ) << 14) | ((TYPE) << 3)))
 #define _ASM_UNSET_CRC(op, SZ, TYPE) ".purgem " #op "\n\t"
-#else /* !TOOLCHAIN_SUPPORTS_CRC */
+#else /* !CONFIG_AS_HAS_CRC */
 #define _ASM_SET_CRC(op, SZ, TYPE) ".set\tcrc\n\t"
 #define _ASM_UNSET_CRC(op, SZ, TYPE)
 #endif
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 067a635d3bc8..74c2dedc55b4 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -239,7 +239,7 @@
 	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 	.endm
 
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifdef CONFIG_AS_HAS_MSA
 	.macro	_cfcmsa	rd, cs
 	.set	push
 	.set	mips32r2
@@ -507,7 +507,7 @@
 	.endm
 #endif
 
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifdef CONFIG_AS_HAS_MSA
 #define FPR_BASE_OFFS	THREAD_FPR0
 #define FPR_BASE	$1
 #else
@@ -518,7 +518,7 @@
 	.macro	msa_save_all	thread
 	.set	push
 	.set	noat
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifdef CONFIG_AS_HAS_MSA
 	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
 #endif
 	st_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
@@ -565,7 +565,7 @@
 	.set	hardfloat
 	lw	$1, THREAD_MSA_CSR(\thread)
 	_ctcmsa	MSA_CSR, $1
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifdef CONFIG_AS_HAS_MSA
 	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
 #endif
 	ld_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
diff --git a/arch/mips/include/asm/ginvt.h b/arch/mips/include/asm/ginvt.h
index 87b2974ffc53..20244a622552 100644
--- a/arch/mips/include/asm/ginvt.h
+++ b/arch/mips/include/asm/ginvt.h
@@ -10,7 +10,7 @@ enum ginvt_type {
 	GINVT_MMID,
 };
 
-#ifdef TOOLCHAIN_SUPPORTS_GINV
+#ifdef CONFIG_AS_HAS_GINV
 # define _ASM_SET_GINV	".set	ginv\n"
 # define _ASM_UNSET_GINV
 #else
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2d53704d9f24..8f0ebc399338 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1604,7 +1604,7 @@ do {									\
 	local_irq_restore(__flags);					\
 } while (0)
 
-#ifndef TOOLCHAIN_SUPPORTS_XPA
+#ifndef CONFIG_AS_HAS_XPA
 #define _ASM_SET_MFHC0							\
 	_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,				\
 			 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)	\
@@ -1615,7 +1615,7 @@ do {									\
 			 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)	\
 			 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11))
 #define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t"
-#else	/* !TOOLCHAIN_SUPPORTS_XPA */
+#else	/* !CONFIG_AS_HAS_XPA */
 #define _ASM_SET_MFHC0 ".set\txpa\n\t"
 #define _ASM_SET_MTHC0 ".set\txpa\n\t"
 #define _ASM_UNSET_MFHC0
@@ -2040,7 +2040,7 @@ do {									\
  * Macros to access the guest system control coprocessor
  */
 
-#ifndef TOOLCHAIN_SUPPORTS_VIRT
+#ifndef CONFIG_AS_HAS_VIRT
 #define _ASM_SET_MFGC0							\
 	_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,				\
 			 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)	\
@@ -2077,7 +2077,7 @@ do {									\
 #define __tlbginvf()							\
 		_ASM_INSN_IF_MIPS(0x4200000c)				\
 		_ASM_INSN32_IF_MM(0x0000517c)
-#else	/* !TOOLCHAIN_SUPPORTS_VIRT */
+#else	/* !CONFIG_AS_HAS_VIRT */
 #define _ASM_SET_VIRT ".set\tvirt\n\t"
 #define _ASM_SET_MFGC0	_ASM_SET_VIRT
 #define _ASM_SET_DMFGC0	_ASM_SET_VIRT
@@ -2395,7 +2395,7 @@ do {									\
 	: : "r" (val));							\
 } while (0)
 
-#ifdef TOOLCHAIN_SUPPORTS_DSP
+#ifdef CONFIG_AS_HAS_DSP
 #define rddsp(mask)							\
 ({									\
 	unsigned int __dspctl;						\
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
index 236a49ee2e3e..a9ca57e3f780 100644
--- a/arch/mips/include/asm/msa.h
+++ b/arch/mips/include/asm/msa.h
@@ -156,7 +156,7 @@ static inline void init_msa_upper(void)
 	_init_msa_upper();
 }
 
-#ifndef TOOLCHAIN_SUPPORTS_MSA
+#ifndef CONFIG_AS_HAS_MSA
 /*
  * Define assembler macros using .word for the c[ft]cmsa instructions in order
  * to allow compilation with toolchains that do not support MSA. Once all
@@ -173,7 +173,7 @@ static inline void init_msa_upper(void)
 		      _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6)	\
 		      _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6))
 #define _ASM_UNSET_CTCMSA ".purgem ctcmsa\n\t"
-#else /* TOOLCHAIN_SUPPORTS_MSA */
+#else /* CONFIG_AS_HAS_MSA */
 #define _ASM_SET_CFCMSA						\
 		".set\tfp=64\n\t"				\
 		".set\tmsa\n\t"
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 2/5] MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  2023-04-07 10:27 [PATCH 0/5] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
  2023-04-07 10:27 ` [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
@ 2023-04-07 10:27 ` Jiaxun Yang
  2023-04-07 22:08   ` Nick Desaulniers
  2023-04-07 10:27 ` [PATCH 3/5] MIPS: Detect toolchain support of workarounds in Kconfig Jiaxun Yang
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-07 10:27 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

microMIPS smartMIPS kernel can only be compiled if they are supported
by toolchain.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c52401c155a4..9e9de2b62f28 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2360,7 +2360,7 @@ config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
 	  Select this if you want neither microMIPS nor SmartMIPS support
 
 config CPU_HAS_SMARTMIPS
-	depends on SYS_SUPPORTS_SMARTMIPS
+	depends on SYS_SUPPORTS_SMARTMIPS && CC_HAS_SMARTMIPS
 	bool "SmartMIPS"
 	help
 	  SmartMIPS is a extension of the MIPS32 architecture aimed at
@@ -2372,7 +2372,7 @@ config CPU_HAS_SMARTMIPS
 	  here.
 
 config CPU_MICROMIPS
-	depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
+	depends on 32BIT && SYS_SUPPORTS_MICROMIPS && CC_HAS_MICROMIPS && !CPU_MIPSR6
 	bool "microMIPS"
 	help
 	  When this option is enabled the kernel will be built using the
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 3/5] MIPS: Detect toolchain support of workarounds in Kconfig
  2023-04-07 10:27 [PATCH 0/5] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
  2023-04-07 10:27 ` [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
  2023-04-07 10:27 ` [PATCH 2/5] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Jiaxun Yang
@ 2023-04-07 10:27 ` Jiaxun Yang
  2023-04-07 22:15   ` Nick Desaulniers
  2023-04-07 10:27 ` [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Jiaxun Yang
  2023-04-07 10:27 ` [PATCH 5/5] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Jiaxun Yang
  4 siblings, 1 reply; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-07 10:27 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

LLVM toolchain does not support most of workarounds, detect
those supports in Kconfig so we can hide unsupported workarounds
to user.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig               | 28 +++++++++++++++++++++++++---
 arch/mips/Makefile              |  6 +++---
 arch/mips/cavium-octeon/Kconfig |  1 +
 3 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9e9de2b62f28..d896af492da6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -371,9 +371,9 @@ config MACH_DECSTATION
 	select CEVT_R4K if CPU_R4X00
 	select CSRC_IOASIC
 	select CSRC_R4K if CPU_R4X00
-	select CPU_DADDI_WORKAROUNDS if 64BIT
-	select CPU_R4000_WORKAROUNDS if 64BIT
-	select CPU_R4400_WORKAROUNDS if 64BIT
+	imply CPU_DADDI_WORKAROUNDS
+	imply CPU_R4000_WORKAROUNDS
+	imply CPU_R4400_WORKAROUNDS
 	select DMA_NONCOHERENT
 	select NO_IOPORT_MAP
 	select IRQ_MIPS_CPU
@@ -1723,6 +1723,7 @@ config CPU_JUMP_WORKAROUNDS
 config CPU_LOONGSON2F_WORKAROUNDS
 	bool "Loongson 2F Workarounds"
 	default y
+	depends on AS_HAS_NOP_WORKAROUNDS && AS_HAS_JUMP_WORKAROUNDS
 	select CPU_NOP_WORKAROUNDS
 	select CPU_JUMP_WORKAROUNDS
 	help
@@ -2456,6 +2457,7 @@ config CPU_HAS_SYNC
 #   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
 config CPU_DADDI_WORKAROUNDS
 	bool
+	depends on CPU_R4X00_BUGS64 && CC_HAS_DADDI_WORKAROUNDS
 
 # Work around certain R4000 CPU errata (as implemented by GCC):
 #
@@ -2477,6 +2479,7 @@ config CPU_DADDI_WORKAROUNDS
 #   erratum #52
 config CPU_R4000_WORKAROUNDS
 	bool
+	depends on CPU_R4X00_BUGS64 && CC_HAS_R4000_WORKAROUNDS
 	select CPU_R4400_WORKAROUNDS
 
 # Work around certain R4400 CPU errata (as implemented by GCC):
@@ -2487,6 +2490,7 @@ config CPU_R4000_WORKAROUNDS
 #   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
 config CPU_R4400_WORKAROUNDS
 	bool
+	depends on CPU_R4X00_BUGS64 && CC_HAS_R4400_WORKAROUNDS
 
 config CPU_R4X00_BUGS64
 	bool
@@ -3167,6 +3171,15 @@ config CC_HAS_MNO_BRANCH_LIKELY
 	def_bool y
 	depends on $(cc-option,-mno-branch-likely)
 
+config CC_HAS_R4000_WORKAROUNDS
+	def_bool $(cc-option,-mfix-r4000)
+
+config CC_HAS_R4400_WORKAROUNDS
+	def_bool $(cc-option,-mfix-r4400)
+
+config CC_HAS_DADDI_WORKAROUNDS
+	def_bool $(cc-option,-mno-daddi)
+
 # https://github.com/llvm/llvm-project/issues/61045
 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
 	def_bool y if CC_IS_CLANG
@@ -3192,6 +3205,15 @@ config AS_HAS_DSP
 config AS_HAS_GINV
 	def_bool $(cc-option,-Wa$(comma)-mginv)
 
+config AS_HAS_CN63XXP1_WORKAROUNDS
+	def_bool $(cc-option,-Wa$(comma)-mfix-cn63xxp1)
+
+config AS_HAS_NOP_WORKAROUNDS
+	def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-nop)
+
+config AS_HAS_JUMP_WORKAROUNDS
+	def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-jump)
+
 menu "Power management options"
 
 config ARCH_HIBERNATION_POSSIBLE
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 3aa0f9d4ceb6..344fe5f00f7b 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -193,9 +193,9 @@ cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2
 endif
 cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi)
 
-cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)
-cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)
-cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= $(call cc-option,-mno-daddi,)
+cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= -mfix-r4000
+cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= -mfix-r4400
+cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= -mno-daddi
 ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
 cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop
 cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 450e979ef5d9..38c9dc89cd5f 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -4,6 +4,7 @@ if CPU_CAVIUM_OCTEON
 config CAVIUM_CN63XXP1
 	bool "Enable CN63XXP1 errata workarounds"
 	default "n"
+	depends on AS_HAS_CN63XXP1_WORKAROUNDS
 	help
 	  The CN63XXP1 chip requires build time workarounds to
 	  function reliably, select this option to enable them.  These
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU
  2023-04-07 10:27 [PATCH 0/5] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
                   ` (2 preceding siblings ...)
  2023-04-07 10:27 ` [PATCH 3/5] MIPS: Detect toolchain support of workarounds in Kconfig Jiaxun Yang
@ 2023-04-07 10:27 ` Jiaxun Yang
  2023-04-07 22:19   ` Nick Desaulniers
  2023-04-07 10:27 ` [PATCH 5/5] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Jiaxun Yang
  4 siblings, 1 reply; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-07 10:27 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

LLVM is not happy with using o32 ABI on 64 bit CPU, thus build 32 bit
kernel is unsupported.

Detect this in Kconfig to prevent user select 32 bit kernel with
unsupported toolchain.

Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d896af492da6..5e399a5ac3b3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2016,6 +2016,7 @@ choice
 config 32BIT
 	bool "32-bit kernel"
 	depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
+	depends on CC_HAS_O32_ABI
 	select TRAD_SIGNALS
 	help
 	  Select this option if you want to build a 32-bit kernel.
@@ -3136,7 +3137,7 @@ config COMPAT
 
 config MIPS32_O32
 	bool "Kernel support for o32 binaries"
-	depends on 64BIT
+	depends on 64BIT && CC_HAS_O32_ABI
 	select ARCH_WANT_OLD_COMPAT_IPC
 	select COMPAT
 	select MIPS32_COMPAT
@@ -3184,6 +3185,10 @@ config CC_HAS_DADDI_WORKAROUNDS
 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
 	def_bool y if CC_IS_CLANG
 
+config CC_HAS_O32_ABI
+	def_bool y
+	depends on !CPU_SUPPORTS_64BIT_KERNEL || $(cc-option,-march=mips3 -mabi=32)
+
 config AS_HAS_MSA
 	def_bool $(cc-option,-Wa$(comma)-mmsa)
 
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 5/5] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-07 10:27 [PATCH 0/5] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
                   ` (3 preceding siblings ...)
  2023-04-07 10:27 ` [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Jiaxun Yang
@ 2023-04-07 10:27 ` Jiaxun Yang
  2023-04-07 22:23   ` Nick Desaulniers
  4 siblings, 1 reply; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-07 10:27 UTC (permalink / raw)
  To: linux-mips; +Cc: llvm, tsbogend, ndesaulniers, nathan, Jiaxun Yang

LLVM does not implement some of -march option. However those march
does not provide any special functionality in most cases, they just
serves as compiler's tuning target.

Fallback -march CFLAG to ISA level if unsupported by toolchain so
we can get those kernel to build with LLVM.

Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Makefile | 30 +++++++++++++++++-------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 344fe5f00f7b..eab6abeaa45c 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -148,10 +148,10 @@ cflags-y += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
 #
 # CPU-dependent compiler/assembler options for optimization.
 #
-cflags-$(CONFIG_CPU_R3000)	+= -march=r3000
-cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
-cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap
-cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
+cflags-$(CONFIG_CPU_R3000)	+= $(call cc-option,-march=r3000,-march=mips1)
+cflags-$(CONFIG_CPU_R4300)	+= $(call cc-option,-march=r4300,-march=mips3) -Wa,--trap
+cflags-$(CONFIG_CPU_R4X00)	+= $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
+cflags-$(CONFIG_CPU_TX49XX)	+= $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R1)	+= -march=mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2)	+= -march=mips32r2 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R5)	+= -march=mips32r5 -Wa,--trap -modd-spreg
@@ -160,19 +160,21 @@ cflags-$(CONFIG_CPU_MIPS64_R1)	+= -march=mips64 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R2)	+= -march=mips64r2 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R5)	+= -march=mips64r5 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R6)	+= -march=mips64r6 -Wa,--trap
-cflags-$(CONFIG_CPU_P5600)	+= -march=p5600 -Wa,--trap -modd-spreg
-cflags-$(CONFIG_CPU_R5000)	+= -march=r5000 -Wa,--trap
-cflags-$(CONFIG_CPU_R5500)	+= $(call cc-option,-march=r5500,-march=r5000) \
+cflags-$(CONFIG_CPU_P5600)	+= $(call cc-option,-march=p5600,-march=mips32r5) \
+			-Wa,--trap -modd-spreg
+cflags-$(CONFIG_CPU_R5000)	+= $(call cc-option,-march=r5000,-march=mips4) \
 			-Wa,--trap
-cflags-$(CONFIG_CPU_NEVADA)	+= $(call cc-option,-march=rm5200,-march=r5000) \
+cflags-$(CONFIG_CPU_R5500)	+= $(call cc-option,-march=r5500,-march=mips4) \
 			-Wa,--trap
-cflags-$(CONFIG_CPU_RM7000)	+= $(call cc-option,-march=rm7000,-march=r5000) \
+cflags-$(CONFIG_CPU_NEVADA)	+= $(call cc-option,-march=rm5200,-march=mips4) \
 			-Wa,--trap
-cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1,-march=r5000) \
+cflags-$(CONFIG_CPU_RM7000)	+= $(call cc-option,-march=rm7000,-march=mips4) \
+			-Wa,--trap
+cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1,-march=mips4) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mdmx)
 cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mips3d)
-cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=r8000) \
+cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=mips4) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
 ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
@@ -181,8 +183,10 @@ endif
 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
 cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap
 
-cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2E) += \
+			$(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2F) += \
+			$(call cc-option,-march=loongson2f,-march=mips3) -Wa,--trap
 # Some -march= flags enable MMI instructions, and GCC complains about that
 # support being enabled alongside -msoft-float. Thus explicitly disable MMI.
 cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)
-- 
2.39.2 (Apple Git-143)


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* Re: [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig
  2023-04-07 10:27 ` [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
@ 2023-04-07 18:57   ` Nathan Chancellor
  2023-04-07 22:51     ` Jiaxun Yang
  0 siblings, 1 reply; 15+ messages in thread
From: Nathan Chancellor @ 2023-04-07 18:57 UTC (permalink / raw)
  To: Jiaxun Yang; +Cc: linux-mips, llvm, tsbogend, ndesaulniers

Hi Jiaxun,

On Fri, Apr 07, 2023 at 11:27:17AM +0100, Jiaxun Yang wrote:
> Use Kconfig to perform Kconfig toolchain feature check, so we will
> be able to have toolchain feature availablility information in Kconfig
> to guard relevant options.
> 

First of all, thank you a lot for this series! I applied them on top of
mips-next and my allnoconfig issue appears to be gone. However, with
this change, 32r1{,el}_defconfig is broken for arch/mips/kernel/traps.c.

$ make -skj"$(nproc)" ARCH=mips CROSS_COMPILE=mips-linux-gnu- LLVM=1 LLVM_IAS=0 O=build mrproper 32r1_defconfig arch/mips/kernel/traps.o
...
/tmp/traps-f8ea56.s: Assembler messages:
/tmp/traps-f8ea56.s:8227: Error: `fp=64' used with a 32-bit fpu
/tmp/traps-f8ea56.s:8228: Error: `fp=64' used with a 32-bit fpu
/tmp/traps-f8ea56.s:8228: Warning: the `msa' extension requires MIPS32 revision 2 or greater
clang: error: assembler command failed with exit code 1 (use -v to see invocation)
...

In case it matters:

$ clang --version | head -1
ClangBuiltLinux clang version 16.0.1

$ mips-linux-gnu-as --version | head -1
GNU assembler (GNU Binutils) 2.40

A few comments below, I have not tested anything beyond this.

> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  arch/mips/Kconfig                | 27 +++++++++++++++++++++++++++
>  arch/mips/Makefile               | 29 +++--------------------------
>  arch/mips/crypto/crc32-mips.c    |  4 ++--
>  arch/mips/include/asm/asmmacro.h |  8 ++++----
>  arch/mips/include/asm/ginvt.h    |  2 +-
>  arch/mips/include/asm/mipsregs.h | 10 +++++-----
>  arch/mips/include/asm/msa.h      |  4 ++--
>  7 files changed, 44 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 770d098b11bf..c52401c155a4 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -3157,6 +3157,12 @@ config MIPS32_N32
>  
>  	  If unsure, say N.
>  
> +config CC_HAS_SMARTMIPS
> +	def_bool $(cc-option,-mmicromips)

-msmartmips?

> +
> +config CC_HAS_MICROMIPS
> +	def_bool $(cc-option,-mmicromips)

Neither of these configurations are used in this change. Should they be
moved to the next change in the series?

>  config CC_HAS_MNO_BRANCH_LIKELY
>  	def_bool y
>  	depends on $(cc-option,-mno-branch-likely)
> @@ -3165,6 +3171,27 @@ config CC_HAS_MNO_BRANCH_LIKELY
>  config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>  	def_bool y if CC_IS_CLANG
>  
> +config AS_HAS_MSA
> +	def_bool $(cc-option,-Wa$(comma)-mmsa)
> +
> +config AS_HAS_VIRT
> +	def_bool $(cc-option,-Wa$(comma)-mvirt)
> +
> +# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which
> +# only warns
> +config AS_HAS_XPA
> +	def_bool $(cc-option,-Wa$(comma)-mxpa) if !CPU_MICROMIPS
> +	def_bool $(cc-option,-mmicromips -Wa$(comma)-fatal-warnings -Wa$(comma)-mxpa) if CPU_MICROMIPS
> +
> +config AS_HAS_CRC
> +	def_bool $(cc-option,-Wa$(comma)-mcrc)
> +
> +config AS_HAS_DSP
> +	def_bool $(cc-option,-Wa$(comma)-mdsp)
> +
> +config AS_HAS_GINV
> +	def_bool $(cc-option,-Wa$(comma)-mginv)
> +
>  menu "Power management options"
>  
>  config ARCH_HIBERNATION_POSSIBLE
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index a7a4ee66a9d3..3aa0f9d4ceb6 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -233,32 +233,9 @@ cflags-$(CONFIG_CPU_LOONGSON64)	+= $(call as-option,-Wa$(comma)-mno-fix-loongson
>  # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
>  # been fixed properly.
>  mips-cflags				:= $(cflags-y)
> -ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y)
> -smartmips-ase				:= $(call cc-option-yn,$(mips-cflags) -msmartmips)
> -cflags-$(smartmips-ase)			+= -msmartmips -Wa,--no-warn
> -endif
> -ifeq ($(CONFIG_CPU_MICROMIPS),y)
> -micromips-ase				:= $(call cc-option-yn,$(mips-cflags) -mmicromips)
> -cflags-$(micromips-ase)			+= -mmicromips
> -endif
> -ifeq ($(CONFIG_CPU_HAS_MSA),y)
> -toolchain-msa				:= $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa)
> -cflags-$(toolchain-msa)			+= -DTOOLCHAIN_SUPPORTS_MSA
> -endif
> -toolchain-virt				:= $(call cc-option-yn,$(mips-cflags) -mvirt)
> -cflags-$(toolchain-virt)		+= -DTOOLCHAIN_SUPPORTS_VIRT
> -# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which
> -# only warns
> -xpa-cflags-y				:= $(mips-cflags)
> -xpa-cflags-$(micromips-ase)		+= -mmicromips -Wa$(comma)-fatal-warnings
> -toolchain-xpa				:= $(call cc-option-yn,$(xpa-cflags-y) -mxpa)
> -cflags-$(toolchain-xpa)			+= -DTOOLCHAIN_SUPPORTS_XPA
> -toolchain-crc				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)
> -cflags-$(toolchain-crc)			+= -DTOOLCHAIN_SUPPORTS_CRC
> -toolchain-dsp				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mdsp)
> -cflags-$(toolchain-dsp)			+= -DTOOLCHAIN_SUPPORTS_DSP
> -toolchain-ginv				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mginv)
> -cflags-$(toolchain-ginv)		+= -DTOOLCHAIN_SUPPORTS_GINV
> +
> +cflags-$(CONFIG_CPU_HAS_SMARTMIPS)	+= -msmartmips -Wa,--no-warn
> +cflags-$(CONFIG_CPU_MICROMIPS)		+= -mmicromips
>  
>  #
>  # Firmware support
> diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c
> index 3e4f5ba104f8..54bbcfae06d5 100644
> --- a/arch/mips/crypto/crc32-mips.c
> +++ b/arch/mips/crypto/crc32-mips.c
> @@ -27,7 +27,7 @@ enum crc_type {
>  	crc32c,
>  };
>  
> -#ifndef TOOLCHAIN_SUPPORTS_CRC
> +#ifndef CONFIG_AS_HAS_CRC
>  #define _ASM_SET_CRC(OP, SZ, TYPE)					  \
>  _ASM_MACRO_3R(OP, rt, rs, rt2,						  \
>  	".ifnc	\\rt, \\rt2\n\t"					  \
> @@ -38,7 +38,7 @@ _ASM_MACRO_3R(OP, rt, rs, rt2,						  \
>  	_ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) |	  \
>  			  ((SZ) << 14) | ((TYPE) << 3)))
>  #define _ASM_UNSET_CRC(op, SZ, TYPE) ".purgem " #op "\n\t"
> -#else /* !TOOLCHAIN_SUPPORTS_CRC */
> +#else /* !CONFIG_AS_HAS_CRC */
>  #define _ASM_SET_CRC(op, SZ, TYPE) ".set\tcrc\n\t"
>  #define _ASM_UNSET_CRC(op, SZ, TYPE)
>  #endif
> diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
> index 067a635d3bc8..74c2dedc55b4 100644
> --- a/arch/mips/include/asm/asmmacro.h
> +++ b/arch/mips/include/asm/asmmacro.h
> @@ -239,7 +239,7 @@
>  	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
>  	.endm
>  
> -#ifdef TOOLCHAIN_SUPPORTS_MSA
> +#ifdef CONFIG_AS_HAS_MSA
>  	.macro	_cfcmsa	rd, cs
>  	.set	push
>  	.set	mips32r2
> @@ -507,7 +507,7 @@
>  	.endm
>  #endif
>  
> -#ifdef TOOLCHAIN_SUPPORTS_MSA
> +#ifdef CONFIG_AS_HAS_MSA
>  #define FPR_BASE_OFFS	THREAD_FPR0
>  #define FPR_BASE	$1
>  #else
> @@ -518,7 +518,7 @@
>  	.macro	msa_save_all	thread
>  	.set	push
>  	.set	noat
> -#ifdef TOOLCHAIN_SUPPORTS_MSA
> +#ifdef CONFIG_AS_HAS_MSA
>  	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
>  #endif
>  	st_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
> @@ -565,7 +565,7 @@
>  	.set	hardfloat
>  	lw	$1, THREAD_MSA_CSR(\thread)
>  	_ctcmsa	MSA_CSR, $1
> -#ifdef TOOLCHAIN_SUPPORTS_MSA
> +#ifdef CONFIG_AS_HAS_MSA
>  	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
>  #endif
>  	ld_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
> diff --git a/arch/mips/include/asm/ginvt.h b/arch/mips/include/asm/ginvt.h
> index 87b2974ffc53..20244a622552 100644
> --- a/arch/mips/include/asm/ginvt.h
> +++ b/arch/mips/include/asm/ginvt.h
> @@ -10,7 +10,7 @@ enum ginvt_type {
>  	GINVT_MMID,
>  };
>  
> -#ifdef TOOLCHAIN_SUPPORTS_GINV
> +#ifdef CONFIG_AS_HAS_GINV
>  # define _ASM_SET_GINV	".set	ginv\n"
>  # define _ASM_UNSET_GINV
>  #else
> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
> index 2d53704d9f24..8f0ebc399338 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -1604,7 +1604,7 @@ do {									\
>  	local_irq_restore(__flags);					\
>  } while (0)
>  
> -#ifndef TOOLCHAIN_SUPPORTS_XPA
> +#ifndef CONFIG_AS_HAS_XPA
>  #define _ASM_SET_MFHC0							\
>  	_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,				\
>  			 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)	\
> @@ -1615,7 +1615,7 @@ do {									\
>  			 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)	\
>  			 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11))
>  #define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t"
> -#else	/* !TOOLCHAIN_SUPPORTS_XPA */
> +#else	/* !CONFIG_AS_HAS_XPA */
>  #define _ASM_SET_MFHC0 ".set\txpa\n\t"
>  #define _ASM_SET_MTHC0 ".set\txpa\n\t"
>  #define _ASM_UNSET_MFHC0
> @@ -2040,7 +2040,7 @@ do {									\
>   * Macros to access the guest system control coprocessor
>   */
>  
> -#ifndef TOOLCHAIN_SUPPORTS_VIRT
> +#ifndef CONFIG_AS_HAS_VIRT
>  #define _ASM_SET_MFGC0							\
>  	_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,				\
>  			 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)	\
> @@ -2077,7 +2077,7 @@ do {									\
>  #define __tlbginvf()							\
>  		_ASM_INSN_IF_MIPS(0x4200000c)				\
>  		_ASM_INSN32_IF_MM(0x0000517c)
> -#else	/* !TOOLCHAIN_SUPPORTS_VIRT */
> +#else	/* !CONFIG_AS_HAS_VIRT */
>  #define _ASM_SET_VIRT ".set\tvirt\n\t"
>  #define _ASM_SET_MFGC0	_ASM_SET_VIRT
>  #define _ASM_SET_DMFGC0	_ASM_SET_VIRT
> @@ -2395,7 +2395,7 @@ do {									\
>  	: : "r" (val));							\
>  } while (0)
>  
> -#ifdef TOOLCHAIN_SUPPORTS_DSP
> +#ifdef CONFIG_AS_HAS_DSP
>  #define rddsp(mask)							\
>  ({									\
>  	unsigned int __dspctl;						\
> diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
> index 236a49ee2e3e..a9ca57e3f780 100644
> --- a/arch/mips/include/asm/msa.h
> +++ b/arch/mips/include/asm/msa.h
> @@ -156,7 +156,7 @@ static inline void init_msa_upper(void)
>  	_init_msa_upper();
>  }
>  
> -#ifndef TOOLCHAIN_SUPPORTS_MSA
> +#ifndef CONFIG_AS_HAS_MSA
>  /*
>   * Define assembler macros using .word for the c[ft]cmsa instructions in order
>   * to allow compilation with toolchains that do not support MSA. Once all
> @@ -173,7 +173,7 @@ static inline void init_msa_upper(void)
>  		      _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6)	\
>  		      _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6))
>  #define _ASM_UNSET_CTCMSA ".purgem ctcmsa\n\t"
> -#else /* TOOLCHAIN_SUPPORTS_MSA */
> +#else /* CONFIG_AS_HAS_MSA */
>  #define _ASM_SET_CFCMSA						\
>  		".set\tfp=64\n\t"				\
>  		".set\tmsa\n\t"
> -- 
> 2.39.2 (Apple Git-143)
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH 2/5] MIPS: Add toolchain feature dependency for microMIPS smartMIPS
  2023-04-07 10:27 ` [PATCH 2/5] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Jiaxun Yang
@ 2023-04-07 22:08   ` Nick Desaulniers
  0 siblings, 0 replies; 15+ messages in thread
From: Nick Desaulniers @ 2023-04-07 22:08 UTC (permalink / raw)
  To: Jiaxun Yang; +Cc: linux-mips, llvm, tsbogend, nathan

On Fri, Apr 7, 2023 at 3:27 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> microMIPS smartMIPS kernel can only be compiled if they are supported
> by toolchain.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  arch/mips/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index c52401c155a4..9e9de2b62f28 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2360,7 +2360,7 @@ config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
>           Select this if you want neither microMIPS nor SmartMIPS support
>
>  config CPU_HAS_SMARTMIPS
> -       depends on SYS_SUPPORTS_SMARTMIPS
> +       depends on SYS_SUPPORTS_SMARTMIPS && CC_HAS_SMARTMIPS
>         bool "SmartMIPS"
>         help
>           SmartMIPS is a extension of the MIPS32 architecture aimed at
> @@ -2372,7 +2372,7 @@ config CPU_HAS_SMARTMIPS
>           here.
>
>  config CPU_MICROMIPS
> -       depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
> +       depends on 32BIT && SYS_SUPPORTS_MICROMIPS && CC_HAS_MICROMIPS && !CPU_MIPSR6

^ greater than 80 chars (85 in total). Consider creating two "depends on" lines.

Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>

>         bool "microMIPS"
>         help
>           When this option is enabled the kernel will be built using the
> --
> 2.39.2 (Apple Git-143)
>


-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] MIPS: Detect toolchain support of workarounds in Kconfig
  2023-04-07 10:27 ` [PATCH 3/5] MIPS: Detect toolchain support of workarounds in Kconfig Jiaxun Yang
@ 2023-04-07 22:15   ` Nick Desaulniers
  0 siblings, 0 replies; 15+ messages in thread
From: Nick Desaulniers @ 2023-04-07 22:15 UTC (permalink / raw)
  To: Jiaxun Yang; +Cc: linux-mips, llvm, tsbogend, nathan, Masahiro Yamada

On Fri, Apr 7, 2023 at 3:27 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> LLVM toolchain does not support most of workarounds, detect
> those supports in Kconfig so we can hide unsupported workarounds
> to user.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

TIL about "imply" in Kconfig. + Masahiro to triple check that; the rest LGTM.
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>

> ---
>  arch/mips/Kconfig               | 28 +++++++++++++++++++++++++---
>  arch/mips/Makefile              |  6 +++---
>  arch/mips/cavium-octeon/Kconfig |  1 +
>  3 files changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 9e9de2b62f28..d896af492da6 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -371,9 +371,9 @@ config MACH_DECSTATION
>         select CEVT_R4K if CPU_R4X00
>         select CSRC_IOASIC
>         select CSRC_R4K if CPU_R4X00
> -       select CPU_DADDI_WORKAROUNDS if 64BIT
> -       select CPU_R4000_WORKAROUNDS if 64BIT
> -       select CPU_R4400_WORKAROUNDS if 64BIT
> +       imply CPU_DADDI_WORKAROUNDS
> +       imply CPU_R4000_WORKAROUNDS
> +       imply CPU_R4400_WORKAROUNDS
>         select DMA_NONCOHERENT
>         select NO_IOPORT_MAP
>         select IRQ_MIPS_CPU
> @@ -1723,6 +1723,7 @@ config CPU_JUMP_WORKAROUNDS
>  config CPU_LOONGSON2F_WORKAROUNDS
>         bool "Loongson 2F Workarounds"
>         default y
> +       depends on AS_HAS_NOP_WORKAROUNDS && AS_HAS_JUMP_WORKAROUNDS
>         select CPU_NOP_WORKAROUNDS
>         select CPU_JUMP_WORKAROUNDS
>         help
> @@ -2456,6 +2457,7 @@ config CPU_HAS_SYNC
>  #   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>  config CPU_DADDI_WORKAROUNDS
>         bool
> +       depends on CPU_R4X00_BUGS64 && CC_HAS_DADDI_WORKAROUNDS
>
>  # Work around certain R4000 CPU errata (as implemented by GCC):
>  #
> @@ -2477,6 +2479,7 @@ config CPU_DADDI_WORKAROUNDS
>  #   erratum #52
>  config CPU_R4000_WORKAROUNDS
>         bool
> +       depends on CPU_R4X00_BUGS64 && CC_HAS_R4000_WORKAROUNDS
>         select CPU_R4400_WORKAROUNDS
>
>  # Work around certain R4400 CPU errata (as implemented by GCC):
> @@ -2487,6 +2490,7 @@ config CPU_R4000_WORKAROUNDS
>  #   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>  config CPU_R4400_WORKAROUNDS
>         bool
> +       depends on CPU_R4X00_BUGS64 && CC_HAS_R4400_WORKAROUNDS
>
>  config CPU_R4X00_BUGS64
>         bool
> @@ -3167,6 +3171,15 @@ config CC_HAS_MNO_BRANCH_LIKELY
>         def_bool y
>         depends on $(cc-option,-mno-branch-likely)
>
> +config CC_HAS_R4000_WORKAROUNDS
> +       def_bool $(cc-option,-mfix-r4000)
> +
> +config CC_HAS_R4400_WORKAROUNDS
> +       def_bool $(cc-option,-mfix-r4400)
> +
> +config CC_HAS_DADDI_WORKAROUNDS
> +       def_bool $(cc-option,-mno-daddi)
> +
>  # https://github.com/llvm/llvm-project/issues/61045
>  config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>         def_bool y if CC_IS_CLANG
> @@ -3192,6 +3205,15 @@ config AS_HAS_DSP
>  config AS_HAS_GINV
>         def_bool $(cc-option,-Wa$(comma)-mginv)
>
> +config AS_HAS_CN63XXP1_WORKAROUNDS
> +       def_bool $(cc-option,-Wa$(comma)-mfix-cn63xxp1)
> +
> +config AS_HAS_NOP_WORKAROUNDS
> +       def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-nop)
> +
> +config AS_HAS_JUMP_WORKAROUNDS
> +       def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-jump)
> +
>  menu "Power management options"
>
>  config ARCH_HIBERNATION_POSSIBLE
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 3aa0f9d4ceb6..344fe5f00f7b 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -193,9 +193,9 @@ cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2
>  endif
>  cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi)
>
> -cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
> -cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
> -cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
> +cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += -mfix-r4000
> +cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += -mfix-r4400
> +cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += -mno-daddi
>  ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
>  cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop
>  cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump
> diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
> index 450e979ef5d9..38c9dc89cd5f 100644
> --- a/arch/mips/cavium-octeon/Kconfig
> +++ b/arch/mips/cavium-octeon/Kconfig
> @@ -4,6 +4,7 @@ if CPU_CAVIUM_OCTEON
>  config CAVIUM_CN63XXP1
>         bool "Enable CN63XXP1 errata workarounds"
>         default "n"
> +       depends on AS_HAS_CN63XXP1_WORKAROUNDS
>         help
>           The CN63XXP1 chip requires build time workarounds to
>           function reliably, select this option to enable them.  These
> --
> 2.39.2 (Apple Git-143)
>


-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU
  2023-04-07 10:27 ` [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Jiaxun Yang
@ 2023-04-07 22:19   ` Nick Desaulniers
  2023-04-07 22:21     ` Nick Desaulniers
  2023-04-07 22:26     ` Jiaxun Yang
  0 siblings, 2 replies; 15+ messages in thread
From: Nick Desaulniers @ 2023-04-07 22:19 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-mips, llvm, tsbogend, nathan, Masahiro Yamada,
	Linux Kbuild mailing list

On Fri, Apr 7, 2023 at 3:27 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> LLVM is not happy with using o32 ABI on 64 bit CPU, thus build 32 bit
> kernel is unsupported.
>
> Detect this in Kconfig to prevent user select 32 bit kernel with
> unsupported toolchain.
>
> Reported-by: Nathan Chancellor <nathan@kernel.org>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

I suspect this may fix:
Link: https://github.com/ClangBuiltLinux/linux/issues/884

> ---
>  arch/mips/Kconfig | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index d896af492da6..5e399a5ac3b3 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2016,6 +2016,7 @@ choice
>  config 32BIT
>         bool "32-bit kernel"
>         depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
> +       depends on CC_HAS_O32_ABI

Does this disable 32b mips builds with clang?

>         select TRAD_SIGNALS
>         help
>           Select this option if you want to build a 32-bit kernel.
> @@ -3136,7 +3137,7 @@ config COMPAT
>
>  config MIPS32_O32
>         bool "Kernel support for o32 binaries"
> -       depends on 64BIT
> +       depends on 64BIT && CC_HAS_O32_ABI
>         select ARCH_WANT_OLD_COMPAT_IPC
>         select COMPAT
>         select MIPS32_COMPAT
> @@ -3184,6 +3185,10 @@ config CC_HAS_DADDI_WORKAROUNDS
>  config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>         def_bool y if CC_IS_CLANG
>
> +config CC_HAS_O32_ABI
> +       def_bool y
> +       depends on !CPU_SUPPORTS_64BIT_KERNEL || $(cc-option,-march=mips3 -mabi=32)

Should this be
def_bool $(cc-option,-march=mips3 -mabi=32)
depends on !CPU_SUPPORTS_64BIT_KERNEL

?

> +
>  config AS_HAS_MSA
>         def_bool $(cc-option,-Wa$(comma)-mmsa)
>
> --
> 2.39.2 (Apple Git-143)
>


-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU
  2023-04-07 22:19   ` Nick Desaulniers
@ 2023-04-07 22:21     ` Nick Desaulniers
  2023-04-07 22:26     ` Jiaxun Yang
  1 sibling, 0 replies; 15+ messages in thread
From: Nick Desaulniers @ 2023-04-07 22:21 UTC (permalink / raw)
  To: Jiaxun Yang
  Cc: linux-mips, llvm, tsbogend, nathan, Masahiro Yamada,
	Linux Kbuild mailing list

On Fri, Apr 7, 2023 at 3:19 PM Nick Desaulniers <ndesaulniers@google.com> wrote:
>
> On Fri, Apr 7, 2023 at 3:27 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> >
> > LLVM is not happy with using o32 ABI on 64 bit CPU, thus build 32 bit
> > kernel is unsupported.
> >
> > Detect this in Kconfig to prevent user select 32 bit kernel with
> > unsupported toolchain.
> >
> > Reported-by: Nathan Chancellor <nathan@kernel.org>
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> I suspect this may fix:
> Link: https://github.com/ClangBuiltLinux/linux/issues/884

Oh, and there was
https://github.com/ClangBuiltLinux/linux/issues/884#issuecomment-1242729142
I wonder if that is preferable or a source of inspiration?


-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH 5/5] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-07 10:27 ` [PATCH 5/5] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Jiaxun Yang
@ 2023-04-07 22:23   ` Nick Desaulniers
  2023-04-08  9:47     ` Jiaxun Yang
  0 siblings, 1 reply; 15+ messages in thread
From: Nick Desaulniers @ 2023-04-07 22:23 UTC (permalink / raw)
  To: Jiaxun Yang; +Cc: linux-mips, llvm, tsbogend, nathan

On Fri, Apr 7, 2023 at 3:27 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> LLVM does not implement some of -march option. However those march
> does not provide any special functionality in most cases, they just
> serves as compiler's tuning target.

Then should we change these then to be in the form:

-cflags-$(CONFIG_CPU_R3000)     += -march=r3000
+cflags-$(CONFIG_CPU_R3000)     += -march=mips1 $(call cc-option,-mtune=r3000)

>
> Fallback -march CFLAG to ISA level if unsupported by toolchain so
> we can get those kernel to build with LLVM.
>
> Reported-by: Nathan Chancellor <nathan@kernel.org>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  arch/mips/Makefile | 30 +++++++++++++++++-------------
>  1 file changed, 17 insertions(+), 13 deletions(-)
>
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 344fe5f00f7b..eab6abeaa45c 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -148,10 +148,10 @@ cflags-y += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
>  #
>  # CPU-dependent compiler/assembler options for optimization.
>  #
> -cflags-$(CONFIG_CPU_R3000)     += -march=r3000
> -cflags-$(CONFIG_CPU_R4300)     += -march=r4300 -Wa,--trap
> -cflags-$(CONFIG_CPU_R4X00)     += -march=r4600 -Wa,--trap
> -cflags-$(CONFIG_CPU_TX49XX)    += -march=r4600 -Wa,--trap
> +cflags-$(CONFIG_CPU_R3000)     += $(call cc-option,-march=r3000,-march=mips1)
> +cflags-$(CONFIG_CPU_R4300)     += $(call cc-option,-march=r4300,-march=mips3) -Wa,--trap
> +cflags-$(CONFIG_CPU_R4X00)     += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
> +cflags-$(CONFIG_CPU_TX49XX)    += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg
> @@ -160,19 +160,21 @@ cflags-$(CONFIG_CPU_MIPS64_R1)    += -march=mips64 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS64_R5) += -march=mips64r5 -Wa,--trap
>  cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap
> -cflags-$(CONFIG_CPU_P5600)     += -march=p5600 -Wa,--trap -modd-spreg
> -cflags-$(CONFIG_CPU_R5000)     += -march=r5000 -Wa,--trap
> -cflags-$(CONFIG_CPU_R5500)     += $(call cc-option,-march=r5500,-march=r5000) \
> +cflags-$(CONFIG_CPU_P5600)     += $(call cc-option,-march=p5600,-march=mips32r5) \
> +                       -Wa,--trap -modd-spreg
> +cflags-$(CONFIG_CPU_R5000)     += $(call cc-option,-march=r5000,-march=mips4) \
>                         -Wa,--trap
> -cflags-$(CONFIG_CPU_NEVADA)    += $(call cc-option,-march=rm5200,-march=r5000) \
> +cflags-$(CONFIG_CPU_R5500)     += $(call cc-option,-march=r5500,-march=mips4) \
>                         -Wa,--trap
> -cflags-$(CONFIG_CPU_RM7000)    += $(call cc-option,-march=rm7000,-march=r5000) \
> +cflags-$(CONFIG_CPU_NEVADA)    += $(call cc-option,-march=rm5200,-march=mips4) \
>                         -Wa,--trap
> -cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-march=sb1,-march=r5000) \
> +cflags-$(CONFIG_CPU_RM7000)    += $(call cc-option,-march=rm7000,-march=mips4) \
> +                       -Wa,--trap
> +cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-march=sb1,-march=mips4) \
>                         -Wa,--trap
>  cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-mno-mdmx)
>  cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-mno-mips3d)
> -cflags-$(CONFIG_CPU_R10000)    += $(call cc-option,-march=r10000,-march=r8000) \
> +cflags-$(CONFIG_CPU_R10000)    += $(call cc-option,-march=r10000,-march=mips4) \
>                         -Wa,--trap
>  cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
>  ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
> @@ -181,8 +183,10 @@ endif
>  cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
>  cflags-$(CONFIG_CPU_BMIPS)     += -march=mips32 -Wa,-mips32 -Wa,--trap
>
> -cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap
> -cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap
> +cflags-$(CONFIG_CPU_LOONGSON2E) += \
> +                       $(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap
> +cflags-$(CONFIG_CPU_LOONGSON2F) += \
> +                       $(call cc-option,-march=loongson2f,-march=mips3) -Wa,--trap
>  # Some -march= flags enable MMI instructions, and GCC complains about that
>  # support being enabled alongside -msoft-float. Thus explicitly disable MMI.
>  cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)
> --
> 2.39.2 (Apple Git-143)
>


-- 
Thanks,
~Nick Desaulniers

^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU
  2023-04-07 22:19   ` Nick Desaulniers
  2023-04-07 22:21     ` Nick Desaulniers
@ 2023-04-07 22:26     ` Jiaxun Yang
  1 sibling, 0 replies; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-07 22:26 UTC (permalink / raw)
  To: Nick Desaulniers
  Cc: linux-mips@vger.kernel.org, llvm, Thomas Bogendoerfer,
	Nathan Chancellor, Masahiro Yamada, Linux Kbuild mailing list



> 2023年4月7日 23:19，Nick Desaulniers <ndesaulniers@google.com> 写道：
> 
> On Fri, Apr 7, 2023 at 3:27 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>> 
>> LLVM is not happy with using o32 ABI on 64 bit CPU, thus build 32 bit
>> kernel is unsupported.
>> 
>> Detect this in Kconfig to prevent user select 32 bit kernel with
>> unsupported toolchain.
>> 
>> Reported-by: Nathan Chancellor <nathan@kernel.org>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> I suspect this may fix:
> Link: https://github.com/ClangBuiltLinux/linux/issues/884
> 
>> ---
>> arch/mips/Kconfig | 7 ++++++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index d896af492da6..5e399a5ac3b3 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -2016,6 +2016,7 @@ choice
>> config 32BIT
>>        bool "32-bit kernel"
>>        depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> +       depends on CC_HAS_O32_ABI
> 
> Does this disable 32b mips builds with clang?

It disable 32bit kernel build for 64bit CPU with clang.

i.e.: 32bit kernel for R4000, 32bit kernel for MIPS64R2 is disabled, but you can still build 32 bit
kernel for mips32r2.

> 
>>        select TRAD_SIGNALS
>>        help
>>          Select this option if you want to build a 32-bit kernel.
>> @@ -3136,7 +3137,7 @@ config COMPAT
>> 
>> config MIPS32_O32
>>        bool "Kernel support for o32 binaries"
>> -       depends on 64BIT
>> +       depends on 64BIT && CC_HAS_O32_ABI
>>        select ARCH_WANT_OLD_COMPAT_IPC
>>        select COMPAT
>>        select MIPS32_COMPAT
>> @@ -3184,6 +3185,10 @@ config CC_HAS_DADDI_WORKAROUNDS
>> config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>>        def_bool y if CC_IS_CLANG
>> 
>> +config CC_HAS_O32_ABI
>> +       def_bool y
>> +       depends on !CPU_SUPPORTS_64BIT_KERNEL || $(cc-option,-march=mips3 -mabi=32)
> 
> Should this be
> def_bool $(cc-option,-march=mips3 -mabi=32)
> depends on !CPU_SUPPORTS_64BIT_KERNEL

Hmm, the logic is to enable CC_HAS_O32_ABI if CPU is 32bit only (!CPU_SUPPORTS_64BIT_KERNEL)
or toolchain supports 64bit CPU with o32 ABI combination.

Thanks
Jiaxun

> 
> ?
> 
>> +
>> config AS_HAS_MSA
>>        def_bool $(cc-option,-Wa$(comma)-mmsa)
>> 
>> --
>> 2.39.2 (Apple Git-143)
>> 
> 
> 
> -- 
> Thanks,
> ~Nick Desaulniers



^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig
  2023-04-07 18:57   ` Nathan Chancellor
@ 2023-04-07 22:51     ` Jiaxun Yang
  0 siblings, 0 replies; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-07 22:51 UTC (permalink / raw)
  To: Nathan Chancellor
  Cc: linux-mips@vger.kernel.org, llvm, Thomas Bogendoerfer,
	Nick Desaulniers



> 2023年4月7日 19:57，Nathan Chancellor <nathan@kernel.org> 写道：
> 
> Hi Jiaxun,
> 
> On Fri, Apr 07, 2023 at 11:27:17AM +0100, Jiaxun Yang wrote:
>> Use Kconfig to perform Kconfig toolchain feature check, so we will
>> be able to have toolchain feature availablility information in Kconfig
>> to guard relevant options.
>> 
> 
> First of all, thank you a lot for this series! I applied them on top of
> mips-next and my allnoconfig issue appears to be gone. However, with
> this change, 32r1{,el}_defconfig is broken for arch/mips/kernel/traps.c.
> 
> $ make -skj"$(nproc)" ARCH=mips CROSS_COMPILE=mips-linux-gnu- LLVM=1 LLVM_IAS=0 O=build mrproper 32r1_defconfig arch/mips/kernel/traps.o
> ...
> /tmp/traps-f8ea56.s: Assembler messages:
> /tmp/traps-f8ea56.s:8227: Error: `fp=64' used with a 32-bit fpu
> /tmp/traps-f8ea56.s:8228: Error: `fp=64' used with a 32-bit fpu
> /tmp/traps-f8ea56.s:8228: Warning: the `msa' extension requires MIPS32 revision 2 or greater
> clang: error: assembler command failed with exit code 1 (use -v to see invocation)
> ...


Oh that’s actually a problem in code.
Will add a patch to address this in v2.

> 
> In case it matters:
> 
> $ clang --version | head -1
> ClangBuiltLinux clang version 16.0.1
> 
> $ mips-linux-gnu-as --version | head -1
> GNU assembler (GNU Binutils) 2.40
> 
> A few comments below, I have not tested anything beyond this.
> 
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>> arch/mips/Kconfig                | 27 +++++++++++++++++++++++++++
>> arch/mips/Makefile               | 29 +++--------------------------
>> arch/mips/crypto/crc32-mips.c    |  4 ++--
>> arch/mips/include/asm/asmmacro.h |  8 ++++----
>> arch/mips/include/asm/ginvt.h    |  2 +-
>> arch/mips/include/asm/mipsregs.h | 10 +++++-----
>> arch/mips/include/asm/msa.h      |  4 ++--
>> 7 files changed, 44 insertions(+), 40 deletions(-)
>> 
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index 770d098b11bf..c52401c155a4 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -3157,6 +3157,12 @@ config MIPS32_N32
>> 
>>   If unsure, say N.
>> 
>> +config CC_HAS_SMARTMIPS
>> + def_bool $(cc-option,-mmicromips)
> 
> -msmartmips?

Good catch :-D

> 
>> +
>> +config CC_HAS_MICROMIPS
>> + def_bool $(cc-option,-mmicromips)
> 
> Neither of these configurations are used in this change. Should they be
> moved to the next change in the series?

Hmm I’d prefer leave them here because this patch tracks all compiler checks that
we have in Makefile.


Thanks
- Jiaxun



^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH 5/5] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported
  2023-04-07 22:23   ` Nick Desaulniers
@ 2023-04-08  9:47     ` Jiaxun Yang
  0 siblings, 0 replies; 15+ messages in thread
From: Jiaxun Yang @ 2023-04-08  9:47 UTC (permalink / raw)
  To: Nick Desaulniers
  Cc: linux-mips@vger.kernel.org, llvm, Thomas Bogendoerfer,
	Nathan Chancellor



> 2023年4月7日 23:23，Nick Desaulniers <ndesaulniers@google.com> 写道：
> 
> On Fri, Apr 7, 2023 at 3:27 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>> 
>> LLVM does not implement some of -march option. However those march
>> does not provide any special functionality in most cases, they just
>> serves as compiler's tuning target.
> 
> Then should we change these then to be in the form:
> 
> -cflags-$(CONFIG_CPU_R3000)     += -march=r3000
> +cflags-$(CONFIG_CPU_R3000)     += -march=mips1 $(call cc-option,-mtune=r3000)

Just tested with GCC and it seems like there are still some difference in generated code
for -march=r4600 and -march=mips3 -mtune=r4600.
As I’m unable to test on a real system I’d prefer just leave them as is.

I’ll try to reword commit message.

Thanks
Jiaxun

> 
> -- 
> Thanks,
> ~Nick Desaulniers



^ permalink raw reply	[flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-04-08  9:47 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-04-07 10:27 [PATCH 0/5] MIPS: LLVM toolchain support for more CPUs Jiaxun Yang
2023-04-07 10:27 ` [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig Jiaxun Yang
2023-04-07 18:57   ` Nathan Chancellor
2023-04-07 22:51     ` Jiaxun Yang
2023-04-07 10:27 ` [PATCH 2/5] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Jiaxun Yang
2023-04-07 22:08   ` Nick Desaulniers
2023-04-07 10:27 ` [PATCH 3/5] MIPS: Detect toolchain support of workarounds in Kconfig Jiaxun Yang
2023-04-07 22:15   ` Nick Desaulniers
2023-04-07 10:27 ` [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Jiaxun Yang
2023-04-07 22:19   ` Nick Desaulniers
2023-04-07 22:21     ` Nick Desaulniers
2023-04-07 22:26     ` Jiaxun Yang
2023-04-07 10:27 ` [PATCH 5/5] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Jiaxun Yang
2023-04-07 22:23   ` Nick Desaulniers
2023-04-08  9:47     ` Jiaxun Yang

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