From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Jonas Gorski <jonas.gorski@gmail.com>,
"Maciej W. Rozycki" <macro@orcam.me.uk>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH v2 2/4] MIPS: Introduce config options for LLSC availability
Date: Wed, 12 Jun 2024 10:53:30 +0100 [thread overview]
Message-ID: <20240612-mips-llsc-v2-2-a42bd5562bdb@flygoat.com> (raw)
In-Reply-To: <20240612-mips-llsc-v2-0-a42bd5562bdb@flygoat.com>
Introduce CPU_HAS_LLSC and CPU_MAY_HAVE_LLSC to determine availability
of LLSC and Kconfig level.
They are both true for almost all supported CPUs besides:
R3000: Doesn't have LLSC, so both false.
R5000 series: LLSC is unusable for 64bit kernel, so both false.
R10000: Some platforms decided to opt-out LLSC due to errata, so only
select CPU_MAY_HAVE_LLSC.
WAR_4KC_LLSC: LLSC is buggy on certain reversion, which can be detected
at cpu-probe or platform override, so only select CPU_MAY_HAVE_LLSC.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2: Make cpu_has_llsc logic clear
---
arch/mips/Kconfig | 20 ++++++++++++++++++++
arch/mips/include/asm/cpu-features.h | 9 ++++++++-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 8ac467c1f9c8..50260a7e9b54 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1548,6 +1548,7 @@ config CPU_R3000
config CPU_R4300
bool "R4300"
depends on SYS_HAS_CPU_R4300
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
@@ -1556,6 +1557,7 @@ config CPU_R4300
config CPU_R4X00
bool "R4x00"
depends on SYS_HAS_CPU_R4X00
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1566,6 +1568,7 @@ config CPU_R4X00
config CPU_TX49XX
bool "R49XX"
depends on SYS_HAS_CPU_TX49XX
+ select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
@@ -1574,6 +1577,7 @@ config CPU_TX49XX
config CPU_R5000
bool "R5000"
depends on SYS_HAS_CPU_R5000
+ select CPU_HAS_LLSC if !64BIT
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1583,6 +1587,7 @@ config CPU_R5000
config CPU_R5500
bool "R5500"
depends on SYS_HAS_CPU_R5500
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1593,6 +1598,7 @@ config CPU_R5500
config CPU_NEVADA
bool "RM52xx"
depends on SYS_HAS_CPU_NEVADA
+ select CPU_HAS_LLSC if !64BIT
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1602,6 +1608,8 @@ config CPU_NEVADA
config CPU_R10000
bool "R10000"
depends on SYS_HAS_CPU_R10000
+ select CPU_HAS_LLSC if !WAR_R10000_LLSC
+ select CPU_MAY_HAVE_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
@@ -1613,6 +1621,7 @@ config CPU_R10000
config CPU_RM7000
bool "RM7000"
depends on SYS_HAS_CPU_RM7000
+ select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
@@ -1622,6 +1631,7 @@ config CPU_RM7000
config CPU_SB1
bool "SB1"
depends on SYS_HAS_CPU_SB1
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1656,6 +1666,7 @@ config CPU_BMIPS
select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
@@ -2381,6 +2392,15 @@ config CPU_DIEI_BROKEN
config CPU_HAS_RIXI
bool
+# For CPU that must have LLSC
+config CPU_HAS_LLSC
+ def_bool TARGET_ISA_REV > 0 && !WAR_4KC_LLSC
+ select CPU_MAY_HAVE_LLSC
+
+# For CPU that LLSC support is optional
+config CPU_MAY_HAVE_LLSC
+ def_bool TARGET_ISA_REV > 0
+
config CPU_NO_LOAD_STORE_LR
bool
help
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 404390bb87ea..40f5570de563 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -185,8 +185,15 @@
#ifndef cpu_has_ejtag
#define cpu_has_ejtag __opt(MIPS_CPU_EJTAG)
#endif
+
#ifndef cpu_has_llsc
-#define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC)
+# if defined(CONFIG_CPU_HAS_LLSC)
+# define cpu_has_llsc 1
+# elif defined(CONFIG_CPU_MAY_HAVE_LLSC)
+# define cpu_has_llsc __opt(MIPS_CPU_LLSC)
+# else
+# define cpu_has_llsc 0
+# endif
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc cpu_has_llsc
--
2.43.0
next prev parent reply other threads:[~2024-06-12 9:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 9:53 [PATCH v2 0/4] MIPS: Enable ARCH_SUPPORTS_ATOMIC_RMW Jiaxun Yang
2024-06-12 9:53 ` [PATCH v2 1/4] MIPS: Introduce WAR_4KC_LLSC config option Jiaxun Yang
2024-06-12 9:53 ` Jiaxun Yang [this message]
2024-06-20 16:06 ` [PATCH v2 2/4] MIPS: Introduce config options for LLSC availability Thomas Bogendoerfer
2024-06-20 16:30 ` Jiaxun Yang
2024-06-20 17:41 ` Thomas Bogendoerfer
2024-06-21 0:00 ` Maciej W. Rozycki
2024-06-21 10:45 ` Jiaxun Yang
2024-06-21 13:57 ` Maciej W. Rozycki
2024-06-21 15:21 ` Jiaxun Yang
2024-06-21 17:40 ` Maciej W. Rozycki
2024-06-21 20:31 ` Thomas Bogendoerfer
2024-06-12 9:53 ` [PATCH v2 3/4] MIPS: Select ARCH_SUPPORTS_ATOMIC_RMW when possible Jiaxun Yang
2024-06-12 9:53 ` [PATCH v2 4/4] MIPS: Select ARCH_HAVE_NMI_SAFE_CMPXCHG " Jiaxun Yang
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