Re: [PATCH 00/38] irqchip: mips-gic: Cleanup & optimisation

[Paul Burton <paul.burton@imgtec.com>]

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Hi Marc,

On Friday, 18 August 2017 10:28:01 PDT Marc Zyngier wrote:
> Hi Paul,
> 
> On 13/08/17 05:36, Paul Burton wrote:
> > This series cleans up the MIPS Global Interrupt Controller (GIC) driver
> > somewhat. It moves us towards using a header in a similar vein to the
> > ones we have for the MIPS Coherence Manager (CM) & Cluster Power
> > Controller (CPC) which allows us to access the GIC outside of the
> > irqchip driver - something beneficial already for the clocksource &
> > clock event driver, and which will be beneficial for further drivers
> > (eg. one for the GIC watchdog timer) and for multi-cluster work. Using
> > this header is also beneficial for consistency & code-sharing.
> > 
> > In addition to cleanups the series also optimises the driver in various
> > ways, including by using a per-CPU variable for pcpu_masks & removing
> > the need to read the GIC_SH_MASK_* registers when decoding interrupts in
> > gic_handle_shared_int().
> > 
> > This series requires my "[PATCH 00/19] MIPS: Initial multi-cluster
> > support" series to be applied first.
> 
> I went through the whole series, and didn't spot anything bad (the
> couple of nits I raised can either be fixed at a later time or as a
> fixup on top of what you have).

Thanks :) I appreciate your review. So shall I take that as you'd prefer that 
I submit separate fixup patches rather than submit a v2?

> Given that this has a number of dependencies (your multicluster series),
> how do you want to get this merged?
> 
> Thanks,
> 
> 	M.

Ralf mentioned in a meeting yesterday that he was going to speak to Thomas 
about that, and suggested that perhaps it'd be easiest for him to take it 
through the MIPS tree. I'm happy either way.

Thanks,
    Paul

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