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From: Jun Sun <jsun@mvista.com>
To: "Kevin D. Kissell" <kevink@mips.com>, ralf@oss.sgi.com
Cc: Dominic Sweetman <dom@algor.co.uk>,
	linux-mips@oss.sgi.com, linux-mips@fnet.fr
Subject: Re: load_unaligned() and "uld" instruction
Date: Tue, 26 Sep 2000 11:04:12 -0700	[thread overview]
Message-ID: <39D0E51C.79A0BE50@mvista.com> (raw)
In-Reply-To: 000d01c02782$32d31560$0deca8c0@Ulysses

"Kevin D. Kissell" wrote:
> >
> > If we have to use "-mips2" option, is there a clean way which allows us
> > to "uld/usw" instructions (instead of manually twicking the compilation
> > for each file that uses them)?
>

Ralf, before the perfect solution is found, the following patch makes
the gcc complain go away.  It just use ".set mips3" pragma.
 
> It's clear that I'll have to do
> something similar with the unaligned accesses in the USB
> support code before it will run on the MIPS 4Kc and
> similar CPUs.
> 

I am pretty close to get USB running with the v2.4-test5.  The unaligned
access is the minor problem.  The bigger problem I am fighting with now
is bus_to_virt()/virt_to_bus() and USB interrupt.

Jun

=====================================

--- linux/include/asm-mips/unaligned.h.orig     Mon Sep 25 14:02:52 2000
+++ linux/include/asm-mips/unaligned.h  Tue Sep 26 10:53:31 2000
@@ -19,7 +19,7 @@
 {
        unsigned long long __res;
 
-       __asm__("uld\t%0,(%1)"
+       __asm__(".set\tmips3\n\tuld\t%0,(%1)"
                :"=&r" (__res)
                :"r" (__addr));
 
@@ -33,7 +33,7 @@
 {
        unsigned long __res;
 
-       __asm__("ulw\t%0,(%1)"
+       __asm__(".set\tmips3\n\tulw\t%0,(%1)"
                :"=&r" (__res)
                :"r" (__addr));
 
@@ -47,7 +47,7 @@
 {
        unsigned long __res;
 
-       __asm__("ulh\t%0,(%1)"
+       __asm__(".set\tmips3\n\tulh\t%0,(%1)"
                :"=&r" (__res)
                :"r" (__addr));
 
@@ -60,7 +60,7 @@
 extern __inline__ void stq_u(unsigned long __val, unsigned long long *
__addr)
 {
        __asm__ __volatile__(
-               "usd\t%0,(%1)"
+               ".set\tmips3\n\tusd\t%0,(%1)"
                : /* No results */
                :"r" (__val),
                 "r" (__addr));
@@ -72,7 +72,7 @@
 extern __inline__ void stl_u(unsigned long __val, unsigned int *
__addr)
 {
        __asm__ __volatile__(
-               "usw\t%0,(%1)"
+               ".set\tmips3\n\tusw\t%0,(%1)"
                : /* No results */
                :"r" (__val),
                 "r" (__addr));
@@ -84,7 +84,7 @@
 extern __inline__ void stw_u(unsigned long __val, unsigned short *
__addr)
 {
        __asm__ __volatile__(
-               "ush\t%0,(%1)"
+               ".set\tmips3\n\tush\t%0,(%1)"
                : /* No results */
                :"r" (__val),
                 "r" (__addr));

  parent reply	other threads:[~2000-09-26 18:05 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2000-09-25 18:48 load_unaligned() and "uld" instruction Jun Sun
2000-09-25 21:16 ` Dominic Sweetman
2000-09-25 21:36   ` Jun Sun
2000-09-25 23:29     ` Ralf Baechle
2000-09-26  6:22     ` Kevin D. Kissell
2000-09-26  6:22       ` Kevin D. Kissell
2000-09-26  9:08       ` Dominic Sweetman
2000-09-26  9:08         ` Dominic Sweetman
2000-09-29 17:22         ` Ralf Baechle
2000-10-09 14:49           ` Dominic Sweetman
2000-09-26 18:04       ` Jun Sun [this message]
2000-09-27 10:06         ` Maciej W. Rozycki
2000-10-06  0:43           ` Ralf Baechle
2000-10-06  9:54             ` Maciej W. Rozycki
2000-10-06 16:21               ` Ralf Baechle
2000-10-05 12:13         ` Ralf Baechle
2000-10-06  1:11           ` Jun Sun
2000-10-05 19:41             ` Kevin D. Kissell
2000-10-05 19:41               ` Kevin D. Kissell
2000-10-06  4:32               ` Jun Sun
2000-10-05 22:10                 ` Kevin D. Kissell
2000-10-05 22:10                   ` Kevin D. Kissell
2000-10-06  5:53                   ` Jun Sun
2000-10-05 23:14                     ` Kevin D. Kissell
2000-10-05 23:14                       ` Kevin D. Kissell
2000-10-06 16:32                     ` Ralf Baechle
2000-10-07  1:35                     ` Jun Sun
2000-10-06 22:26                       ` Ralf Baechle
2000-10-06 16:28                 ` Ralf Baechle
2000-10-07  1:24                   ` Jun Sun
2000-10-06 20:46                     ` Kevin D. Kissell
2000-10-06 20:46                       ` Kevin D. Kissell
2000-10-07  7:16                       ` Jun Sun

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