From: Jun Sun <jsun@mvista.com>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: Ralf Baechle <ralf@oss.sgi.com>,
linux-mips@fnet.fr, linux-mips@oss.sgi.com,
Dominic Sweetman <dom@algor.co.uk>
Subject: Re: load_unaligned() and "uld" instruction
Date: Thu, 05 Oct 2000 21:32:41 -0700 [thread overview]
Message-ID: <39DD55E9.AFCACB0E@mvista.com> (raw)
In-Reply-To: 00d101c02f04$3a6d7340$0deca8c0@Ulysses
"Kevin D. Kissell" wrote:
>
> > > > Ralf, before the perfect solution is found, the following patch makes
> > > > the gcc complain go away. It just use ".set mips3" pragma.
>
> Which, as Ralf correctly observes, will generate code that will
> crash on 32-bit CPUs,
Why will it crash 32-bit CPUs? On my R5432 CPU, the lwl/lwr sequence
executes just fine.
Or do you mean it will crash SOME 32-bit CPUs? Do those 32-bit CPUs
support lwl or lwr? If they don't, they should generate a reserved
instruction exception. If they do, I don't see any problem.
> > With the second half, are you saying the "cut-off-upper-32-bit" bug
> > actually hides the register corruption problem? If so, maybe we need
> > the "cut-off-upper_32-bit" bug for the 32-bit MIPS tree.
>
> This is a joke, right?
>
Not entirely. I was thinking if the unaligned load/store instruction
corrupts the upper 32 bit content on SOME cpus, maybe we do need to cut
the upper 32bit as a workaround. Well, I hope it is not necessary.
Jun
next prev parent reply other threads:[~2000-10-05 21:34 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-09-25 18:48 load_unaligned() and "uld" instruction Jun Sun
2000-09-25 21:16 ` Dominic Sweetman
2000-09-25 21:36 ` Jun Sun
2000-09-25 23:29 ` Ralf Baechle
2000-09-26 6:22 ` Kevin D. Kissell
2000-09-26 6:22 ` Kevin D. Kissell
2000-09-26 9:08 ` Dominic Sweetman
2000-09-26 9:08 ` Dominic Sweetman
2000-09-29 17:22 ` Ralf Baechle
2000-10-09 14:49 ` Dominic Sweetman
2000-09-26 18:04 ` Jun Sun
2000-09-27 10:06 ` Maciej W. Rozycki
2000-10-06 0:43 ` Ralf Baechle
2000-10-06 9:54 ` Maciej W. Rozycki
2000-10-06 16:21 ` Ralf Baechle
2000-10-05 12:13 ` Ralf Baechle
2000-10-06 1:11 ` Jun Sun
2000-10-05 19:41 ` Kevin D. Kissell
2000-10-05 19:41 ` Kevin D. Kissell
2000-10-06 4:32 ` Jun Sun [this message]
2000-10-05 22:10 ` Kevin D. Kissell
2000-10-05 22:10 ` Kevin D. Kissell
2000-10-06 5:53 ` Jun Sun
2000-10-05 23:14 ` Kevin D. Kissell
2000-10-05 23:14 ` Kevin D. Kissell
2000-10-06 16:32 ` Ralf Baechle
2000-10-07 1:35 ` Jun Sun
2000-10-06 22:26 ` Ralf Baechle
2000-10-06 16:28 ` Ralf Baechle
2000-10-07 1:24 ` Jun Sun
2000-10-06 20:46 ` Kevin D. Kissell
2000-10-06 20:46 ` Kevin D. Kissell
2000-10-07 7:16 ` Jun Sun
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