From: "Kevin D. Kissell" <kevink@mips.com>
To: "Jun Sun" <jsun@mvista.com>
Cc: "Ralf Baechle" <ralf@oss.sgi.com>, <linux-mips@fnet.fr>,
<linux-mips@oss.sgi.com>
Subject: Re: load_unaligned() and "uld" instruction
Date: Fri, 6 Oct 2000 01:14:40 +0200 [thread overview]
Message-ID: <011e01c02f22$10017b60$0deca8c0@Ulysses> (raw)
In-Reply-To: 39DD68DE.E9B26A3D@mvista.com
> > > Why will it crash 32-bit CPUs? On my R5432 CPU, the lwl/lwr sequence
> > > executes just fine.
> > >
> > > Or do you mean it will crash SOME 32-bit CPUs? Do those 32-bit CPUs
> > > support lwl or lwr? If they don't, they should generate a reserved
> > > instruction exception. If they do, I don't see any problem.
> >
> > Please re-read my previous message. I wasn't talking about the
> > MIPS I lwl/lwr sequence for loading an unaligned 32-bit word, I was
> > talking about the MIPS III ldl/ldr sequence for loading an unaligned
> > 64-bit doubleword.
> >
> > Kevin K.
>
> Ahh, my bad.
>
> Although the usb does use get_unaligned(u64) (ldl/ldr), it actually does
> not run into it - at least in my test so far. That probably explains
> why my fix runs on the R5432 CPU so far.
The 5432 may have a 32-bit external bus, but it's still (as far
as I know) a 64-bit part internally, so as long as you're executing
in kernel mode, the ldl/ldr's should work as designed.
Kevin K.
WARNING: multiple messages have this Message-ID (diff)
From: "Kevin D. Kissell" <kevink@mips.com>
To: Jun Sun <jsun@mvista.com>
Cc: Ralf Baechle <ralf@oss.sgi.com>,
linux-mips@fnet.fr, linux-mips@oss.sgi.com
Subject: Re: load_unaligned() and "uld" instruction
Date: Fri, 6 Oct 2000 01:14:40 +0200 [thread overview]
Message-ID: <011e01c02f22$10017b60$0deca8c0@Ulysses> (raw)
Message-ID: <20001005231440.Hf6Q8w2K_G6emk16b-_MJb0cc5Npda4nogviRs-wNNU@z> (raw)
In-Reply-To: 39DD68DE.E9B26A3D@mvista.com
> > > Why will it crash 32-bit CPUs? On my R5432 CPU, the lwl/lwr sequence
> > > executes just fine.
> > >
> > > Or do you mean it will crash SOME 32-bit CPUs? Do those 32-bit CPUs
> > > support lwl or lwr? If they don't, they should generate a reserved
> > > instruction exception. If they do, I don't see any problem.
> >
> > Please re-read my previous message. I wasn't talking about the
> > MIPS I lwl/lwr sequence for loading an unaligned 32-bit word, I was
> > talking about the MIPS III ldl/ldr sequence for loading an unaligned
> > 64-bit doubleword.
> >
> > Kevin K.
>
> Ahh, my bad.
>
> Although the usb does use get_unaligned(u64) (ldl/ldr), it actually does
> not run into it - at least in my test so far. That probably explains
> why my fix runs on the R5432 CPU so far.
The 5432 may have a 32-bit external bus, but it's still (as far
as I know) a 64-bit part internally, so as long as you're executing
in kernel mode, the ldl/ldr's should work as designed.
Kevin K.
next prev parent reply other threads:[~2000-10-05 23:12 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-09-25 18:48 load_unaligned() and "uld" instruction Jun Sun
2000-09-25 21:16 ` Dominic Sweetman
2000-09-25 21:36 ` Jun Sun
2000-09-25 23:29 ` Ralf Baechle
2000-09-26 6:22 ` Kevin D. Kissell
2000-09-26 6:22 ` Kevin D. Kissell
2000-09-26 9:08 ` Dominic Sweetman
2000-09-26 9:08 ` Dominic Sweetman
2000-09-29 17:22 ` Ralf Baechle
2000-10-09 14:49 ` Dominic Sweetman
2000-09-26 18:04 ` Jun Sun
2000-09-27 10:06 ` Maciej W. Rozycki
2000-10-06 0:43 ` Ralf Baechle
2000-10-06 9:54 ` Maciej W. Rozycki
2000-10-06 16:21 ` Ralf Baechle
2000-10-05 12:13 ` Ralf Baechle
2000-10-06 1:11 ` Jun Sun
2000-10-05 19:41 ` Kevin D. Kissell
2000-10-05 19:41 ` Kevin D. Kissell
2000-10-06 4:32 ` Jun Sun
2000-10-05 22:10 ` Kevin D. Kissell
2000-10-05 22:10 ` Kevin D. Kissell
2000-10-06 5:53 ` Jun Sun
2000-10-05 23:14 ` Kevin D. Kissell [this message]
2000-10-05 23:14 ` Kevin D. Kissell
2000-10-06 16:32 ` Ralf Baechle
2000-10-07 1:35 ` Jun Sun
2000-10-06 22:26 ` Ralf Baechle
2000-10-06 16:28 ` Ralf Baechle
2000-10-07 1:24 ` Jun Sun
2000-10-06 20:46 ` Kevin D. Kissell
2000-10-06 20:46 ` Kevin D. Kissell
2000-10-07 7:16 ` Jun Sun
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