lemote-fulong patch update

lemote-fulong patch update

[tiansm]

My boss Fuxin Zhang is busy, and I take the job.
It's my first time to submit patch, correct me if I have done anything wrong

[PATCH 1/16] new files for lemote fulong mini-PC support

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>


Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Songmao Tian <tiansm@lemote.com>
---
 arch/mips/lemote/lm2e/Makefile               |    7 +
 arch/mips/lemote/lm2e/bonito-irq.c           |   74 +++++
 arch/mips/lemote/lm2e/dbg_io.c               |  146 ++++++++++
 arch/mips/lemote/lm2e/irq.c                  |  146 ++++++++++
 arch/mips/lemote/lm2e/pci.c                  |   72 +++++
 arch/mips/lemote/lm2e/prom.c                 |  109 ++++++++
 arch/mips/lemote/lm2e/reset.c                |   46 +++
 arch/mips/lemote/lm2e/setup.c                |  144 ++++++++++
 arch/mips/pci/fixup-lm2e.c                   |  256 +++++++++++++++++
 arch/mips/pci/ops-lm2e.c                     |  153 +++++++++++
 include/asm-mips/mach-lemote/bonito.h        |  381 ++++++++++++++++++++++++++
 include/asm-mips/mach-lemote/dma-coherence.h |   43 +++
 include/asm-mips/mach-lemote/mc146818rtc.h   |   36 +++
 13 files changed, 1613 insertions(+), 0 deletions(-)

diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile
new file mode 100644
index 0000000..0ba6f12
--- /dev/null
+++ b/arch/mips/lemote/lm2e/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for Lemote Fulong mini-PC board.
+#
+
+obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o
+EXTRA_AFLAGS := $(CFLAGS)
+
diff --git a/arch/mips/lemote/lm2e/bonito-irq.c b/arch/mips/lemote/lm2e/bonito-irq.c
new file mode 100644
index 0000000..a81f0d6
--- /dev/null
+++ b/arch/mips/lemote/lm2e/bonito-irq.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/io.h>
+
+#include <bonito.h>
+
+
+static inline void bonito_irq_enable(unsigned int irq)
+{
+	BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE));
+	mmiowb();
+}
+
+static inline void bonito_irq_disable(unsigned int irq)
+{
+	BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE));
+	mmiowb();
+}
+
+static struct irq_chip bonito_irq_type = {
+	.name	= "bonito_irq",
+	.ack	= bonito_irq_disable,
+	.mask	= bonito_irq_disable,
+	.mask_ack = bonito_irq_disable,
+	.unmask	= bonito_irq_enable,
+};
+
+static struct irqaction dma_timeout_irqaction = {
+	.handler	= no_action,
+	.name		= "dma_timeout",
+};
+
+void bonito_irq_init(void)
+{
+	u32 i;
+
+	for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) {
+		set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
+	}
+
+	setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction);
+}
diff --git a/arch/mips/lemote/lm2e/dbg_io.c b/arch/mips/lemote/lm2e/dbg_io.c
new file mode 100644
index 0000000..f54bfaa
--- /dev/null
+++ b/arch/mips/lemote/lm2e/dbg_io.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <asm/types.h>
+#include <linux/init.h>
+#include <asm/serial.h>		/* For the serial port location and base baud */
+
+#define         UART16550_BAUD_2400             2400
+#define         UART16550_BAUD_4800             4800
+#define         UART16550_BAUD_9600             9600
+#define         UART16550_BAUD_19200            19200
+#define         UART16550_BAUD_38400            38400
+#define         UART16550_BAUD_57600            57600
+#define         UART16550_BAUD_115200           115200
+
+#define         UART16550_PARITY_NONE           0
+#define         UART16550_PARITY_ODD            0x08
+#define         UART16550_PARITY_EVEN           0x18
+#define         UART16550_PARITY_MARK           0x28
+#define         UART16550_PARITY_SPACE          0x38
+
+#define         UART16550_DATA_5BIT             0x0
+#define         UART16550_DATA_6BIT             0x1
+#define         UART16550_DATA_7BIT             0x2
+#define         UART16550_DATA_8BIT             0x3
+
+#define         UART16550_STOP_1BIT             0x0
+#define         UART16550_STOP_2BIT             0x4
+
+/* ----------------------------------------------------- */
+
+/* === CONFIG === */
+#ifdef CONFIG_64BIT
+#define         BASE                    (0xffffffffbfd003f8)
+#else
+#define         BASE                    (0xbfd003f8)
+#endif
+
+#define         MAX_BAUD                BASE_BAUD
+/* === END OF CONFIG === */
+
+#define         REG_OFFSET              1
+
+/* register offset */
+#define         OFS_RCV_BUFFER          0
+#define         OFS_TRANS_HOLD          0
+#define         OFS_SEND_BUFFER         0
+#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
+#define         OFS_INTR_ID             (2*REG_OFFSET)
+#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
+#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
+#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
+#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
+#define         OFS_LINE_STATUS         (5*REG_OFFSET)
+#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
+#define         OFS_RS232_INPUT         (6*REG_OFFSET)
+#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
+
+#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
+#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
+
+/* memory-mapped read/write of the port */
+#define         UART16550_READ(y)    (*((volatile u8*)(BASE + y)))
+#define         UART16550_WRITE(y, z)  ((*((volatile u8*)(BASE + y))) = z)
+
+void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
+{
+	/* disable interrupts */
+	UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+	/* set up buad rate */
+	{
+		u32 divisor;
+
+		/* set DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+		/* set divisor */
+		divisor = MAX_BAUD / baud;
+		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
+
+		/* clear DIAB bit */
+		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+	}
+
+	/* set data format */
+	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+static int remoteDebugInitialized = 0;
+
+u8 getDebugChar(void)
+{
+	if (!remoteDebugInitialized) {
+		remoteDebugInitialized = 1;
+		debugInit(UART16550_BAUD_115200,
+			  UART16550_DATA_8BIT,
+			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+	}
+
+	while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0) ;
+	return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+int putDebugChar(u8 byte)
+{
+	if (!remoteDebugInitialized) {
+		remoteDebugInitialized = 1;
+		/* 
+		   debugInit(UART16550_BAUD_115200,
+		   UART16550_DATA_8BIT,
+		   UART16550_PARITY_NONE, UART16550_STOP_1BIT); */
+	}
+
+	while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0) ;
+	UART16550_WRITE(OFS_SEND_BUFFER, byte);
+	return 1;
+}
diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c
new file mode 100644
index 0000000..476ba9e
--- /dev/null
+++ b/arch/mips/lemote/lm2e/irq.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+#include <asm/delay.h>
+#include <bonito.h>
+
+/*
+ * the first level int-handler will jump here if it is a bonito irq
+ */
+static void bonito_irqdispatch(void)
+{
+	u32 int_status;
+	int i;
+
+	/* workaround the IO dma problem: let cpu looping to allow DMA finish */
+	int_status = BONITO_INTISR;
+	if (int_status & (1 << 10)) {
+		while (int_status & (1 << 10)) {
+			udelay(1);
+			int_status = BONITO_INTISR;
+		}
+	}
+
+	/* Get pending sources, masked by current enables */
+	int_status = BONITO_INTISR & BONITO_INTEN;
+
+	if (int_status != 0) {
+		i = __ffs(int_status);
+		int_status &= ~(1 << i);
+		do_IRQ(i +BONITO_IRQ_BASE);
+	}
+	return;
+}
+
+static void i8259_irqdispatch(void)
+{
+	int irq;
+
+	irq = i8259_irq();
+	if (irq >= 0) {
+		do_IRQ(irq);
+	} else {
+		spurious_interrupt();
+	}
+
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
+	if (pending & CAUSEF_IP7) {
+		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
+	} else if (pending & CAUSEF_IP5) {
+		i8259_irqdispatch();
+	} else if (pending & CAUSEF_IP2) {
+		bonito_irqdispatch();
+	} else {
+		spurious_interrupt();
+	}
+}
+
+static struct irqaction cascade_irqaction = {
+	.handler = no_action,
+	.mask = CPU_MASK_NONE,
+	.name = "cascade",
+};
+
+void __init arch_init_irq(void)
+{
+	extern void bonito_irq_init(void);
+
+	printk(KERN_INFO"arch init irq\n");
+	/*
+	 * Clear all of the interrupts while we change the able around a bit.
+	 * int-handler is not on bootstrap
+	 */
+	clear_c0_status(ST0_IM | ST0_BEV);
+	local_irq_disable();
+
+	/* most bonito irq should be level triggered */
+	BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR
+	    | BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
+	BONITO_INTSTEER = 0;
+
+	/* 
+	 * Mask out all interrupt by writing "1" to all bit position in 
+	 * the interrupt reset reg. 
+	 */
+	BONITO_INTENCLR = ~0;
+
+	/* init all controller
+	 *   0-15         ------> i8259 interrupt
+	 *   16-23        ------> mips cpu interrupt
+	 *   32-63        ------> bonito irq
+	 */
+
+	/* Sets the first-level interrupt dispatcher. */
+	mips_cpu_irq_init();
+	init_i8259_irqs();
+	bonito_irq_init();
+
+	/*
+	printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE);
+	printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n", 
+			BONITO_INTEN, BONITO_INTENSET,
+			BONITO_INTENCLR, BONITO_INTISR);
+	*/
+
+	/* bonito irq at IP2 */
+	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
+	/* 8259 irq at IP5 */
+	setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
+
+}
diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c
new file mode 100644
index 0000000..e9c5ce2
--- /dev/null
+++ b/arch/mips/lemote/lm2e/pci.c
@@ -0,0 +1,72 @@
+/*
+ * pci.c
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+extern struct pci_ops loongson2e_pci_pci_ops;
+
+static struct resource loongson2e_pci_mem_resource = {
+	.name   = "LOONGSON2E PCI MEM",
+	.start  = 0x14000000UL,
+	.end    = 0x1fffffffUL,
+	.flags  = IORESOURCE_MEM,
+};
+
+static struct resource loongson2e_pci_io_resource = {
+	.name   = "LOONGSON2E PCI IO MEM",
+	.start  = 0x00004000UL,
+	.end    = 0x1fffffffUL,
+	.flags  = IORESOURCE_IO,
+};
+
+
+static struct pci_controller  loongson2e_pci_controller = {
+	.pci_ops        = &loongson2e_pci_pci_ops,
+	.io_resource    = &loongson2e_pci_io_resource,
+	.mem_resource   = &loongson2e_pci_mem_resource,
+	.mem_offset     = 0x00000000UL,
+	.io_offset      = 0x00000000UL,
+};
+
+
+static int __init pcibios_init(void)
+{
+	extern int pci_probe_only;
+	pci_probe_only = 0;
+
+#ifdef CONFIG_TRACE_BOOT
+	printk(KERN_INFO"arch_initcall:pcibios_init\n");
+	printk(KERN_INFO"register_pci_controller : %x\n",&loongson2e_pci_controller);
+#endif
+	register_pci_controller(&loongson2e_pci_controller);
+	return 0;
+}
+
+arch_initcall(pcibios_init);
diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c
new file mode 100644
index 0000000..bb70a69
--- /dev/null
+++ b/arch/mips/lemote/lm2e/prom.c
@@ -0,0 +1,109 @@
+/*
+ * Based on Ocelot Linux port, which is
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * Copyright 2003 ICT CAS
+ * Author: Michael Guo <guoyi@ict.ac.cn>
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+
+extern unsigned long bus_clock;
+extern unsigned long cpu_clock;
+extern unsigned int memsize, highmemsize;
+extern int putDebugChar(unsigned char byte);
+
+static int argc;
+/* pmon passes arguments in 32bit pointers */
+static int *arg;
+static int *env;
+
+const char *get_system_type(void)
+{
+	return "lemote-fulong";
+}
+
+void __init prom_init_cmdline(void)
+{
+	int i;
+	long l;
+
+	/* arg[0] is "g", the rest is boot parameters */
+	arcs_cmdline[0] = '\0';
+	for (i = 1; i < argc; i++) {
+		l = (long)arg[i];
+		if (strlen(arcs_cmdline) + strlen(((char *)l) + 1)
+		    >= sizeof(arcs_cmdline))
+			break;
+		strcat(arcs_cmdline, ((char *)l));
+		strcat(arcs_cmdline, " ");
+	}
+}
+
+void __init prom_init(void)
+{
+	long l;
+	argc = fw_arg0;
+	arg = (int *)fw_arg1;
+	env = (int *)fw_arg2;
+
+	mips_machgroup = MACH_GROUP_LEMOTE;
+	mips_machtype = MACH_LEMOTE_FULONG;
+
+	prom_init_cmdline();
+
+	if ((strstr(arcs_cmdline, "console=")) == NULL)
+		strcat(arcs_cmdline, " console=ttyS0,115200");
+	if ((strstr(arcs_cmdline, "root=")) == NULL)
+		strcat(arcs_cmdline, " root=/dev/hda1");
+
+	l = (long)*env;
+	while (l != 0) {
+		if (strncmp("busclock", (char *)l, strlen("busclock")) == 0) {
+			bus_clock = simple_strtol((char *)l + strlen("busclock="), 
+					NULL, 10);
+		}
+		if (strncmp("cpuclock", (char *)l, strlen("cpuclock")) == 0) {
+			cpu_clock = simple_strtol((char *)l + strlen("cpuclock="), 
+					NULL, 10);
+		}
+		if (strncmp("memsize", (char *)l, strlen("memsize")) == 0) {
+			memsize = simple_strtol((char *)l + strlen("memsize="),
+						NULL, 10);
+		}
+		if (strncmp("highmemsize", (char *)l, strlen("highmemsize")) == 0) {
+			highmemsize = simple_strtol((char *)l + strlen("highmemsize="),
+					  NULL, 10);
+		}
+		env++;
+		l = (long)*env;
+	}
+	if (memsize == 0)
+		memsize = 256;
+
+	printk("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n",
+	       bus_clock, cpu_clock, memsize, highmemsize);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+void prom_putchar(char c)
+{
+	putDebugChar(c);
+}
diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c
new file mode 100644
index 0000000..0738732
--- /dev/null
+++ b/arch/mips/lemote/lm2e/reset.c
@@ -0,0 +1,46 @@
+/*
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <linux/delay.h>
+
+static void loongson2e_restart(char *command)
+{
+#ifdef CONFIG_32BIT
+	*(unsigned long *)0xbfe00104 &= ~(1 << 2);
+	*(unsigned long *)0xbfe00104 |= (1 << 2);
+#else
+	*(unsigned long *)0xffffffffbfe00104 &= ~(1 << 2);
+	*(unsigned long *)0xffffffffbfe00104 |= (1 << 2);
+#endif
+	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+}
+
+static void loongson2e_halt(void)
+{
+	while (1) ;
+}
+
+static void loongson2e_power_off(void)
+{
+	loongson2e_halt();
+}
+
+void mips_reboot_setup(void)
+{
+	_machine_restart = loongson2e_restart;
+	_machine_halt = loongson2e_halt;
+	pm_power_off = loongson2e_power_off;
+}
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c
new file mode 100644
index 0000000..b372c58
--- /dev/null
+++ b/arch/mips/lemote/lm2e/setup.c
@@ -0,0 +1,144 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * setup.c - board dependent boot routines
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+
+#include <asm/mc146818-time.h>
+#include <asm/time.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pci.h>
+#include <asm/wbflush.h>
+
+#include <linux/bootmem.h>
+#include <linux/tty.h>
+#include <linux/mc146818rtc.h>
+
+#ifdef CONFIG_VT
+#include <linux/console.h>
+#include <linux/screen_info.h>
+#endif
+
+extern void mips_reboot_setup(void);
+
+#ifdef CONFIG_64BIT
+#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p)))
+#else
+#define PTR_PAD(p) (p)
+#endif
+
+unsigned long cpu_clock;
+unsigned long bus_clock;
+unsigned int memsize;
+unsigned int highmemsize = 0;
+
+void __init plat_timer_setup(struct irqaction *irq)
+{
+	setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
+}
+
+static void __init loongson2e_time_init(void)
+{
+	/* setup mips r4k timer */
+	mips_hpt_frequency = cpu_clock / 2;
+}
+
+static unsigned long __init mips_rtc_get_time(void)
+{
+	return mc146818_get_cmos_time();
+}
+
+void (*__wbflush) (void);
+static void wbflush_loongson2e(void)
+{
+	asm(".set\tpush\n\t"
+	    ".set\tnoreorder\n\t"
+	    ".set mips3\n\t"
+	    "sync\n\t"
+	    "nop\n\t"
+	    ".set\tpop\n\t"
+	    ".set mips0\n\t");
+}
+
+void __init plat_mem_setup(void)
+{
+	set_io_port_base(PTR_PAD(0xbfd00000));
+
+	ioport_resource.start = 0;
+	ioport_resource.end = 0xffffffff;
+	iomem_resource.start = 0;
+	iomem_resource.end = 0xffffffff;
+
+	mips_reboot_setup();
+
+	board_time_init = loongson2e_time_init;
+	rtc_mips_get_time = mips_rtc_get_time;
+
+	__wbflush = wbflush_loongson2e;
+
+	//add_memory_region(0x100000, (memsize<<20) - 0x100000, BOOT_MEM_RAM);  
+	add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+#ifdef CONFIG_64BIT
+	if (highmemsize > 0) {
+		add_memory_region(0x10000000, 0x10000000, BOOT_MEM_RESERVED);
+		add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM);
+	}
+#endif
+
+#ifdef CONFIG_VT
+#if defined(CONFIG_VGA_CONSOLE)
+	conswitchp = &vga_con;
+
+	screen_info = (struct screen_info) {
+		0, 25,		/* orig-x, orig-y */
+		    0,		/* unused */
+		    0,		/* orig-video-page */
+		    0,		/* orig-video-mode */
+		    80,		/* orig-video-cols */
+		    0, 0, 0,	/* ega_ax, ega_bx, ega_cx */
+		    25,		/* orig-video-lines */
+		    VIDEO_TYPE_VGAC,	/* orig-video-isVGA */
+		    16		/* orig-video-points */
+	};
+#elif defined(CONFIG_DUMMY_CONSOLE)
+	conswitchp = &dummy_con;
+#endif
+#endif
+
+}
+
+#include <linux/module.h>
+EXPORT_SYMBOL(__wbflush);
+
diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c
new file mode 100644
index 0000000..277f9fe
--- /dev/null
+++ b/arch/mips/pci/fixup-lm2e.c
@@ -0,0 +1,256 @@
+/*
+ * fixup-lm2e.c
+ *
+ * Copyright (C) 2004 ICT CAS
+ * Author: Li xiaoyu, ICT CAS
+ *   lixy@ict.ac.cn
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <bonito.h>
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	unsigned int val;
+	if (PCI_SLOT(dev->devfn) == 4) {	/* wireless card(notebook) */
+		dev->irq = BONITO_IRQ_BASE + 26;
+		return dev->irq;
+	} else if (PCI_SLOT(dev->devfn) == 5) {	/* via686b */
+		switch (PCI_FUNC(dev->devfn)) {
+		case 2:
+			dev->irq = 10;
+			break;
+		case 3:
+			dev->irq = 11;
+			break;
+		case 5:
+			dev->irq = 9;
+			break;
+		}
+		return dev->irq;
+	} else if (PCI_SLOT(dev->devfn) == 6) {	/* radeon 7000 */
+		dev->irq = BONITO_IRQ_BASE + 27;
+		return dev->irq;
+	} else if (PCI_SLOT(dev->devfn) == 7) {	/* 8139 */
+		dev->irq = BONITO_IRQ_BASE + 26;
+		return dev->irq;
+	} else if (PCI_SLOT(dev->devfn) == 8) {	/* nec usb */
+		switch (PCI_FUNC(dev->devfn)) {
+		case 0:
+			dev->irq = BONITO_IRQ_BASE + 26;
+			break;
+		case 1:
+			dev->irq = BONITO_IRQ_BASE + 27;
+			dev->irq = 11;
+			break;
+		case 2:
+			dev->irq = BONITO_IRQ_BASE + 28;
+			break;
+		}
+		pci_read_config_dword(dev, 0xe0, &val);
+		pci_write_config_dword(dev, 0xe0, (val & ~7) | 0x4);
+		pci_write_config_dword(dev, 0xe4, 1 << 5);
+		return dev->irq;
+	} else
+		return 0;
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+	return 0;
+}
+
+static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
+{
+	unsigned char c;
+
+	printk(KERN_INFO"via686b fix: ISA bridge\n");
+
+	/*  Enable I/O Recovery time */
+	pci_write_config_byte(pdev, 0x40, 0x08);
+
+	/*  Enable ISA refresh */
+	pci_write_config_byte(pdev, 0x41, 0x01);
+
+	/*  disable ISA line buffer */
+	pci_write_config_byte(pdev, 0x45, 0x00);
+
+	/*  Gate INTR, and flush line buffer */
+	pci_write_config_byte(pdev, 0x46, 0xe0);
+
+	/*  Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */
+	//pci_write_config_byte(pdev, 0x47, 0x20); 
+	/*  enable PCI Delay Transaction, Enable EISA ports 4D0/4D1. 
+	 *  enable time-out timer 
+	 */
+	pci_write_config_byte(pdev, 0x47, 0xe6);
+
+	/* enable level trigger on pci irqs: 9,10,11,13 */
+	/* important! without this PCI interrupts won't work */
+	outb(0x2e, 0x4d1);
+
+	/*  512 K PCI Decode */
+	pci_write_config_byte(pdev, 0x48, 0x01);
+
+	/*  Wait for PGNT before grant to ISA Master/DMA */
+	pci_write_config_byte(pdev, 0x4a, 0x84);
+
+	/*  Plug'n'Play */
+	/*  Parallel DRQ 3, Floppy DRQ 2 (default) */
+	pci_write_config_byte(pdev, 0x50, 0x0e);
+
+	/*  IRQ Routing for Floppy and Parallel port */
+	/*  IRQ 6 for floppy, IRQ 7 for parallel port */
+	pci_write_config_byte(pdev, 0x51, 0x76);
+
+	/*  IRQ Routing for serial ports (take IRQ 3 and 4) */
+	pci_write_config_byte(pdev, 0x52, 0x34);
+
+	/*  All IRQ's level triggered. */
+	pci_write_config_byte(pdev, 0x54, 0x00);
+
+	/* route PIRQA-D irq */
+	pci_write_config_byte(pdev, 0x55, 0x90);	/* bit 7-4, PIRQA */
+	pci_write_config_byte(pdev, 0x56, 0xba);	/* bit 7-4, PIRQC; 3-0, PIRQB */
+	pci_write_config_byte(pdev, 0x57, 0xd0);	/* bit 7-4, PIRQD */
+
+	/* enable function 5/6, audio/modem */
+	pci_read_config_byte(pdev, 0x85, &c);
+	c &= ~(0x3 << 2);
+	pci_write_config_byte(pdev, 0x85, c);
+
+	printk(KERN_INFO"via686b fix: ISA bridge done\n");
+}
+
+static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
+{
+	printk(KERN_INFO"via686b fix: IDE\n");
+
+	/* Modify IDE controller setup */
+	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48);
+	pci_write_config_byte(pdev, PCI_COMMAND,
+			      PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+			      PCI_COMMAND_MASTER);
+	pci_write_config_byte(pdev, 0x40, 0x0b);
+	/* legacy mode */
+	pci_write_config_byte(pdev, 0x42, 0x09);
+
+#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */
+	/* disable read prefetch/write post buffers */
+	pci_write_config_byte(pdev, 0x41, 0x02);  
+
+	/* use 3/4 as fifo thresh hold  */
+	pci_write_config_byte(pdev, 0x43, 0x0a);
+	pci_write_config_byte(pdev, 0x44, 0x00);
+
+	pci_write_config_byte(pdev, 0x45, 0x00);
+#else
+	pci_write_config_byte(pdev, 0x41, 0xc2);
+	pci_write_config_byte(pdev, 0x43, 0x35);
+	pci_write_config_byte(pdev, 0x44, 0x1c);
+
+	pci_write_config_byte(pdev, 0x45, 0x10);
+#endif
+
+	printk(KERN_INFO"via686b fix: IDE done\n");
+}
+
+static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev)
+{
+	unsigned int val;
+	unsigned char c;
+
+	/* enable IO */
+	pci_write_config_byte(pdev, PCI_COMMAND,
+			      PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+			      PCI_COMMAND_MASTER);
+	pci_read_config_dword(pdev, 0x4, &val);
+	pci_write_config_dword(pdev, 0x4, val | 1);
+
+	/* route ac97 IRQ */
+	pci_write_config_byte(pdev, 0x3c, 9);
+	pdev->irq = 9;
+	printk(KERN_INFO"ac97 interrupt = 9\n");
+
+	pci_read_config_byte(pdev, 0x8, &c);
+	printk(KERN_INFO"ac97 rev=%d\n", c);
+
+	/* link control: enable link & SGD PCM output */
+	pci_write_config_byte(pdev, 0x41, 0xcc);
+
+	/* disable game port, FM, midi, sb, enable write to reg2c-2f */
+	pci_write_config_byte(pdev, 0x42, 0x20);
+
+	printk(KERN_INFO"Setting sub-vendor ID & device ID\n");
+
+	/* we are using Avance logic codec */
+	pci_write_config_word(pdev, 0x2c, 0x1005);
+	pci_write_config_word(pdev, 0x2e, 0x4710);
+	pci_read_config_dword(pdev, 0x2c, &val);
+	printk(KERN_INFO"sub vendor-device id=%x\n", val);
+
+	pci_write_config_byte(pdev, 0x42, 0x0);
+}
+
+static void __init loongson2e_fixup_pcimap(struct pci_dev *pdev)
+{
+	static int first = 1;
+
+	(void)pdev;
+	if (first)
+		first = 0;
+	else
+		return;
+
+	/* local to PCI mapping: [256M,512M] -> [256M,512M]; differ from pmon */
+	/* 
+	 *       cpu address space [256M,448M] is window for accessing pci space
+	 *       we set pcimap_lo[0,1,2] to map it to pci space [256M,448M]
+	 *        pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0
+	 */
+	/* 1,00 0110 ,0001 01,00 0000 */
+	BONITO_PCIMAP = 0x46140;
+	//1, 00 0010, 0000,01, 00 0000
+	//BONITO_PCIMAP = 0x42040;
+
+	/* 
+	 * PCI to local mapping: [2G,2G+256M] -> [0,256M]
+	 */
+	BONITO_PCIBASE0 = 0x80000000;
+	BONITO_PCIBASE1 = 0x00800000;
+	BONITO_PCIBASE2 = 0x90000000;
+
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, loongson2e_fixup_pcimap);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
+			 loongson2e_686b_func0_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
+			 loongson2e_686b_func1_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5,
+			 loongson2e_686b_func5_fixup);
diff --git a/arch/mips/pci/ops-lm2e.c b/arch/mips/pci/ops-lm2e.c
new file mode 100644
index 0000000..b868029
--- /dev/null
+++ b/arch/mips/pci/ops-lm2e.c
@@ -0,0 +1,153 @@
+/*
+ * ops-lm2e.c
+ *
+ * Copyright (C) 2004 ICT CAS
+ * Author: Li xiaoyu, ICT CAS
+ *   lixy@ict.ac.cn
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+
+#include <bonito.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+static inline void bflush(void)
+{
+	/* flush Bonito register writes */
+	(void)BONITO_PCICMD;
+}
+
+static int lm2e_pci_config_access(unsigned char access_type,
+				  struct pci_bus *bus, unsigned int devfn,
+				  int where, u32 *data)
+{
+	u32 busnum = bus->number;
+	u32 addr, type;
+	void *addrp;
+	int device = PCI_SLOT(devfn);
+	int function = PCI_FUNC(devfn);
+	int reg = where & ~3;
+
+	if (busnum == 0) {
+		/* Type 0 configuration on onboard PCI bus */
+		if (device > 20 || function > 7) {
+			*data = -1;	/* device out of range */
+			return PCIBIOS_DEVICE_NOT_FOUND;
+		}
+		addr = (1 << (device + 11)) | (function << 8) | reg;
+		type = 0;
+	} else {
+		/* Type 1 configuration on offboard PCI bus */
+		if (device > 31 || function > 7) {
+			*data = -1;	/* device out of range */
+			return PCIBIOS_DEVICE_NOT_FOUND;
+		}
+		addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+		type = 0x10000;
+	}
+
+	/* clear aborts */
+	BONITO_PCICMD |= BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT;
+
+	BONITO_PCIMAP_CFG = (addr >> 16) | type;
+	bflush();
+
+	addrp = (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (addr & 0xffff));
+	if (access_type == PCI_ACCESS_WRITE) {
+		*(volatile unsigned int *)addrp = cpu_to_le32(*data);
+	} else {
+		*data = le32_to_cpu(*(volatile unsigned int *)addrp);
+	}
+	if (BONITO_PCICMD & (BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT)) {
+		BONITO_PCICMD |= BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT;
+		*data = -1;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+
+}
+
+static int lm2e_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
+				 int where, int size, u32 * val)
+{
+	u32 data = 0;
+
+	int ret = lm2e_pci_config_access(PCI_ACCESS_READ, 
+			bus, devfn, where, &data); 
+
+	if (ret != PCIBIOS_SUCCESSFUL)
+		return ret;
+
+	if (size == 1)
+		*val = (data >> ((where & 3) << 3)) & 0xff;
+	else if (size == 2)
+		*val = (data >> ((where & 3) << 3)) & 0xffff;
+	else
+		*val = data;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int lm2e_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
+				  int where, int size, u32 val)
+{
+	u32 data = 0;
+	int ret;
+
+	if (size == 4)
+		data = val;
+	else {
+		ret = lm2e_pci_config_access(PCI_ACCESS_READ, 
+				bus, devfn, where, &data);
+		if (ret != PCIBIOS_SUCCESSFUL)
+			return ret;
+
+		if (size == 1)
+			data = (data & ~(0xff << ((where & 3) << 3))) |
+			    (val << ((where & 3) << 3));
+		else if (size == 2)
+			data = (data & ~(0xffff << ((where & 3) << 3))) |
+			    (val << ((where & 3) << 3));
+	}
+
+	ret = lm2e_pci_config_access(PCI_ACCESS_WRITE, 
+			bus, devfn, where, &data);
+	if (ret != PCIBIOS_SUCCESSFUL)
+		return ret;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops loongson2e_pci_pci_ops = {
+	.read = lm2e_pci_pcibios_read,
+	.write = lm2e_pci_pcibios_write
+};
diff --git a/include/asm-mips/mach-lemote/bonito.h b/include/asm-mips/mach-lemote/bonito.h
new file mode 100644
index 0000000..83f7ac3
--- /dev/null
+++ b/include/asm-mips/mach-lemote/bonito.h
@@ -0,0 +1,381 @@
+/*
+ * Based on Algorithmics header
+ */
+
+#ifndef _BONITO_H
+#define _BONITI_H
+
+#ifdef __ASSEMBLER__
+
+/* offsets from base register */
+#define BONITO(x)	(x)
+
+#else /* !__ASSEMBLER */
+
+/* offsets from base pointer */
+#define BONITO(x) *(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))
+
+#endif /* __ASSEMBLER__ */
+
+#define BONITO_BOOT_BASE		0x1fc00000
+#define BONITO_BOOT_SIZE		0x00100000
+#define BONITO_BOOT_TOP 		(BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
+#define BONITO_FLASH_BASE		0x1c000000
+#define BONITO_FLASH_SIZE		0x03000000
+#define BONITO_FLASH_TOP		(BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
+#define BONITO_SOCKET_BASE		0x1f800000
+#define BONITO_SOCKET_SIZE		0x00400000
+#define BONITO_SOCKET_TOP		(BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
+#define BONITO_REG_BASE 		0x1fe00000
+#define BONITO_REG_SIZE 		0x00040000
+#define BONITO_REG_TOP			(BONITO_REG_BASE+BONITO_REG_SIZE-1)
+#define BONITO_DEV_BASE 		0x1ff00000
+#define BONITO_DEV_SIZE 		0x00100000
+#define BONITO_DEV_TOP			(BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
+#define BONITO_PCILO_BASE		0x10000000
+#define BONITO_PCILO_SIZE		0x0c000000
+#define BONITO_PCILO_TOP		(BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
+#define BONITO_PCILO0_BASE		0x10000000
+#define BONITO_PCILO1_BASE		0x14000000
+#define BONITO_PCILO2_BASE		0x18000000
+#define BONITO_PCIHI_BASE		0x20000000
+#define BONITO_PCIHI_SIZE		0x20000000
+#define BONITO_PCIHI_TOP		(BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
+#define BONITO_PCIIO_BASE		0x1fd00000
+#define BONITO_PCIIO_SIZE		0x00100000
+#define BONITO_PCIIO_TOP		(BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
+#define BONITO_PCICFG_BASE		0x1fe80000
+#define BONITO_PCICFG_SIZE		0x00080000
+#define BONITO_PCICFG_TOP		(BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
+
+/* Bonito Register Bases */
+
+#define BONITO_PCICONFIGBASE		0x00
+#define BONITO_REGBASE			0x100
+
+/* PCI Configuration  Registers */
+
+#define BONITO_PCI_REG(x)               BONITO(BONITO_PCICONFIGBASE + (x))
+#define BONITO_PCIDID			BONITO_PCI_REG(0x00)
+#define BONITO_PCICMD			BONITO_PCI_REG(0x04)
+#define BONITO_PCICLASS 		BONITO_PCI_REG(0x08)
+#define BONITO_PCILTIMER		BONITO_PCI_REG(0x0c)
+#define BONITO_PCIBASE0 		BONITO_PCI_REG(0x10)
+#define BONITO_PCIBASE1 		BONITO_PCI_REG(0x14)
+#define BONITO_PCIBASE2 		BONITO_PCI_REG(0x18)
+#define BONITO_PCIEXPRBASE		BONITO_PCI_REG(0x30)
+#define BONITO_PCIINT			BONITO_PCI_REG(0x3c)
+
+#define BONITO_PCICMD_PERR		0x80000000
+#define BONITO_PCICMD_SERR		0x40000000
+#define BONITO_PCICMD_MABORT		0x20000000
+#define BONITO_PCICMD_MTABORT		0x10000000
+#define BONITO_PCICMD_TABORT		0x08000000
+#define BONITO_PCICMD_MPERR	 	0x01000000
+#define BONITO_PCICMD_PERRRESPEN	0x00000040
+#define BONITO_PCICMD_ASTEPEN		0x00000080
+#define BONITO_PCICMD_SERREN		0x00000100
+#define BONITO_PCILTIMER_BUSLATENCY	0x0000ff00
+#define BONITO_PCILTIMER_BUSLATENCY_SHIFT	8
+
+/* 1. Bonito h/w Configuration */
+/* Power on register */
+
+#define BONITO_BONPONCFG		BONITO(BONITO_REGBASE + 0x00)
+
+#define BONITO_BONPONCFG_SYSCONTROLLERRD	0x00040000
+#define BONITO_BONPONCFG_ROMCS1SAMP	0x00020000
+#define BONITO_BONPONCFG_ROMCS0SAMP	0x00010000
+#define BONITO_BONPONCFG_CPUBIGEND	0x00004000
+#define BONITO_BONPONCFG_CPUPARITY	0x00002000
+#define BONITO_BONPONCFG_CPUTYPE	0x00000007
+#define BONITO_BONPONCFG_CPUTYPE_SHIFT	0
+#define BONITO_BONPONCFG_PCIRESET_OUT	0x00000008
+#define BONITO_BONPONCFG_IS_ARBITER	0x00000010
+#define BONITO_BONPONCFG_ROMBOOT	0x000000c0
+#define BONITO_BONPONCFG_ROMBOOT_SHIFT	6
+
+#define BONITO_BONPONCFG_ROMBOOT_FLASH	(0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_SDRAM	(0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_CPURESET	(0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+
+#define BONITO_BONPONCFG_ROMCS0WIDTH	0x00000100
+#define BONITO_BONPONCFG_ROMCS1WIDTH	0x00000200
+#define BONITO_BONPONCFG_ROMCS0FAST	0x00000400
+#define BONITO_BONPONCFG_ROMCS1FAST	0x00000800
+#define BONITO_BONPONCFG_CONFIG_DIS	0x00000020
+
+/* Other Bonito configuration */
+
+#define BONITO_BONGENCFG_OFFSET         0x4
+#define BONITO_BONGENCFG		BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
+
+#define BONITO_BONGENCFG_DEBUGMODE	0x00000001
+#define BONITO_BONGENCFG_SNOOPEN	0x00000002
+#define BONITO_BONGENCFG_CPUSELFRESET	0x00000004
+
+#define BONITO_BONGENCFG_FORCE_IRQA	0x00000008
+#define BONITO_BONGENCFG_IRQA_ISOUT	0x00000010
+#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
+#define BONITO_BONGENCFG_BYTESWAP	0x00000040
+
+#define BONITO_BONGENCFG_UNCACHED	0x00000080
+#define BONITO_BONGENCFG_PREFETCHEN	0x00000100
+#define BONITO_BONGENCFG_WBEHINDEN	0x00000200
+#define BONITO_BONGENCFG_CACHEALG	0x00000c00
+#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
+#define BONITO_BONGENCFG_PCIQUEUE	0x00001000
+#define BONITO_BONGENCFG_CACHESTOP	0x00002000
+#define BONITO_BONGENCFG_MSTRBYTESWAP	0x00004000
+#define BONITO_BONGENCFG_BUSERREN	0x00008000
+#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
+#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT	0x00020000
+
+/* 2. IO & IDE configuration */
+
+#define BONITO_IODEVCFG 		BONITO(BONITO_REGBASE + 0x08)
+
+/* 3. IO & IDE configuration */
+
+#define BONITO_SDCFG			BONITO(BONITO_REGBASE + 0x0c)
+
+/* 4. PCI address map control */
+
+#define BONITO_PCIMAP			BONITO(BONITO_REGBASE + 0x10)
+#define BONITO_PCIMEMBASECFG		BONITO(BONITO_REGBASE + 0x14)
+#define BONITO_PCIMAP_CFG		BONITO(BONITO_REGBASE + 0x18)
+
+/* 5. ICU & GPIO regs */
+
+/* GPIO Regs - r/w */
+
+#define BONITO_GPIODATA_OFFSET          0x1c
+#define BONITO_GPIODATA 		BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
+#define BONITO_GPIOIE			BONITO(BONITO_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define BONITO_INTEDGE			BONITO(BONITO_REGBASE + 0x24)
+#define BONITO_INTSTEER 		BONITO(BONITO_REGBASE + 0x28)
+#define BONITO_INTPOL			BONITO(BONITO_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define BONITO_INTENSET 		BONITO(BONITO_REGBASE + 0x30)
+#define BONITO_INTENCLR 		BONITO(BONITO_REGBASE + 0x34)
+#define BONITO_INTEN			BONITO(BONITO_REGBASE + 0x38)
+#define BONITO_INTISR			BONITO(BONITO_REGBASE + 0x3c)
+
+/* PCI mail boxes */
+
+#define BONITO_PCIMAIL0_OFFSET          0x40
+#define BONITO_PCIMAIL1_OFFSET          0x44
+#define BONITO_PCIMAIL2_OFFSET          0x48
+#define BONITO_PCIMAIL3_OFFSET          0x4c
+#define BONITO_PCIMAIL0 		BONITO(BONITO_REGBASE + 0x40)
+#define BONITO_PCIMAIL1 		BONITO(BONITO_REGBASE + 0x44)
+#define BONITO_PCIMAIL2 		BONITO(BONITO_REGBASE + 0x48)
+#define BONITO_PCIMAIL3 		BONITO(BONITO_REGBASE + 0x4c)
+
+/* 6. PCI cache */
+
+#define BONITO_PCICACHECTRL		BONITO(BONITO_REGBASE + 0x50)
+#define BONITO_PCICACHETAG		BONITO(BONITO_REGBASE + 0x54)
+
+#define BONITO_PCIBADADDR		BONITO(BONITO_REGBASE + 0x58)
+#define BONITO_PCIMSTAT 		BONITO(BONITO_REGBASE + 0x5c)
+
+/*
+#define BONITO_PCIRDPOST		BONITO(BONITO_REGBASE + 0x60)
+#define BONITO_PCIDATA			BONITO(BONITO_REGBASE + 0x64)
+*/
+
+/* 7. IDE DMA & Copier */
+
+#define BONITO_CONFIGBASE		0x000
+#define BONITO_BONITOBASE		0x100
+#define BONITO_LDMABASE 		0x200
+#define BONITO_COPBASE			0x300
+#define BONITO_REG_BLOCKMASK		0x300
+
+#define BONITO_LDMACTRL 		BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMASTAT 		BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMAADDR 		BONITO(BONITO_LDMABASE + 0x4)
+#define BONITO_LDMAGO			BONITO(BONITO_LDMABASE + 0x8)
+#define BONITO_LDMADATA 		BONITO(BONITO_LDMABASE + 0xc)
+
+#define BONITO_COPCTRL			BONITO(BONITO_COPBASE + 0x0)
+#define BONITO_COPSTAT			BONITO(BONITO_COPBASE + 0x0)
+#define BONITO_COPPADDR 		BONITO(BONITO_COPBASE + 0x4)
+#define BONITO_COPDADDR 		BONITO(BONITO_COPBASE + 0x8)
+#define BONITO_COPGO			BONITO(BONITO_COPBASE + 0xc)
+
+/* ###### Bit Definitions for individual Registers #### */
+
+/* Gen DMA. */
+
+#define BONITO_IDECOPDADDR_DMA_DADDR	0x0ffffffc
+#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT	2
+#define BONITO_IDECOPPADDR_DMA_PADDR	0xfffffffc
+#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT	2
+#define BONITO_IDECOPGO_DMA_SIZE	0x0000fffe
+#define BONITO_IDECOPGO_DMA_SIZE_SHIFT	0
+#define BONITO_IDECOPGO_DMA_WRITE	0x00010000
+#define BONITO_IDECOPGO_DMAWCOUNT	0x000f0000
+#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT	16
+
+#define BONITO_IDECOPCTRL_DMA_STARTBIT	0x80000000
+#define BONITO_IDECOPCTRL_DMA_RSTBIT	0x40000000
+
+/* DRAM - sdCfg */
+
+#define BONITO_SDCFG_AROWBITS		0x00000003
+#define BONITO_SDCFG_AROWBITS_SHIFT	0
+#define BONITO_SDCFG_ACOLBITS		0x0000000c
+#define BONITO_SDCFG_ACOLBITS_SHIFT	2
+#define BONITO_SDCFG_ABANKBIT		0x00000010
+#define BONITO_SDCFG_ASIDES		0x00000020
+#define BONITO_SDCFG_AABSENT		0x00000040
+#define BONITO_SDCFG_AWIDTH64		0x00000080
+
+#define BONITO_SDCFG_BROWBITS		0x00000300
+#define BONITO_SDCFG_BROWBITS_SHIFT	8
+#define BONITO_SDCFG_BCOLBITS		0x00000c00
+#define BONITO_SDCFG_BCOLBITS_SHIFT	10
+#define BONITO_SDCFG_BBANKBIT		0x00001000
+#define BONITO_SDCFG_BSIDES		0x00002000
+#define BONITO_SDCFG_BABSENT		0x00004000
+#define BONITO_SDCFG_BWIDTH64		0x00008000
+
+#define BONITO_SDCFG_EXTRDDATA		0x00010000
+#define BONITO_SDCFG_EXTRASCAS		0x00020000
+#define BONITO_SDCFG_EXTPRECH		0x00040000
+#define BONITO_SDCFG_EXTRASWIDTH	0x00180000
+#define BONITO_SDCFG_EXTRASWIDTH_SHIFT	19
+#define BONITO_SDCFG_DRAMRESET		0x00200000
+#define BONITO_SDCFG_DRAMEXTREGS	0x00400000
+#define BONITO_SDCFG_DRAMPARITY 	0x00800000
+
+/* PCI Cache - pciCacheCtrl */
+
+#define BONITO_PCICACHECTRL_CACHECMD	0x00000007
+#define BONITO_PCICACHECTRL_CACHECMD_SHIFT	0
+#define BONITO_PCICACHECTRL_CACHECMDLINE	0x00000018
+#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT	3
+#define BONITO_PCICACHECTRL_CMDEXEC	0x00000020
+
+#define BONITO_IODEVCFG_BUFFBIT_CS0	0x00000001
+#define BONITO_IODEVCFG_SPEEDBIT_CS0	0x00000002
+#define BONITO_IODEVCFG_MOREABITS_CS0	0x00000004
+
+#define BONITO_IODEVCFG_BUFFBIT_CS1	0x00000008
+#define BONITO_IODEVCFG_SPEEDBIT_CS1	0x00000010
+#define BONITO_IODEVCFG_MOREABITS_CS1	0x00000020
+
+#define BONITO_IODEVCFG_BUFFBIT_CS2	0x00000040
+#define BONITO_IODEVCFG_SPEEDBIT_CS2	0x00000080
+#define BONITO_IODEVCFG_MOREABITS_CS2	0x00000100
+
+#define BONITO_IODEVCFG_BUFFBIT_CS3	0x00000200
+#define BONITO_IODEVCFG_SPEEDBIT_CS3	0x00000400
+#define BONITO_IODEVCFG_MOREABITS_CS3	0x00000800
+
+#define BONITO_IODEVCFG_BUFFBIT_IDE	0x00001000
+#define BONITO_IODEVCFG_SPEEDBIT_IDE	0x00002000
+#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
+#define BONITO_IODEVCFG_MODEBIT_IDE	0x00008000
+#define BONITO_IODEVCFG_DMAON_IDE	0x001f0000
+#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
+#define BONITO_IODEVCFG_DMAOFF_IDE	0x01e00000
+#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT	21
+#define BONITO_IODEVCFG_EPROMSPLIT	0x02000000
+
+/* gpio */
+#define BONITO_GPIO_GPIOW		0x000003ff
+#define BONITO_GPIO_GPIOW_SHIFT 	0
+#define BONITO_GPIO_GPIOR		0x01ff0000
+#define BONITO_GPIO_GPIOR_SHIFT 	16
+#define BONITO_GPIO_GPINR		0xfe000000
+#define BONITO_GPIO_GPINR_SHIFT 	25
+#define BONITO_GPIO_IOW(N)		(1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
+#define BONITO_GPIO_IOR(N)		(1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
+#define BONITO_GPIO_INR(N)		(1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
+
+/* ICU */
+#define BONITO_ICU_MBOXES		0x0000000f
+#define BONITO_ICU_MBOXES_SHIFT 	0
+#define BONITO_ICU_DMARDY		0x00000010
+#define BONITO_ICU_DMAEMPTY		0x00000020
+#define BONITO_ICU_COPYRDY		0x00000040
+#define BONITO_ICU_COPYEMPTY		0x00000080
+#define BONITO_ICU_COPYERR		0x00000100
+#define BONITO_ICU_PCIIRQ		0x00000200
+#define BONITO_ICU_MASTERERR		0x00000400
+#define BONITO_ICU_SYSTEMERR		0x00000800
+#define BONITO_ICU_DRAMPERR		0x00001000
+#define BONITO_ICU_RETRYERR		0x00002000
+#define BONITO_ICU_GPIOS		0x01ff0000
+#define BONITO_ICU_GPIOS_SHIFT		16
+#define BONITO_ICU_GPINS		0x7e000000
+#define BONITO_ICU_GPINS_SHIFT		25
+#define BONITO_ICU_MBOX(N)		(1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
+#define BONITO_ICU_GPIO(N)		(1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
+#define BONITO_ICU_GPIN(N)		(1<<(BONITO_ICU_GPINS_SHIFT+(N)))
+
+/* pcimap */
+
+#define BONITO_PCIMAP_PCIMAP_LO0	0x0000003f
+#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT	0
+#define BONITO_PCIMAP_PCIMAP_LO1	0x00000fc0
+#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT	6
+#define BONITO_PCIMAP_PCIMAP_LO2	0x0003f000
+#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT	12
+#define BONITO_PCIMAP_PCIMAP_2		0x00040000
+#define BONITO_PCIMAP_WIN(WIN,ADDR)	((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#define BONITO_PCIMAP_WINSIZE           (1<<26)
+#define BONITO_PCIMAP_WINOFFSET(ADDR)	((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
+#define BONITO_PCIMAP_WINBASE(ADDR)	((ADDR) << 26)
+
+/* pcimembaseCfg */
+
+#define BONITO_PCIMEMBASECFG_MASK               0xf0000000
+#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK	0x0000001f
+#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT	0
+#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS	0x000003e0
+#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT	5
+#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED	0x00000400
+#define BONITO_PCIMEMBASECFG_MEMBASE0_IO	0x00000800
+
+#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK	0x0001f000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT	12
+#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS	0x003e0000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT	17
+#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED	0x00400000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_IO	0x00800000
+
+#define BONITO_PCIMEMBASECFG_ASHIFT	23
+#define BONITO_PCIMEMBASECFG_AMASK              0x007fffff
+#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE)	(((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
+#define BONITO_PCIMEMBASECFGBASE(WIN,BASE)	(((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
+
+#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG)  (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
+
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+
+#define BONITO_PCITOPHYS(WIN,ADDR,CFG)          ( \
+                                                  (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \
+                                                  (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \
+                                                )
+
+/* PCICmd */
+
+#define BONITO_PCICMD_MEMEN		0x00000002
+#define BONITO_PCICMD_MSTREN		0x00000004
+
+#define BONITO_IRQ_BASE   32
+
+#endif /* !_BONITO_H */
diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h
new file mode 100644
index 0000000..9506af4
--- /dev/null
+++ b/include/asm-mips/mach-lemote/dma-coherence.h
@@ -0,0 +1,43 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ */
+#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
+#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
+
+struct device;
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+					  size_t size)
+{
+	return virt_to_phys(addr) | 0x80000000;
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+					       struct page *page)
+{
+	return page_to_phys(page) | 0x80000000;
+}
+
+static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+	return dma_addr & 0x7fffffff;
+}
+
+static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+{
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+	return 0;
+}
+
+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h
new file mode 100644
index 0000000..7850f89
--- /dev/null
+++ b/include/asm-mips/mach-lemote/mc146818rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_GENERIC_MC146818RTC_H
+#define __ASM_MACH_GENERIC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#define RTC_PORT(x)	(0x70 + (x))
+#define RTC_IRQ		8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+	outb_p(addr, RTC_PORT(0));
+	return inb_p(RTC_PORT(1));
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+	outb_p(addr, RTC_PORT(0));
+	outb_p(data, RTC_PORT(1));
+}
+
+#define RTC_ALWAYS_BCD	0
+
+#ifndef mc146818_decode_year
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */
-- 
1.4.4.1

[PATCH 2/16] arch related Makefile update for lemote fulong mini-PC

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>


Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/Makefile        |    8 ++++++++
 arch/mips/kernel/Makefile |    1 +
 arch/mips/lib-32/Makefile |    1 +
 arch/mips/lib-64/Makefile |    1 +
 arch/mips/mm/Makefile     |    1 +
 arch/mips/pci/Makefile    |    1 +
 6 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 92bca6a..2a6742d 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
 cflags-$(CONFIG_CPU_VR41XX)	+= -march=r4100 -Wa,--trap
 cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R1)	+= $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
 			-Wa,-mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2)	+= $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -298,6 +299,13 @@ cflags-$(CONFIG_WR_PPMC)		+= -Iinclude/asm-mips/mach-wrppmc
 load-$(CONFIG_WR_PPMC)		+= 0xffffffff80100000
 
 #
+# lemote fulong mini-PC board
+#
+core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/
+load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000
+cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote
+
+#
 # For all MIPS, Inc. eval boards
 #
 core-$(CONFIG_MIPS_BOARDS_GEN)	+= arch/mips/mips-boards/generic/
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 4924626..40fdf79 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_R10000)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_SB1)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_MIPS32)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_MIPS64)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_LOONGSON2)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R6000)		+= r6000_fpu.o r4k_switch.o
 
 obj-$(CONFIG_SMP)		+= smp.o
diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile
index 8b94d4c..b4be604 100644
--- a/arch/mips/lib-32/Makefile
+++ b/arch/mips/lib-32/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_CPU_SB1)		+= dump_tlb.o
 obj-$(CONFIG_CPU_TX39XX)	+= r3k_dump_tlb.o
 obj-$(CONFIG_CPU_TX49XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_VR41XX)	+= dump_tlb.o
+obj-$(CONFIG_CPU_LOONGSON2)	+= dump_tlb.o
diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile
index 8b94d4c..b4be604 100644
--- a/arch/mips/lib-64/Makefile
+++ b/arch/mips/lib-64/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_CPU_SB1)		+= dump_tlb.o
 obj-$(CONFIG_CPU_TX39XX)	+= r3k_dump_tlb.o
 obj-$(CONFIG_CPU_TX49XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_VR41XX)	+= dump_tlb.o
+obj-$(CONFIG_CPU_LOONGSON2)	+= dump_tlb.o
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 293697b..ab24195 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_CPU_R5432)		+= c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
 obj-$(CONFIG_CPU_R8000)		+= c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o
 obj-$(CONFIG_CPU_RM7000)	+= c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
 obj-$(CONFIG_CPU_RM9000)	+= c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
+obj-$(CONFIG_CPU_LOONGSON2)	+= c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
 obj-$(CONFIG_CPU_SB1)		+= c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \
 				   tlb-r4k.o
 obj-$(CONFIG_CPU_TX39XX)	+= c-tx39.o pg-r4k.o tlb-r3k.o
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bf85995..3a77235 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938)	+= fixup-tx4938.o ops-tx4938.o
 obj-$(CONFIG_VICTOR_MPC30X)	+= fixup-mpc30x.o
 obj-$(CONFIG_ZAO_CAPCELLA)	+= fixup-capcella.o
 obj-$(CONFIG_WR_PPMC)		+= fixup-wrppmc.o
+obj-$(CONFIG_LEMOTE_FULONG)	+= fixup-lm2e.o ops-lm2e.o
-- 
1.4.4.1

[PATCH 3/16] Kconfig update for lemote fulong mini-PC

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>


Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/Kconfig |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 338bfa3..c18a835 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -16,6 +16,27 @@ choice
 	prompt "System type"
 	default SGI_IP22
 
+config LEMOTE_FULONG
+	bool "Support for Lemote's fulong mini-PC"
+	select SYS_HAS_CPU_LOONGSON2
+	select DMA_NONCOHERENT
+	select BOOT_ELF32
+	select BOARD_SCACHE
+	select HW_HAS_PCI
+	select I8259
+	select ISA
+	select IRQ_CPU
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_HAS_EARLY_PRINTK
+	select GENERIC_HARDIRQS_NO__DO_IRQ
+	select CPU_HAS_WB
+	help
+        Lemote Fulong mini-PC board, which uses Chinese Loongson-2E CPU and a fpga north bridge
+
+
 config MIPS_MTX1
 	bool "4G Systems MTX-1 board"
 	select DMA_NONCOHERENT
@@ -1142,6 +1163,13 @@ choice
 	prompt "CPU type"
 	default CPU_R4X00
 
+config CPU_LOONGSON2
+	bool "LOONGSON2"
+	depends on SYS_HAS_CPU_LOONGSON2
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select CPU_SUPPORTS_64BIT_KERNEL
+	select CPU_SUPPORTS_HIGHMEM
+
 config CPU_MIPS32_R1
 	bool "MIPS32 Release 1"
 	depends on SYS_HAS_CPU_MIPS32_R1
@@ -1352,6 +1380,9 @@ config CPU_SB1
 
 endchoice
 
+config SYS_HAS_CPU_LOONGSON2
+	bool
+
 config SYS_HAS_CPU_MIPS32_R1
 	bool
 
@@ -1681,6 +1712,13 @@ config CPU_HAS_SMARTMIPS
 config CPU_HAS_WB
 	bool
 
+config 64BIT_CONTEXT
+	bool "Save 64bit integer registers" if CPU_LOONGSON2 && 32BIT
+	help
+	  Loongson2 CPU is 64bit , when used in 32BIT mode, its integer registers
+	  can still be accessed as 64bit, mainly for multimedia instructions. We must have
+	  all 64bit save/restored to make sure those instructions to get correct result.
+
 #
 # Vectored interrupt mode is an R2 feature
 #
-- 
1.4.4.1

[PATCH 4/16] TO_PHYS_MASK for loongson2

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 include/asm-mips/addrspace.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 964c5ed..a4d9a07 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -145,7 +145,7 @@
 #define TO_PHYS_MASK	_CONST64_(0x000000ffffffffff)	/* 2^^40 - 1 */
 #endif
 
-#if defined (CONFIG_CPU_R10000)
+#if defined (CONFIG_CPU_R10000) || defined (CONFIG_CPU_LOONGSON2)
 #define TO_PHYS_MASK	_CONST64_(0x000000ffffffffff)	/* 2^^40 - 1 */
 #endif
 
-- 
1.4.4.1

[PATCH 5/16] add MACH_GROUP_LEMOTE & MACH_LEMOTE_FULONG

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 include/asm-mips/bootinfo.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index c7c945b..f4607f1 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -213,6 +213,12 @@
 #define MACH_GROUP_NEC_EMMA2RH 25	/* NEC EMMA2RH (was 23)		*/
 #define  MACH_NEC_MARKEINS	0	/* NEC EMMA2RH Mark-eins	*/
 
+/*
+ * Valid machtype for group LEMOTE
+ */
+#define MACH_GROUP_LEMOTE          27
+#define  MACH_LEMOTE_FULONG        0
+
 #define CL_SIZE			COMMAND_LINE_SIZE
 
 const char *get_system_type(void);
-- 
1.4.4.1

[PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 include/asm-mips/cacheops.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index c4a1ec3..df7f2de 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -20,7 +20,11 @@
 #define Index_Load_Tag_D	0x05
 #define Index_Store_Tag_I	0x08
 #define Index_Store_Tag_D	0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I    	0x00
+#else
 #define Hit_Invalidate_I	0x10
+#endif
 #define Hit_Invalidate_D	0x11
 #define Hit_Writeback_Inv_D	0x15
 
-- 
1.4.4.1

[PATCH 7/16] add Loongson processor definitions

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 include/asm-mips/cpu.h |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index d38fdbf..d289359 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -89,6 +89,8 @@
 #define PRID_IMP_34K		0x9500
 #define PRID_IMP_24KE		0x9600
 #define PRID_IMP_74K		0x9700
+#define PRID_IMP_LOONGSON1      0x4200
+#define PRID_IMP_LOONGSON2      0x6300
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -200,7 +202,10 @@
 #define CPU_SB1A		62
 #define CPU_74K			63
 #define CPU_R14000		64
-#define CPU_LAST		64
+#define CPU_LOONGSON1           65
+#define CPU_LOONGSON2           66
+
+#define CPU_LAST		66
 
 /*
  * ISA Level encodings
-- 
1.4.4.1

[PATCH 8/16] define MODULE_PROC_FAMILY for Loongson2

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 include/asm-mips/module.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index 399d03f..f615324 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "RM9000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
+#elif defined CONFIG_CPU_LOONGSON2
+#define MODULE_PROC_FAMILY "LOONGSON2 "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
-- 
1.4.4.1

[PATCH 9/16] add serial port definition for lemote fulong

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>


Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 include/asm-mips/serial.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index d7a6513..0f78438 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -204,6 +204,12 @@
 #define IP32_SERIAL_PORT_DEFNS
 #endif /* CONFIG_SGI_IP32 */
 
+#if defined(CONFIG_LEMOTE_FULONG)
+#define LEMOTE_FULONG_SERIAL_PORT_DEFNS			\
+	/* UART CLK   PORT IRQ     FLAGS        */	\
+	{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },	/* ttyS0 */
+#endif
+
 #define SERIAL_PORT_DFNS				\
 	DDB5477_SERIAL_PORT_DEFNS			\
 	EV64120_SERIAL_PORT_DEFNS			\
@@ -213,6 +219,7 @@
 	MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS		\
 	MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS		\
 	MOMENCO_OCELOT_SERIAL_PORT_DEFNS		\
-	MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
+	MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS		\
+	LEMOTE_FULONG_SERIAL_PORT_DEFNS
 
 #endif /* _ASM_SERIAL_H */
-- 
1.4.4.1

[PATCH 10/16] make cpu_probe recognize Loongson2

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/kernel/cpu-probe.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ab755ea..c9e3637 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -464,6 +464,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 		             MIPS_CPU_LLSC;
 		c->tlbsize = 64;
 		break;
+	case PRID_IMP_LOONGSON2:
+		c->cputype = CPU_LOONGSON2;
+		c->isa_level = MIPS_CPU_ISA_III;
+		c->options = R4K_OPTS |
+			     MIPS_CPU_FPU | MIPS_CPU_LLSC |
+			     MIPS_CPU_32FPR;
+		c->tlbsize = 64;
+		break;
 	}
 }
 
-- 
1.4.4.1

[PATCH 11/16] add Loongson support to /proc/cpuinfo

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/kernel/proc.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 5ddc2e9..e915117 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -84,6 +84,7 @@ static const char *cpu_name[] = {
 	[CPU_VR4181A]	= "NEC VR4181A",
 	[CPU_SR71000]	= "Sandcraft SR71000",
 	[CPU_PR4450]	= "Philips PR4450",
+	[CPU_LOONGSON2]	= "ICT Loongson-2",
 };
 
 
-- 
1.4.4.1

[PATCH 12/16] cheat for support of more than 256MB memory

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/kernel/setup.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 4975da0..62ef100 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -509,6 +509,14 @@ static void __init resource_init(void)
 		res->end = end;
 
 		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
+#if defined(CONFIG_LEMOTE_FULONG) && defined(CONFIG_64BIT)
+		/* to keep memory continous, we tell system 0x10000000 - 0x20000000 is reserved
+		 * for memory, in fact it is io region, don't occupy it
+		 *
+		 * SPARSEMEM?
+		 */
+		if (boot_mem_map.map[i].type != BOOT_MEM_RESERVED)
+#endif
 		request_resource(&iomem_resource, res);
 
 		/*
-- 
1.4.4.1

[PATCH 13/16] define MODULE_PROC_FAMILY for Loongson2

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/mm/c-r4k.c |   57 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index df04a31..6e6eac6 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -335,6 +335,10 @@ static void r4k_flush_cache_all(void)
 
 static inline void local_r4k___flush_cache_all(void * args)
 {
+#if defined(CONFIG_CPU_LOONGSON2)
+	r4k_blast_scache();
+	return;
+#endif
 	r4k_blast_dcache();
 	r4k_blast_icache();
 
@@ -848,6 +852,26 @@ static void __init probe_pcache(void)
 		c->options |= MIPS_CPU_PREFETCH;
 		break;
 
+	case CPU_LOONGSON2:
+		icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
+		c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
+		if (prid & 0x3) {
+		  c->icache.ways = 4;
+		} else {
+		  c->icache.ways = 2;
+		}
+		c->icache.waybit= 0;
+
+		dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
+		c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
+		if (prid & 0x3) {
+		  c->dcache.ways = 4;
+		} else {
+		  c->dcache.ways = 2;
+		}
+		c->dcache.waybit = 0;
+		break;
+
 	default:
 		if (!(config & MIPS_CONF_M))
 			panic("Don't know how to probe P-caches on this cpu.");
@@ -963,6 +987,14 @@ static void __init probe_pcache(void)
 		break;
 	}
 
+#ifdef  CONFIG_CPU_LOONGSON2
+	/* 
+	 * LOONGSON2 has 4 way icache, but when using indexed cache op, 
+	 * one op will act on all 4 ways
+	 */
+	c->icache.ways = 1;
+#endif
+
 	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
 	       icache_size >> 10,
 	       cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
@@ -1036,6 +1068,25 @@ static int __init probe_scache(void)
 	return 1;
 }
 
+#if defined(CONFIG_CPU_LOONGSON2)
+static void __init loongson2_sc_init(void)
+{
+    struct cpuinfo_mips *c = &current_cpu_data;
+
+    scache_size = 512*1024;
+    c->scache.linesz = 32;
+    c->scache.ways = 4;
+    c->scache.waybit = 0;
+    c->scache.waysize = scache_size / (c->scache.ways);
+    c->scache.sets = scache_size /(c->scache.linesz * c->scache.ways);
+    printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
+		    scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
+
+    c->options |= MIPS_CPU_INCLUSIVE_CACHES;
+    return;
+}
+#endif
+
 extern int r5k_sc_init(void);
 extern int rm7k_sc_init(void);
 extern int mips_sc_init(void);
@@ -1085,6 +1136,12 @@ static void __init setup_scache(void)
 #endif
 		return;
 
+#if defined(CONFIG_CPU_LOONGSON2)
+	case CPU_LOONGSON2:
+		loongson2_sc_init();
+		return;
+#endif
+
 	default:
 		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 		    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-- 
1.4.4.1

[PATCH 14/16] tlb handling support for Loongson2 processor

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/mm/tlb-r4k.c |   23 ++++++++++++++++++++++-
 arch/mips/mm/tlbex.c   |    8 +++++---
 2 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 65160d4..26284bd 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -48,6 +48,22 @@ extern void build_tlb_refill_handler(void);
 
 #endif /* CONFIG_MIPS_MT_SMTC */
 
+#if defined(CONFIG_CPU_LOONGSON2)
+/* 
+ * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, 
+ * unfortrunately, itlb is not totally transparent to software.
+ */
+#define FLUSH_ITLB write_c0_diag(4);
+
+#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC)  write_c0_diag(4); }
+
+#else
+
+#define FLUSH_ITLB
+#define FLUSH_ITLB_VM(vma)
+
+#endif
+
 void local_flush_tlb_all(void)
 {
 	unsigned long flags;
@@ -73,6 +89,7 @@ void local_flush_tlb_all(void)
 	}
 	tlbw_use_hazard();
 	write_c0_entryhi(old_ctx);
+	FLUSH_ITLB;
 	EXIT_CRITICAL(flags);
 }
 
@@ -136,6 +153,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 		} else {
 			drop_mmu_context(mm, cpu);
 		}
+		FLUSH_ITLB;
 		EXIT_CRITICAL(flags);
 	}
 }
@@ -178,6 +196,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
 	} else {
 		local_flush_tlb_all();
 	}
+	FLUSH_ITLB;
 	EXIT_CRITICAL(flags);
 }
 
@@ -210,6 +229,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 
 	finish:
 		write_c0_entryhi(oldpid);
+		FLUSH_ITLB_VM(vma);
 		EXIT_CRITICAL(flags);
 	}
 }
@@ -241,7 +261,7 @@ void local_flush_tlb_one(unsigned long page)
 		tlbw_use_hazard();
 	}
 	write_c0_entryhi(oldpid);
-
+	FLUSH_ITLB;
 	EXIT_CRITICAL(flags);
 }
 
@@ -293,6 +313,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 	else
 		tlb_write_indexed();
 	tlbw_use_hazard();
+	FLUSH_ITLB_VM(vma);
 	EXIT_CRITICAL(flags);
 }
 
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 492c518..e1a58d9 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -893,6 +893,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
 	case CPU_4KSC:
 	case CPU_20KC:
 	case CPU_25KF:
+	case CPU_LOONGSON2:
 		tlbw(p);
 		break;
 
@@ -1276,7 +1277,8 @@ static void __init build_r4000_tlb_refill_handler(void)
 	 * need three, with the second nop'ed and the third being
 	 * unused.
 	 */
-#ifdef CONFIG_32BIT
+	/* Loongson2 ebase is different than r4k, we have more space */
+#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
 	if ((p - tlb_handler) > 64)
 		panic("TLB refill handler space exceeded");
 #else
@@ -1289,7 +1291,7 @@ static void __init build_r4000_tlb_refill_handler(void)
 	/*
 	 * Now fold the handler in the TLB refill handler space.
 	 */
-#ifdef CONFIG_32BIT
+#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
 	f = final_handler;
 	/* Simplest case, just copy the handler. */
 	copy_handler(relocs, labels, tlb_handler, p, f);
@@ -1336,7 +1338,7 @@ static void __init build_r4000_tlb_refill_handler(void)
 		final_len);
 
 	f = final_handler;
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2)
 	if (final_len > 32)
 		final_len = 64;
 	else
-- 
1.4.4.1

[PATCH 15/16] work around for more than 256MB memory support

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 drivers/char/mem.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/char/mem.c b/drivers/char/mem.c
index f5c160c..580ad3e 100644
--- a/drivers/char/mem.c
+++ b/drivers/char/mem.c
@@ -83,8 +83,12 @@ static inline int uncached_access(struct file *file, unsigned long addr)
 	 */
 	if (file->f_flags & O_SYNC)
 		return 1;
+#if defined(CONFIG_LEMOTE_FULONG) && defined(CONFIG_64BIT)
+	return (addr >= __pa(high_memory)) || ((addr >=0x10000000) && (addr < 0x20000000));
+#else
 	return addr >= __pa(high_memory);
 #endif
+#endif
 }
 
 #ifndef ARCH_HAS_VALID_PHYS_ADDR_RANGE
-- 
1.4.4.1

[PATCH 16/16] alsa sound support for mips

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>

Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 sound/core/pcm_native.c |   10 ++++++++++
 sound/core/sgbuf.c      |    9 +++++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 3e276fc..9005bac 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -3145,7 +3145,11 @@ static struct page *snd_pcm_mmap_data_nopage(struct vm_area_struct *area,
 			return NOPAGE_OOM; /* XXX: is this really due to OOM? */
 	} else {
 		vaddr = runtime->dma_area + offset;
+#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
+		page = virt_to_page(CAC_ADDR(vaddr));
+#else
 		page = virt_to_page(vaddr);
+#endif
 	}
 	get_page(page);
 	if (type)
@@ -3261,6 +3265,12 @@ static int snd_pcm_mmap(struct file *file, struct vm_area_struct *area)
 	substream = pcm_file->substream;
 	snd_assert(substream != NULL, return -ENXIO);
 
+#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
+	/* all mmap using uncached mode */
+	area->vm_page_prot = pgprot_noncached(area->vm_page_prot);
+	area->vm_flags |= ( VM_RESERVED | VM_IO);
+#endif
+
 	offset = area->vm_pgoff << PAGE_SHIFT;
 	switch (offset) {
 	case SNDRV_PCM_MMAP_OFFSET_STATUS:
diff --git a/sound/core/sgbuf.c b/sound/core/sgbuf.c
index cefd228..535f0bc 100644
--- a/sound/core/sgbuf.c
+++ b/sound/core/sgbuf.c
@@ -91,12 +91,21 @@ void *snd_malloc_sgbuf_pages(struct device *device,
 		}
 		sgbuf->table[i].buf = tmpb.area;
 		sgbuf->table[i].addr = tmpb.addr;
+#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
+		sgbuf->page_table[i] = virt_to_page(CAC_ADDR(tmpb.area));
+#else
 		sgbuf->page_table[i] = virt_to_page(tmpb.area);
+#endif
 		sgbuf->pages++;
 	}
 
 	sgbuf->size = size;
+#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
+	/* maybe we should use uncached accelerated mode */
+	dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL));
+#else
 	dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL);
+#endif
 	if (! dmab->area)
 		goto _failed;
 	return dmab->area;
-- 
1.4.4.1

Re: [PATCH 16/16] alsa sound support for mips

[Ralf Baechle]

On Sun, Apr 15, 2007 at 11:26:05PM +0800, tiansm@lemote.com wrote:

(Adding a few more people to the cc'list)

>  sound/core/pcm_native.c |   10 ++++++++++
>  sound/core/sgbuf.c      |    9 +++++++++
>  2 files changed, 19 insertions(+), 0 deletions(-)
> 
> diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
> index 3e276fc..9005bac 100644
> --- a/sound/core/pcm_native.c
> +++ b/sound/core/pcm_native.c
> @@ -3145,7 +3145,11 @@ static struct page *snd_pcm_mmap_data_nopage(struct vm_area_struct *area,
>  			return NOPAGE_OOM; /* XXX: is this really due to OOM? */
>  	} else {
>  		vaddr = runtime->dma_area + offset;
> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)

Please use CONFIG_MIPS instead of __mips__ in #if / #ifdefs.

The question if #ifdefing is the right approach to solve this problem is
something else but I think no, ....

> +		page = virt_to_page(CAC_ADDR(vaddr));
> +#else
>  		page = virt_to_page(vaddr);
> +#endif

So this is needed because the MIPS virt_to_page is returning a unsuitable
value if vaddress is not a KSEG0 (64-bit: cached XKPHYS) address which is
what GFP allocations and the slab will return.  So now we have to deciede
if

 a) the MIPS __pa() should be changed to handle uncached addresses.
 b) the sound code here is simply broken.

Some drivers seem to allocate runtime->dma_area from vmalloc, so this
whole area in the sound code is looking like built on quicksand ...

>  	}
>  	get_page(page);
>  	if (type)
> @@ -3261,6 +3265,12 @@ static int snd_pcm_mmap(struct file *file, struct vm_area_struct *area)
>  	substream = pcm_file->substream;
>  	snd_assert(substream != NULL, return -ENXIO);
>  
> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
> +	/* all mmap using uncached mode */
> +	area->vm_page_prot = pgprot_noncached(area->vm_page_prot);
> +	area->vm_flags |= ( VM_RESERVED | VM_IO);

VM_RESERVED will prevent the buffer from being freed.  I assume that is
another workaround for some kernel subsystem blowing up when being fed a
pointer to an uncached RAM address?  This smells like a memory leak.

> +#endif
> +
>  	offset = area->vm_pgoff << PAGE_SHIFT;
>  	switch (offset) {
>  	case SNDRV_PCM_MMAP_OFFSET_STATUS:
> diff --git a/sound/core/sgbuf.c b/sound/core/sgbuf.c
> index cefd228..535f0bc 100644
> --- a/sound/core/sgbuf.c
> +++ b/sound/core/sgbuf.c
> @@ -91,12 +91,21 @@ void *snd_malloc_sgbuf_pages(struct device *device,
>  		}
>  		sgbuf->table[i].buf = tmpb.area;
>  		sgbuf->table[i].addr = tmpb.addr;
> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
> +		sgbuf->page_table[i] = virt_to_page(CAC_ADDR(tmpb.area));

VM_RESERVED will prevent the buffer from being freed.  I assume that is
another workaround for some kernel subsystem blowing up when being fed a
pointer to an uncached RAM address?  This smells like a memory leak.

> +#else
>  		sgbuf->page_table[i] = virt_to_page(tmpb.area);
> +#endif
>  		sgbuf->pages++;
>  	}
>  
>  	sgbuf->size = size;
> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
> +	/* maybe we should use uncached accelerated mode */
> +	dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL));
> +#else
>  	dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL);
> +#endif

I would suggest to get rid of this ifdef with a new arch-specific function
like vmap_io_buffer which will do whatever a platform seems fit for this
case?

>  	if (! dmab->area)
>  		goto _failed;
>  	return dmab->area;

  Ralf

Re: [PATCH 16/16] alsa sound support for mips

[Fuxin Zhang]

>>  		vaddr = runtime->dma_area + offset;
>> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
>>     
>
> Please use CONFIG_MIPS instead of __mips__ in #if / #ifdefs.
>
> The question if #ifdefing is the right approach to solve this problem is
> something else but I think no, ....
>   
I would agree that it is quite ugly, but changing virt_to_page for it 
does not seem right either.
>   
>> +		page = virt_to_page(CAC_ADDR(vaddr));
>> +#else
>>  		page = virt_to_page(vaddr);
>> +#endif
>>     
>
> So this is needed because the MIPS virt_to_page is returning a unsuitable
> value if vaddress is not a KSEG0 (64-bit: cached XKPHYS) address which is
> what GFP allocations and the slab will return.  So now we have to deciede
> if
>
>  a) the MIPS __pa() should be changed to handle uncached addresses.
>  b) the sound code here is simply broken.
>
> Some drivers seem to allocate runtime->dma_area from vmalloc, so this
> whole area in the sound code is looking like built on quicksand ...
>   
>> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
>> +	/* all mmap using uncached mode */
>> +	area->vm_page_prot = pgprot_noncached(area->vm_page_prot);
>> +	area->vm_flags |= ( VM_RESERVED | VM_IO);
>>     
>
> VM_RESERVED will prevent the buffer from being freed.  I assume that is
> another workaround for some kernel subsystem blowing up when being fed a
> pointer to an uncached RAM address?  This smells like a memory leak.
>
>   
Oh, VM_RESERVED should be a memory leak problem, we can remove it.
I don't remember any case of other subsystem's problem, just did not 
think much
to add those flags.
>> +#endif
>> +
>>  	offset = area->vm_pgoff << PAGE_SHIFT;
>>  	switch (offset) {
>>  	case SNDRV_PCM_MMAP_OFFSET_STATUS:
>> diff --git a/sound/core/sgbuf.c b/sound/core/sgbuf.c
>> index cefd228..535f0bc 100644
>> --- a/sound/core/sgbuf.c
>> +++ b/sound/core/sgbuf.c
>> @@ -91,12 +91,21 @@ void *snd_malloc_sgbuf_pages(struct device *device,
>>  		}
>>  		sgbuf->table[i].buf = tmpb.area;
>>  		sgbuf->table[i].addr = tmpb.addr;
>> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
>> +		sgbuf->page_table[i] = virt_to_page(CAC_ADDR(tmpb.area));
>>     
>
> VM_RESERVED will prevent the buffer from being freed.  I assume that is
> another workaround for some kernel subsystem blowing up when being fed a
> pointer to an uncached RAM address?  This smells like a memory leak.
>
>   
>> +#else
>>  		sgbuf->page_table[i] = virt_to_page(tmpb.area);
>> +#endif
>>  		sgbuf->pages++;
>>  	}
>>  
>>  	sgbuf->size = size;
>> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
>> +	/* maybe we should use uncached accelerated mode */
>> +	dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL));
>> +#else
>>  	dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL);
>> +#endif
>>     
>
> I would suggest to get rid of this ifdef with a new arch-specific function
> like vmap_io_buffer which will do whatever a platform seems fit for this
> case?
>   
I think arch-specific function is the correct way, but don't know what 
the alsa gods think.
>   
>>  	if (! dmab->area)
>>  		goto _failed;
>>  	return dmab->area;
>>     
>
>   Ralf
>
>
>
>
>   

Re: [PATCH 16/16] alsa sound support for mips

[Atsushi Nemoto]

On Wed, 18 Apr 2007 22:13:02 +0800, Fuxin Zhang <fxzhang@ict.ac.cn> wrote:
> >> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT)
> >> +	/* all mmap using uncached mode */
> >> +	area->vm_page_prot = pgprot_noncached(area->vm_page_prot);
> >> +	area->vm_flags |= ( VM_RESERVED | VM_IO);
> >>     
> >
> > VM_RESERVED will prevent the buffer from being freed.  I assume that is
> > another workaround for some kernel subsystem blowing up when being fed a
> > pointer to an uncached RAM address?  This smells like a memory leak.
> >
> >   
> Oh, VM_RESERVED should be a memory leak problem, we can remove it.
> I don't remember any case of other subsystem's problem, just did not 
> think much
> to add those flags.

I think pgprot_noncached() is needed because user mapping for a DMA
buffer (runtime->dma_area) should be uncache.  If so, doing this in
snd_pcm_mmap() looks a bit suspicious.  It seems snd_pcm_mmap_data()
is a place to do such an adjustment.  But for now, both
snd_pcm_mmap_status() and snd_pcm_mmap_control() returns -ENXIO for
MIPS so this is not a real problem.

And I wonder if VM_IO is really needed.  The area is a DMA buffer,
_not_ a memory mapped IO area, isn't it?

> > I would suggest to get rid of this ifdef with a new arch-specific function
> > like vmap_io_buffer which will do whatever a platform seems fit for this
> > case?
> >   
> I think arch-specific function is the correct way, but don't know what 
> the alsa gods think.

JFYI, there were some discussions on this topic a while ago:

http://lkml.org/lkml/2006/1/25/117

and I'v seen MIPS version of dma_mmap_coherent(), etc. somewhere...

---
Atsushi Nemoto

Re: [PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2

[Ralf Baechle]

On Sun, Apr 15, 2007 at 11:25:55PM +0800, tiansm@lemote.com wrote:

> +#if defined(CONFIG_CPU_LOONGSON2)
> +#define Hit_Invalidate_I    	0x00

This #ifdef means Index_Invalidate_I and Hit_Invalidate_I will both be
defined as zero, is that really correct?

(This is the point where I would really like to have a CPU manual ...)

> +#else
>  #define Hit_Invalidate_I	0x10
> +#endif

  Ralf

Re: [PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2

[Fuxin Zhang]

Yes, Loongson2 has no Hit_invalidate_I in fact. And although it has 
4-way icache, one Index_invalidate_I will invalidate all 4 ways of the 
same set.

The usermanual and datasheet can be downloaded from:

http://www.lemote.com/upfiles/godson2e-user-manual-V0.6.pdf


Ralf Baechle wrote:
> On Sun, Apr 15, 2007 at 11:25:55PM +0800, tiansm@lemote.com wrote:
>
>   
>> +#if defined(CONFIG_CPU_LOONGSON2)
>> +#define Hit_Invalidate_I    	0x00
>>     
>
> This #ifdef means Index_Invalidate_I and Hit_Invalidate_I will both be
> defined as zero, is that really correct?
>
> (This is the point where I would really like to have a CPU manual ...)
>
>   
>> +#else
>>  #define Hit_Invalidate_I	0x10
>> +#endif
>>     
>
>   Ralf
>
>
>
>
>   

Re: [PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2

[Fuxin Zhang]

Sorry, no english version of datasheet yet.

Fuxin Zhang wrote:
> Yes, Loongson2 has no Hit_invalidate_I in fact. And although it has 
> 4-way icache, one Index_invalidate_I will invalidate all 4 ways of the 
> same set.
>
> The usermanual and datasheet can be downloaded from:
>
> http://www.lemote.com/upfiles/godson2e-user-manual-V0.6.pdf
>
>
> Ralf Baechle wrote:
>> On Sun, Apr 15, 2007 at 11:25:55PM +0800, tiansm@lemote.com wrote:
>>
>>  
>>> +#if defined(CONFIG_CPU_LOONGSON2)
>>> +#define Hit_Invalidate_I        0x00
>>>     
>>
>> This #ifdef means Index_Invalidate_I and Hit_Invalidate_I will both be
>> defined as zero, is that really correct?
>>
>> (This is the point where I would really like to have a CPU manual ...)
>>
>>  
>>> +#else
>>>  #define Hit_Invalidate_I    0x10
>>> +#endif
>>>     
>>
>>   Ralf
>>
>>
>>
>>
>>   
>
>
>
>

Re: [PATCH 4/16] TO_PHYS_MASK for loongson2

[Ralf Baechle]

On Sun, Apr 15, 2007 at 11:25:53PM +0800, tiansm@lemote.com wrote:

> diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
> index 964c5ed..a4d9a07 100644
> --- a/include/asm-mips/addrspace.h
> +++ b/include/asm-mips/addrspace.h
> @@ -145,7 +145,7 @@
>  #define TO_PHYS_MASK	_CONST64_(0x000000ffffffffff)	/* 2^^40 - 1 */
>  #endif
>  
> -#if defined (CONFIG_CPU_R10000)
> +#if defined (CONFIG_CPU_R10000) || defined (CONFIG_CPU_LOONGSON2)
>  #define TO_PHYS_MASK	_CONST64_(0x000000ffffffffff)	/* 2^^40 - 1 */
>  #endif

How about we define TO_PHYS_MASK to 2^57-1 for all processors instead?

The use of TO_PHYS_MASK is to strip of the high bits of of a XKPHYS kernel
virtual address.  Allowing for the top 2 region and 3 cache mode bits that
would leave 59 bits.  If we also allow for the macro to be used for
stripping off the 2 R10000 "uncached attribute" bits we would be down to
57 bits.  Not sure if that would be useful - but we got gobs of address
space to burn and adding yet another #ifdef for every new 64-bit processor
or even variant to addrspace.h isn't really the way to go.

  Ralf

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Ralf Baechle]

On Sun, Apr 15, 2007 at 11:25:52PM +0800, tiansm@lemote.com wrote:

> @@ -1681,6 +1712,13 @@ config CPU_HAS_SMARTMIPS
>  config CPU_HAS_WB
>  	bool
>  
> +config 64BIT_CONTEXT
> +	bool "Save 64bit integer registers" if CPU_LOONGSON2 && 32BIT
> +	help
> +	  Loongson2 CPU is 64bit , when used in 32BIT mode, its integer registers
> +	  can still be accessed as 64bit, mainly for multimedia instructions. We must have
> +	  all 64bit save/restored to make sure those instructions to get correct result.
> +

Is there anything in implementation of this option Loongson2-specific?
If not then I suggest we make this option loook like:

   bool "Save 64bit integer registers" if CPU_SUPPORTS_64BIT_KERNEL && 32BIT

Somebody else might have a use for it!

  Ralf

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Fuxin Zhang]

>> +
>>     
>
> Is there anything in implementation of this option Loongson2-specific?
>   
Yes. Most 64bit MIPS processors cannot access 64bit content of registers 
when it is in 32bit mode.

Loongson2 has no 32/64 mode bit in fact.

And the usage arise from Loongson2's multimedia extension, which is also 
uniq.
> If not then I suggest we make this option loook like:
>
>    bool "Save 64bit integer registers" if CPU_SUPPORTS_64BIT_KERNEL && 32BIT
>
> Somebody else might have a use for it!
>
>   Ralf
>
>
>
>
>   

RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Uhler, Mike]

> Yes. Most 64bit MIPS processors cannot access 64bit content 
> of registers when it is in 32bit mode.

For clarity, there is no 32/64-bit mode in MIPS processors.  There is a
mode in which 64-bit OPERATIONS are enabled (that is, those instructions
which operate on the full width of the registers) - See the definition
of 64-bit Operations Enable in the MIPS64 Architecture for Programmers,
volume III.  Note that such operations are always enabled while the
processor is running in Kernel Mode.

The patch is a little short on context, but if you've got a 64-bit
kernel, I had always assumed that save/restore of context is always done
with LD/SD, not by figuring out whether a process has 64-bit operations
enabled, then doing a conditional LD/SD or LW/SW.

/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler AT mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043
   

> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org 
> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Fuxin Zhang
> Sent: Wednesday, April 18, 2007 6:32 AM
> To: Ralf Baechle
> Cc: tiansm@lemote.com; linux-mips@linux-mips.org; Fuxin Zhang
> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
> 
> 
> >> +
> >>     
> >
> > Is there anything in implementation of this option 
> Loongson2-specific?
> >   
> Yes. Most 64bit MIPS processors cannot access 64bit content 
> of registers when it is in 32bit mode.
> 
> Loongson2 has no 32/64 mode bit in fact.
> 
> And the usage arise from Loongson2's multimedia extension, 
> which is also uniq.
> > If not then I suggest we make this option loook like:
> >
> >    bool "Save 64bit integer registers" if 
> CPU_SUPPORTS_64BIT_KERNEL && 
> > 32BIT
> >
> > Somebody else might have a use for it!
> >
> >   Ralf
> >
> >
> >
> >
> >   
> 
> 

RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Uhler, Mike]

> Yes. Most 64bit MIPS processors cannot access 64bit content 
> of registers when it is in 32bit mode.

For clarity, there is no 32/64-bit mode in MIPS processors.  There is a
mode in which 64-bit OPERATIONS are enabled (that is, those instructions
which operate on the full width of the registers) - See the definition
of 64-bit Operations Enable in the MIPS64 Architecture for Programmers,
volume III.  Note that such operations are always enabled while the
processor is running in Kernel Mode.

The patch is a little short on context, but if you've got a 64-bit
kernel, I had always assumed that save/restore of context is always done
with LD/SD, not by figuring out whether a process has 64-bit operations
enabled, then doing a conditional LD/SD or LW/SW.

/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler AT mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043
   

> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org 
> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Fuxin Zhang
> Sent: Wednesday, April 18, 2007 6:32 AM
> To: Ralf Baechle
> Cc: tiansm@lemote.com; linux-mips@linux-mips.org; Fuxin Zhang
> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
> 
> 
> >> +
> >>     
> >
> > Is there anything in implementation of this option 
> Loongson2-specific?
> >   
> Yes. Most 64bit MIPS processors cannot access 64bit content 
> of registers when it is in 32bit mode.
> 
> Loongson2 has no 32/64 mode bit in fact.
> 
> And the usage arise from Loongson2's multimedia extension, 
> which is also uniq.
> > If not then I suggest we make this option loook like:
> >
> >    bool "Save 64bit integer registers" if 
> CPU_SUPPORTS_64BIT_KERNEL && 
> > 32BIT
> >
> > Somebody else might have a use for it!
> >
> >   Ralf
> >
> >
> >
> >
> >   
> 
> 

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Fuxin Zhang]

Uhler, Mike wrote:
>> Yes. Most 64bit MIPS processors cannot access 64bit content 
>> of registers when it is in 32bit mode.
>>     
>
> For clarity, there is no 32/64-bit mode in MIPS processors.  There is a
> mode in which 64-bit OPERATIONS are enabled (that is, those instructions
> which operate on the full width of the registers) - See the definition
> of 64-bit Operations Enable in the MIPS64 Architecture for Programmers,
> volume III.  Note that such operations are always enabled while the
> processor is running in Kernel Mode.
>
> The patch is a little short on context, but if you've got a 64-bit
> kernel, I had always assumed that save/restore of context is always done
> with LD/SD, not by figuring out whether a process has 64-bit operations
> enabled, then doing a conditional LD/SD or LW/SW.
>
>   
This patch for 32bit kernel. We want to save/restore 64bit register 
content because the high 32bit of register might be used by multimedia 
programs for loongson processor, such as mplayer.

> /gmu
> ---
> Michael Uhler, Chief Technology Officer
> MIPS Technologies, Inc.   Email: uhler AT mips.com
> 1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
> Mountain View, CA 94043
>    
>
>   
>> -----Original Message-----
>> From: linux-mips-bounce@linux-mips.org 
>> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Fuxin Zhang
>> Sent: Wednesday, April 18, 2007 6:32 AM
>> To: Ralf Baechle
>> Cc: tiansm@lemote.com; linux-mips@linux-mips.org; Fuxin Zhang
>> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
>>
>>
>>     
>>>> +
>>>>     
>>>>         
>>> Is there anything in implementation of this option 
>>>       
>> Loongson2-specific?
>>     
>>>   
>>>       
>> Yes. Most 64bit MIPS processors cannot access 64bit content 
>> of registers when it is in 32bit mode.
>>
>> Loongson2 has no 32/64 mode bit in fact.
>>
>> And the usage arise from Loongson2's multimedia extension, 
>> which is also uniq.
>>     
>>> If not then I suggest we make this option loook like:
>>>
>>>    bool "Save 64bit integer registers" if 
>>>       
>> CPU_SUPPORTS_64BIT_KERNEL && 
>>     
>>> 32BIT
>>>
>>> Somebody else might have a use for it!
>>>
>>>   Ralf
>>>
>>>
>>>
>>>
>>>   
>>>       
>>     
>
>
>
>
>   

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Ralf Baechle]

On Wed, Apr 18, 2007 at 08:28:16AM -0700, Uhler, Mike wrote:

> > Yes. Most 64bit MIPS processors cannot access 64bit content 
> > of registers when it is in 32bit mode.
> 
> For clarity, there is no 32/64-bit mode in MIPS processors.  There is a
> mode in which 64-bit OPERATIONS are enabled (that is, those instructions
> which operate on the full width of the registers) - See the definition
> of 64-bit Operations Enable in the MIPS64 Architecture for Programmers,
> volume III.  Note that such operations are always enabled while the
> processor is running in Kernel Mode.
> 
> The patch is a little short on context, but if you've got a 64-bit
> kernel, I had always assumed that save/restore of context is always done
> with LD/SD, not by figuring out whether a process has 64-bit operations
> enabled, then doing a conditional LD/SD or LW/SW.

Here's a funny one where we have something like a mode.  This is a
reposting from Bill Earl:

[...]
     One other issue is that UX should always be set, to allow use of
MIPS3 instructions, and that XX (bit 31) should be set on R5000 and
R10000 processors, to enable MIPS4 instructions.  This in turn means
that, to avoid various illegal address exceptions, the VM system
should not allow a 32-bit user program to map anything into the top 32
KB of the user address space.

     The problem has to do with some compilers using integer
arithmetic to compute a base for some variables in the current stack
frame, and then using negative displacements to address the variables,
for cases where the stack frame exceeds 32 KB, but is located near the
top of memory.  The 32-bit unsigned integer add to, say, 0x7fffff00
(64-bit address 0x000000007fffff00) produces a signed 32-bit value
such as 0x80000f00, which is the 64-bit value 0xffffffff80000f00,
since all 32-bit values, signed or unsigned, are stored as 32-bit
signed values sign-extended to 64 bits.  When you do a load with a
negative offset of, say, -0x1000, you get an address
0xffffffff7fffff00, not 0x000000007fffff00.  With UX=0, this would be
fine, but, with UX=1 (to enable MIPS3 instructions), the above address
is illegal.  If the $sp is always at least 32 KB below the top of the
address space, this problem does not arise, since any such intermediate
pointer generated by the compiler will always be below 0x80000000.
[...]

The original posting is at http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=14452.59571.970106.514001%40liveoak.engr.sgi.com

  Ralf

RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Uhler, Mike]

Note that both of these apply to pre-MIPS64 processors.  In a MIPS64
implementation, The Status.PX bit should be used to enable 64-bit
operations without enabling 64-bit addressing.  The Status.XX bit is
gone and can't be set.  The addressing boundary condition that Bill
mentioned is explicitly address in the Architecture for Programmer's
manual, Volume III, section 4.10 as a requirement for hardware in
exactly this case.

I realize that Loongson is a MIPS III processor where Bill's suggestion
may apply, but it's not a general problem moving forward to MIPS64.

/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler AT mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043
   

> -----Original Message-----
> From: Ralf Baechle [mailto:ralf@linux-mips.org] 
> Sent: Wednesday, April 18, 2007 9:38 AM
> To: Uhler, Mike
> Cc: Fuxin Zhang; tiansm@lemote.com; 
> linux-mips@linux-mips.org; Fuxin Zhang
> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
> 
> On Wed, Apr 18, 2007 at 08:28:16AM -0700, Uhler, Mike wrote:
> 
> > > Yes. Most 64bit MIPS processors cannot access 64bit content of 
> > > registers when it is in 32bit mode.
> > 
> > For clarity, there is no 32/64-bit mode in MIPS processors. 
>  There is 
> > a mode in which 64-bit OPERATIONS are enabled (that is, those 
> > instructions which operate on the full width of the 
> registers) - See 
> > the definition of 64-bit Operations Enable in the MIPS64 
> Architecture 
> > for Programmers, volume III.  Note that such operations are always 
> > enabled while the processor is running in Kernel Mode.
> > 
> > The patch is a little short on context, but if you've got a 64-bit 
> > kernel, I had always assumed that save/restore of context is always 
> > done with LD/SD, not by figuring out whether a process has 64-bit 
> > operations enabled, then doing a conditional LD/SD or LW/SW.
> 
> Here's a funny one where we have something like a mode.  This 
> is a reposting from Bill Earl:
> 
> [...]
>      One other issue is that UX should always be set, to allow use of
> MIPS3 instructions, and that XX (bit 31) should be set on 
> R5000 and R10000 processors, to enable MIPS4 instructions.  
> This in turn means that, to avoid various illegal address 
> exceptions, the VM system should not allow a 32-bit user 
> program to map anything into the top 32 KB of the user address space.
> 
>      The problem has to do with some compilers using integer 
> arithmetic to compute a base for some variables in the 
> current stack frame, and then using negative displacements to 
> address the variables, for cases where the stack frame 
> exceeds 32 KB, but is located near the top of memory.  The 
> 32-bit unsigned integer add to, say, 0x7fffff00 (64-bit 
> address 0x000000007fffff00) produces a signed 32-bit value 
> such as 0x80000f00, which is the 64-bit value 
> 0xffffffff80000f00, since all 32-bit values, signed or 
> unsigned, are stored as 32-bit signed values sign-extended to 
> 64 bits.  When you do a load with a negative offset of, say, 
> -0x1000, you get an address 0xffffffff7fffff00, not 
> 0x000000007fffff00.  With UX=0, this would be fine, but, with 
> UX=1 (to enable MIPS3 instructions), the above address is 
> illegal.  If the $sp is always at least 32 KB below the top 
> of the address space, this problem does not arise, since any 
> such intermediate pointer generated by the compiler will 
> always be below 0x80000000.
> [...]
> 
> The original posting is at 
> http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1445
2.59571.970106.514001%40liveoak.engr.sgi.com
> 
>   Ralf
> 

RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Uhler, Mike]

Note that both of these apply to pre-MIPS64 processors.  In a MIPS64
implementation, The Status.PX bit should be used to enable 64-bit
operations without enabling 64-bit addressing.  The Status.XX bit is
gone and can't be set.  The addressing boundary condition that Bill
mentioned is explicitly address in the Architecture for Programmer's
manual, Volume III, section 4.10 as a requirement for hardware in
exactly this case.

I realize that Loongson is a MIPS III processor where Bill's suggestion
may apply, but it's not a general problem moving forward to MIPS64.

/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler AT mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043
   

> -----Original Message-----
> From: Ralf Baechle [mailto:ralf@linux-mips.org] 
> Sent: Wednesday, April 18, 2007 9:38 AM
> To: Uhler, Mike
> Cc: Fuxin Zhang; tiansm@lemote.com; 
> linux-mips@linux-mips.org; Fuxin Zhang
> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
> 
> On Wed, Apr 18, 2007 at 08:28:16AM -0700, Uhler, Mike wrote:
> 
> > > Yes. Most 64bit MIPS processors cannot access 64bit content of 
> > > registers when it is in 32bit mode.
> > 
> > For clarity, there is no 32/64-bit mode in MIPS processors. 
>  There is 
> > a mode in which 64-bit OPERATIONS are enabled (that is, those 
> > instructions which operate on the full width of the 
> registers) - See 
> > the definition of 64-bit Operations Enable in the MIPS64 
> Architecture 
> > for Programmers, volume III.  Note that such operations are always 
> > enabled while the processor is running in Kernel Mode.
> > 
> > The patch is a little short on context, but if you've got a 64-bit 
> > kernel, I had always assumed that save/restore of context is always 
> > done with LD/SD, not by figuring out whether a process has 64-bit 
> > operations enabled, then doing a conditional LD/SD or LW/SW.
> 
> Here's a funny one where we have something like a mode.  This 
> is a reposting from Bill Earl:
> 
> [...]
>      One other issue is that UX should always be set, to allow use of
> MIPS3 instructions, and that XX (bit 31) should be set on 
> R5000 and R10000 processors, to enable MIPS4 instructions.  
> This in turn means that, to avoid various illegal address 
> exceptions, the VM system should not allow a 32-bit user 
> program to map anything into the top 32 KB of the user address space.
> 
>      The problem has to do with some compilers using integer 
> arithmetic to compute a base for some variables in the 
> current stack frame, and then using negative displacements to 
> address the variables, for cases where the stack frame 
> exceeds 32 KB, but is located near the top of memory.  The 
> 32-bit unsigned integer add to, say, 0x7fffff00 (64-bit 
> address 0x000000007fffff00) produces a signed 32-bit value 
> such as 0x80000f00, which is the 64-bit value 
> 0xffffffff80000f00, since all 32-bit values, signed or 
> unsigned, are stored as 32-bit signed values sign-extended to 
> 64 bits.  When you do a load with a negative offset of, say, 
> -0x1000, you get an address 0xffffffff7fffff00, not 
> 0x000000007fffff00.  With UX=0, this would be fine, but, with 
> UX=1 (to enable MIPS3 instructions), the above address is 
> illegal.  If the $sp is always at least 32 KB below the top 
> of the address space, this problem does not arise, since any 
> such intermediate pointer generated by the compiler will 
> always be below 0x80000000.
> [...]
> 
> The original posting is at 
> http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1445
2.59571.970106.514001%40liveoak.engr.sgi.com
> 
>   Ralf
> 

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Ralf Baechle]

On Wed, Apr 18, 2007 at 03:27:16PM -0700, Uhler, Mike wrote:

> Note that both of these apply to pre-MIPS64 processors.  In a MIPS64
> implementation, The Status.PX bit should be used to enable 64-bit
> operations without enabling 64-bit addressing.  The Status.XX bit is
> gone and can't be set.  The addressing boundary condition that Bill
> mentioned is explicitly address in the Architecture for Programmer's
> manual, Volume III, section 4.10 as a requirement for hardware in
> exactly this case.
> 
> I realize that Loongson is a MIPS III processor where Bill's suggestion
> may apply, but it's not a general problem moving forward to MIPS64.

Linux limits the address space to 0x7fff8000 for 32-bit processes.  For
sake of simplicity and symmetry we do this on both 32-bit and 64-bit
kernels, on all processors.  A 64-bit kernel always runs userspace
processes with UX=1.  Since a 32-bit process cannot create mappings
above the low 2GB there isn't an actual need to use PX.

(I think there is a small bug in this scheme though, a process that is
accessing a 64-bit userspace address that isn't a 32-bit address should
be sent a SIGBUS but will actually receive a SIGSEGV.  But that's a
subtility and also requires extrapolating from an API documents that only
covers a strict 32-bit universe.)

  Ralf

Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC

[Thiemo Seufer]

tiansm@lemote.com wrote:
[snip]
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 92bca6a..2a6742d 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
>  cflags-$(CONFIG_CPU_VR41XX)	+= -march=r4100 -Wa,--trap
>  cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap
>  cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
> +cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap

I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible,
so r5000 / r8000 / r10000 would be better choices.


Thiemo

Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC

[Tian]

Thiemo Seufer wrote:
> tiansm@lemote.com wrote:
> [snip]
>   
>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>> index 92bca6a..2a6742d 100644
>> --- a/arch/mips/Makefile
>> +++ b/arch/mips/Makefile
>> @@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
>>  cflags-$(CONFIG_CPU_VR41XX)	+= -march=r4100 -Wa,--trap
>>  cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap
>>  cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
>> +cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap
>>     
>
> I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible,
> so r5000 / r8000 / r10000 would be better choices.
>
>
> Thiemo
>
>   
I check the datasheet I have and i don't see loongson2e has implemented 
mips iv instructions.

Songmao

Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC

[Fuxin Zhang]

>> +cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap
> 
> I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible,
> so r5000 / r8000 / r10000 would be better choices.

Presently Loongson-2E is nearly MIPS III compatible(with some
self-defined extensions), next version will be mips64 release2 compatible.

-march=r4600 is inherited from loongson-1, -march=mips3 might be a
better choice.

> 
> 
> Thiemo
> 
> 
> 
> 

Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC

[Zhang Fuxin]

>> +cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap
> 
> I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible,
> so r5000 / r8000 / r10000 would be better choices.

Presently Loongson-2E is nearly MIPS III compatible(with some
self-defined extensions), next version will be mips64 release2 compatible.

-march=r4600 is inherited from loongson-1, -march=mips3 might be a
better choice.

> 
> 
> Thiemo
> 
> 
> 
> 

Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC

[Thiemo Seufer]

Zhang Fuxin wrote:
> >> +cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap
> > 
> > I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible,
> > so r5000 / r8000 / r10000 would be better choices.
> 
> Presently Loongson-2E is nearly MIPS III compatible(with some
> self-defined extensions), next version will be mips64 release2 compatible.

I see.

> -march=r4600 is inherited from loongson-1, -march=mips3 might be a
> better choice.

Maybe. The 'mips3' maps to -march=r4000, it would assume more memory
latency and a slower integer divider then -march=r4600.


Thiemo

Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC

[Ralf Baechle]

On Mon, Apr 16, 2007 at 01:44:22PM +0100, Thiemo Seufer wrote:

> Zhang Fuxin wrote:
> > >> +cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap
> > > 
> > > I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible,
> > > so r5000 / r8000 / r10000 would be better choices.
> > 
> > Presently Loongson-2E is nearly MIPS III compatible(with some
> > self-defined extensions), next version will be mips64 release2 compatible.
> 
> I see.
> 
> > -march=r4600 is inherited from loongson-1, -march=mips3 might be a
> > better choice.
> 
> Maybe. The 'mips3' maps to -march=r4000, it would assume more memory
> latency and a slower integer divider then -march=r4600.

I don't really have an issue with that since I see it as a temporary
solution until gcc and binutils know about Loongson 2 specifics.  Given
the bit I know about the Loognson 2 processor architecture I would not
expect a significant performance boost from trying different values for
-march with current toolchains.

  Ralf

Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC

[Zhang Fuxin]

Thiemo Seufer 写道:
> Maybe. The 'mips3' maps to -march=r4000, it would assume more memory
> latency and a slower integer divider then -march=r4600.
>   
Just like Ralf has said, -march might not lead to significant
performance difference, but -mtune=
may. Two years ago, I found that adding a machine.def to descripe
pipeline and resources for loongson2
and -mtune=loongson boost many programs by 2-5%。

>
> Thiemo
>
>
>   

[PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2

[zhangfx]

[-- Attachment #1: Type: text/plain, Size: 625 bytes --]


Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 include/asm-mips/cacheops.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index c4a1ec3..df7f2de 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -20,7 +20,11 @@
 #define Index_Load_Tag_D	0x05
 #define Index_Store_Tag_I	0x08
 #define Index_Store_Tag_D	0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I    	0x00
+#else
 #define Hit_Invalidate_I	0x10
+#endif
 #define Hit_Invalidate_D	0x11
 #define Hit_Writeback_Inv_D	0x15
 
-- 
1.4.4.4