[“PATCH” 0/2] [KMB] mmc clock-frequency property update and

[“PATCH” 0/2] [KMB] mmc clock-frequency property update and

[rashmi.a]

From: Rashmi A <rashmi.a@intel.com>

Patch1: If clock-frequency property is set and it is not the same as the
        current clock rate of clk_xin(base clock frequency), set clk_xin
        to use the provided clock rate.

Patch2: Since the EMMC clock in KMB was changed from 200Mhz to 175Mhz in
	FIP,there were some warnings introduced, as the frequency values
        being checked was still wrt 200Mhz in code. Hence, the frequency
        checks are now updated based on the current 175Mhz EMMC clock
        changed in FIP.

Review comments from Adrian Hunter have been incorporated.
Above 2  patches are tested with Keem Bay evaluation module board.

Please help to review this patch set.


Rashmi A (2):
  mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin
  phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP

 drivers/mmc/host/sdhci-of-arasan.c         | 14 ++++++++++++--
 drivers/phy/intel/phy-intel-keembay-emmc.c |  3 ++-
 2 files changed, 14 insertions(+), 3 deletions(-)

-- 
2.17.1

[“PATCH” 1/2] mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin

[rashmi.a]

From: Rashmi A <rashmi.a@intel.com>

If clock-frequency property is set and it is not the same as the current
clock rate of clk_xin(base clock frequency), set clk_xin to use the
provided clock rate.

Signed-off-by: Rashmi A <rashmi.a@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
---
 drivers/mmc/host/sdhci-of-arasan.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 839965f7c717..0e7c07ed9690 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -1542,6 +1542,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
 		}
 	}
 
+	sdhci_get_of_property(pdev);
+
 	sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
 	if (IS_ERR(sdhci_arasan->clk_ahb)) {
 		ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
@@ -1561,14 +1563,22 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
 		goto err_pltfm_free;
 	}
 
+	/* If clock-frequency property is set, use the provided value */
+	if (pltfm_host->clock &&
+	    pltfm_host->clock != clk_get_rate(clk_xin)) {
+		ret = clk_set_rate(clk_xin, pltfm_host->clock);
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to set SD clock rate\n");
+			goto clk_dis_ahb;
+		}
+	}
+
 	ret = clk_prepare_enable(clk_xin);
 	if (ret) {
 		dev_err(dev, "Unable to enable SD clock.\n");
 		goto clk_dis_ahb;
 	}
 
-	sdhci_get_of_property(pdev);
-
 	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
 
-- 
2.17.1

Re: [“PATCH” 1/2] mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin

[Michal Simek]

On 6/3/21 8:22 PM, rashmi.a@intel.com wrote:
> From: Rashmi A <rashmi.a@intel.com>
> 
> If clock-frequency property is set and it is not the same as the current
> clock rate of clk_xin(base clock frequency), set clk_xin to use the
> provided clock rate.
> 
> Signed-off-by: Rashmi A <rashmi.a@intel.com>
> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
>  drivers/mmc/host/sdhci-of-arasan.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 839965f7c717..0e7c07ed9690 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -1542,6 +1542,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>  		}
>  	}
>  
> +	sdhci_get_of_property(pdev);
> +
>  	sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
>  	if (IS_ERR(sdhci_arasan->clk_ahb)) {
>  		ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
> @@ -1561,14 +1563,22 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>  		goto err_pltfm_free;
>  	}
>  
> +	/* If clock-frequency property is set, use the provided value */
> +	if (pltfm_host->clock &&
> +	    pltfm_host->clock != clk_get_rate(clk_xin)) {
> +		ret = clk_set_rate(clk_xin, pltfm_host->clock);
> +		if (ret) {
> +			dev_err(&pdev->dev, "Failed to set SD clock rate\n");
> +			goto clk_dis_ahb;
> +		}
> +	}
> +
>  	ret = clk_prepare_enable(clk_xin);
>  	if (ret) {
>  		dev_err(dev, "Unable to enable SD clock.\n");
>  		goto clk_dis_ahb;
>  	}
>  
> -	sdhci_get_of_property(pdev);
> -
>  	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
>  		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
>  
> 

Manish/Sai: Please retest this on Xilinx SOC.

Thanks,
Michal

Re: [“PATCH” 1/2] mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin

[Ulf Hansson]

On Fri, 4 Jun 2021 at 08:13, Michal Simek <michal.simek@xilinx.com> wrote:
>
>
>
> On 6/3/21 8:22 PM, rashmi.a@intel.com wrote:
> > From: Rashmi A <rashmi.a@intel.com>
> >
> > If clock-frequency property is set and it is not the same as the current
> > clock rate of clk_xin(base clock frequency), set clk_xin to use the
> > provided clock rate.
> >
> > Signed-off-by: Rashmi A <rashmi.a@intel.com>
> > Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
> > ---
> >  drivers/mmc/host/sdhci-of-arasan.c | 14 ++++++++++++--
> >  1 file changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> > index 839965f7c717..0e7c07ed9690 100644
> > --- a/drivers/mmc/host/sdhci-of-arasan.c
> > +++ b/drivers/mmc/host/sdhci-of-arasan.c
> > @@ -1542,6 +1542,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
> >               }
> >       }
> >
> > +     sdhci_get_of_property(pdev);
> > +
> >       sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
> >       if (IS_ERR(sdhci_arasan->clk_ahb)) {
> >               ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
> > @@ -1561,14 +1563,22 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
> >               goto err_pltfm_free;
> >       }
> >
> > +     /* If clock-frequency property is set, use the provided value */
> > +     if (pltfm_host->clock &&
> > +         pltfm_host->clock != clk_get_rate(clk_xin)) {
> > +             ret = clk_set_rate(clk_xin, pltfm_host->clock);
> > +             if (ret) {
> > +                     dev_err(&pdev->dev, "Failed to set SD clock rate\n");
> > +                     goto clk_dis_ahb;
> > +             }
> > +     }
> > +
> >       ret = clk_prepare_enable(clk_xin);
> >       if (ret) {
> >               dev_err(dev, "Unable to enable SD clock.\n");
> >               goto clk_dis_ahb;
> >       }
> >
> > -     sdhci_get_of_property(pdev);
> > -
> >       if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
> >               sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
> >
> >
>
> Manish/Sai: Please retest this on Xilinx SOC.
>
> Thanks,
> Michal

I am about to queue this patch, but it would be nice to get your
confirmation and tested-by tags before doing so. Would that be
possible within the next couple of days?

Kind regards
Uffe

RE: [“PATCH” 1/2] mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin

[Sai Krishna Potthuri]

Hi,

> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@linaro.org>
> Sent: Thursday, June 17, 2021 3:34 PM
> To: Michal Simek <michals@xilinx.com>; Manish Narani
> <MNARANI@xilinx.com>; Sai Krishna Potthuri <lakshmis@xilinx.com>
> Cc: rashmi.a@intel.com; linux-drivers-review-request@eclists.intel.com;
> linux-mmc <linux-mmc@vger.kernel.org>; Linux ARM <linux-arm-
> kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; Kishon <kishon@ti.com>; Vinod Koul
> <vkoul@kernel.org>; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; linux-phy@lists.infradead.org; Mark
> Gross <mgross@linux.intel.com>; kris.pan@linux.intel.com;
> furong.zhou@intel.com; mallikarjunappa.sangannavar@intel.com; Adrian
> Hunter <adrian.hunter@intel.com>; mahesh.r.vaidya@intel.com;
> nandhini.srikandan@intel.com; Raja Subramanian, Lakshmi Bai
> <lakshmi.bai.raja.subramanian@intel.com>
> Subject: Re: [“PATCH” 1/2] mmc: sdhci-of-arasan: Use clock-frequency
> property to update clk_xin
> 
> On Fri, 4 Jun 2021 at 08:13, Michal Simek <michal.simek@xilinx.com> wrote:
> >
> >
> >
> > On 6/3/21 8:22 PM, rashmi.a@intel.com wrote:
> > > From: Rashmi A <rashmi.a@intel.com>
> > >
> > > If clock-frequency property is set and it is not the same as the
> > > current clock rate of clk_xin(base clock frequency), set clk_xin to
> > > use the provided clock rate.
> > >
> > > Signed-off-by: Rashmi A <rashmi.a@intel.com>
> > > Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
> > > ---
> > >  drivers/mmc/host/sdhci-of-arasan.c | 14 ++++++++++++--
> > >  1 file changed, 12 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c
> > > b/drivers/mmc/host/sdhci-of-arasan.c
> > > index 839965f7c717..0e7c07ed9690 100644
> > > --- a/drivers/mmc/host/sdhci-of-arasan.c
> > > +++ b/drivers/mmc/host/sdhci-of-arasan.c
> > > @@ -1542,6 +1542,8 @@ static int sdhci_arasan_probe(struct
> platform_device *pdev)
> > >               }
> > >       }
> > >
> > > +     sdhci_get_of_property(pdev);
> > > +
> > >       sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
> > >       if (IS_ERR(sdhci_arasan->clk_ahb)) {
> > >               ret = dev_err_probe(dev,
> > > PTR_ERR(sdhci_arasan->clk_ahb), @@ -1561,14 +1563,22 @@ static int
> sdhci_arasan_probe(struct platform_device *pdev)
> > >               goto err_pltfm_free;
> > >       }
> > >
> > > +     /* If clock-frequency property is set, use the provided value */
> > > +     if (pltfm_host->clock &&
> > > +         pltfm_host->clock != clk_get_rate(clk_xin)) {
> > > +             ret = clk_set_rate(clk_xin, pltfm_host->clock);
> > > +             if (ret) {
> > > +                     dev_err(&pdev->dev, "Failed to set SD clock rate\n");
> > > +                     goto clk_dis_ahb;
> > > +             }
> > > +     }
> > > +
> > >       ret = clk_prepare_enable(clk_xin);
> > >       if (ret) {
> > >               dev_err(dev, "Unable to enable SD clock.\n");
> > >               goto clk_dis_ahb;
> > >       }
> > >
> > > -     sdhci_get_of_property(pdev);
> > > -
> > >       if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
> > >               sdhci_arasan->quirks |=
> > > SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
> > >
> > >
> >
> > Manish/Sai: Please retest this on Xilinx SOC.
> >
> > Thanks,
> > Michal
> 
> I am about to queue this patch, but it would be nice to get your confirmation
> and tested-by tags before doing so. Would that be possible within the next
> couple of days?
Tested this patch on Xilinx platforms.
Tested-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>

Regards
Sai Krishna

[“PATCH” 2/2] phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP

[rashmi.a]

From: Rashmi A <rashmi.a@intel.com>

Since the EMMC clock was changed from 200Mhz to 175Mhz in FIP,
there were some warnings introduced, as the frequency values
being checked was still wrt 200Mhz in code. Hence, the frequency
checks are now updated based on the current 175Mhz EMMC clock changed
in FIP.

Spamming kernel log msg:
"phy phy-20290000.mmc_phy.2: Unsupported rate: 43750000"

Signed-off-by: Rashmi A <rashmi.a@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
---
 drivers/phy/intel/phy-intel-keembay-emmc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/intel/phy-intel-keembay-emmc.c b/drivers/phy/intel/phy-intel-keembay-emmc.c
index eb7c635ed89a..0eb11ac7c2e2 100644
--- a/drivers/phy/intel/phy-intel-keembay-emmc.c
+++ b/drivers/phy/intel/phy-intel-keembay-emmc.c
@@ -95,7 +95,8 @@ static int keembay_emmc_phy_power(struct phy *phy, bool on_off)
 	else
 		freqsel = 0x0;
 
-	if (mhz < 50 || mhz > 200)
+	/* Check for EMMC clock rate*/
+	if (mhz > 175)
 		dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);
 
 	/*
-- 
2.17.1

Re: [“PATCH” 2/2] phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP

[Ulf Hansson]

On Thu, 3 Jun 2021 at 20:22, <rashmi.a@intel.com> wrote:
>
> From: Rashmi A <rashmi.a@intel.com>
>
> Since the EMMC clock was changed from 200Mhz to 175Mhz in FIP,
> there were some warnings introduced, as the frequency values
> being checked was still wrt 200Mhz in code. Hence, the frequency
> checks are now updated based on the current 175Mhz EMMC clock changed
> in FIP.
>
> Spamming kernel log msg:
> "phy phy-20290000.mmc_phy.2: Unsupported rate: 43750000"
>
> Signed-off-by: Rashmi A <rashmi.a@intel.com>
> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>

I guess $subject patch should be queued together with patch1/2 (via
the mmc tree?), no?

Vinod, Kishion, if that's okay I need an ack from you to pick it up.

Kind regards
Uffe

> ---
>  drivers/phy/intel/phy-intel-keembay-emmc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/intel/phy-intel-keembay-emmc.c b/drivers/phy/intel/phy-intel-keembay-emmc.c
> index eb7c635ed89a..0eb11ac7c2e2 100644
> --- a/drivers/phy/intel/phy-intel-keembay-emmc.c
> +++ b/drivers/phy/intel/phy-intel-keembay-emmc.c
> @@ -95,7 +95,8 @@ static int keembay_emmc_phy_power(struct phy *phy, bool on_off)
>         else
>                 freqsel = 0x0;
>
> -       if (mhz < 50 || mhz > 200)
> +       /* Check for EMMC clock rate*/
> +       if (mhz > 175)
>                 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);
>
>         /*
> --
> 2.17.1
>

Re: [“PATCH” 2/2] phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP

[Vinod Koul]

On 08-06-21, 14:52, Ulf Hansson wrote:
> On Thu, 3 Jun 2021 at 20:22, <rashmi.a@intel.com> wrote:
> >
> > From: Rashmi A <rashmi.a@intel.com>
> >
> > Since the EMMC clock was changed from 200Mhz to 175Mhz in FIP,
> > there were some warnings introduced, as the frequency values
> > being checked was still wrt 200Mhz in code. Hence, the frequency
> > checks are now updated based on the current 175Mhz EMMC clock changed
> > in FIP.
> >
> > Spamming kernel log msg:
> > "phy phy-20290000.mmc_phy.2: Unsupported rate: 43750000"
> >
> > Signed-off-by: Rashmi A <rashmi.a@intel.com>
> > Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
> 
> I guess $subject patch should be queued together with patch1/2 (via
> the mmc tree?), no?
> 
> Vinod, Kishion, if that's okay I need an ack from you to pick it up.

Sure:

Acked-By: Vinod Koul <vkoul@kernel.org>

-- 
~Vinod

Re: [“PATCH” 0/2] [KMB] mmc clock-frequency property update and

[Ulf Hansson]

On Thu, 3 Jun 2021 at 20:22, <rashmi.a@intel.com> wrote:
>
> From: Rashmi A <rashmi.a@intel.com>
>
> Patch1: If clock-frequency property is set and it is not the same as the
>         current clock rate of clk_xin(base clock frequency), set clk_xin
>         to use the provided clock rate.
>
> Patch2: Since the EMMC clock in KMB was changed from 200Mhz to 175Mhz in
>         FIP,there were some warnings introduced, as the frequency values
>         being checked was still wrt 200Mhz in code. Hence, the frequency
>         checks are now updated based on the current 175Mhz EMMC clock
>         changed in FIP.
>
> Review comments from Adrian Hunter have been incorporated.
> Above 2  patches are tested with Keem Bay evaluation module board.
>
> Please help to review this patch set.
>
>
> Rashmi A (2):
>   mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin
>   phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP
>
>  drivers/mmc/host/sdhci-of-arasan.c         | 14 ++++++++++++--
>  drivers/phy/intel/phy-intel-keembay-emmc.c |  3 ++-
>  2 files changed, 14 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>

Applied for fixes, thanks!

Kind regards
Uffe