From: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: ulf.hansson@linaro.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, andersson@kernel.org,
konradybcio@kernel.org, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Abel Vesa <abel.vesa@linaro.org>,
Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Subject: Re: [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle
Date: Mon, 2 Mar 2026 13:15:44 +0530 [thread overview]
Message-ID: <544925d0-cf32-6b2a-548e-d6f7cc517581@oss.qualcomm.com> (raw)
In-Reply-To: <21a87714-cd11-4217-a2aa-82fddc3a8530@kernel.org>
On 2/19/2026 1:57 PM, Krzysztof Kozlowski wrote:
> On 19/02/2026 06:38, Neeraj Soni wrote:
>>>>
>>>> + - if:
>>>> + required:
>>>> + - qcom,ice
>>>> + then:
>>>> + properties:
>>>> + reg-names:
>>>> + not:
>>>> + contains:
>>>> + const: ice
>>>
>>> And reg is still 4? This is not correct syntax. You need to define
>>> proper and final constraints per each device. I would write example, but
>>> why... more things you could just ignore.
>>>
>> I had included changes for reg in v3:
>> https://lore.kernel.org/all/20260206112053.3287756-2-neeraj.soni@oss.qualcomm.com/
>>
>> but those were not reviewed so i assume them to be incorrect and dropped it.
>> Will fix this in next patch and post.
>>
> Patch v3 was also not correct, because SDHCI v5 devices should have 1 or
> 2 entries, not 1-3 as previous patch said.
>
This is not clear to me. Here:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml#n80
it says the entries should be 1-4 and there are no v5 specific constraints.
So i made it 1-3 while adding qcom-ice constraint.
> You need to embed the ifs:
>
> 189 - if:
> 190 properties:
> 191 compatible:
> 192 contains:
> 193 enum:
> 194 - qcom,sdhci-msm-v4
> 195 then:
>
> here you add one more if:
>
Acked. Will add in next patch.
> 196 properties:
> 197 reg:
>
>
> 198 minItems: 2
> 199 items:
> 200 - description: Host controller register map
> 201 - description: SD Core register map
> 202 - description: CQE register map
> 203 - description: Inline Crypto Engine register map
> 204 reg-names:
> 205 minItems: 2
> 206 items:
> 207 - const: hc
> 208 - const: core
> 209 - const: cqhci
> 210 - const: ice
> 211 else:
>
> and here as well.
>
Acked. Will add in next patch.
> 212 properties:
> 213 reg:
> 214 minItems: 1
> 215 items:
> 216 - description: Host controller register map
> 217 - description: CQE register map
> 218 - description: Inline Crypto Engine register map
> 219 reg-names:
> 220 minItems: 1
> 221 items:
> 222 - const: hc
> 223 - const: cqhci
> 224 - const: ice
>
> At least that's the simplest solution I see now.
>
> Best regards,
> Krzysztof
>
Regards,
Neeraj
next prev parent reply other threads:[~2026-03-02 7:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-17 5:25 [PATCH v4 0/3] Enable Inline crypto engine for kodiak and monaco Neeraj Soni
2026-02-17 5:25 ` [PATCH v4 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle Neeraj Soni
2026-02-17 20:16 ` Krzysztof Kozlowski
2026-02-19 5:38 ` Neeraj Soni
2026-02-19 7:20 ` Krzysztof Kozlowski
2026-02-19 8:09 ` Neeraj Soni
2026-02-19 8:27 ` Krzysztof Kozlowski
2026-03-02 7:45 ` Neeraj Soni [this message]
2026-03-02 7:48 ` Krzysztof Kozlowski
2026-03-02 8:57 ` Krzysztof Kozlowski
2026-03-02 11:25 ` Neeraj Soni
2026-03-02 16:38 ` Krzysztof Kozlowski
2026-03-04 7:28 ` Neeraj Soni
2026-02-17 5:25 ` [PATCH v4 2/3] arm64: dts: qcom: kodiak: enable the inline crypto engine for SDHC Neeraj Soni
2026-02-17 5:25 ` [PATCH v4 3/3] arm64: dts: qcom: monaco: " Neeraj Soni
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