[PATCH] mtd: spi-nor: xmc: add support for XM25QH128C and XM25QH256C

[PATCH] mtd: spi-nor: xmc: add support for XM25QH128C and XM25QH256C

[Jakub Czapiga]

Both chips support SFDP (JESD216).
XM25QH128C only supports 3-bit Block-Protection with Top-Bottom
configuration bit.
XM25QH256C supports 4-bit Block-Protection with Top-Bottom configuration
bit on SR(6).

Signed-off-by: Jakub Czapiga <czapiga@google.com>
---
 drivers/mtd/spi-nor/xmc.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/xmc.c b/drivers/mtd/spi-nor/xmc.c
index d5a06054b0dd..963a44c3909a 100644
--- a/drivers/mtd/spi-nor/xmc.c
+++ b/drivers/mtd/spi-nor/xmc.c
@@ -19,7 +19,17 @@ static const struct flash_info xmc_nor_parts[] = {
 		.name = "XM25QH128A",
 		.size = SZ_16M,
 		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
-	},
+	}, {
+		.id = SNOR_ID(0x20, 0x40, 0x18),
+		.name = "XM25QH128C",
+		.size = SZ_16M,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
+	}, {
+		.id = SNOR_ID(0x20, 0x40, 0x19),
+		.name = "XM25QH256C",
+		.size = SZ_32M,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | SPI_NOR_TB_SR_BIT6,
+	}
 };
 
 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
-- 
2.49.0.rc1.451.g8f38331e32-goog


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Re: [PATCH] mtd: spi-nor: xmc: add support for XM25QH128C and XM25QH256C

[Tudor Ambarus]

Hi, Jakub,

Do you have access to these flashes? Can you test them?

We have a minimum testing requirement before updating or adding new
flashes, here it is:
https://docs.kernel.org/driver-api/mtd/spi-nor.html#minimum-testing-requirements

It's true that we don't have yet locking tests described, but
contributions to the documentation is welcomed!

On 17.03.2025 20:21, Jakub Czapiga wrote:
> Both chips support SFDP (JESD216).
> XM25QH128C only supports 3-bit Block-Protection with Top-Bottom
> configuration bit.
> XM25QH256C supports 4-bit Block-Protection with Top-Bottom configuration
> bit on SR(6).
> 
> Signed-off-by: Jakub Czapiga <czapiga@google.com>
> ---
>  drivers/mtd/spi-nor/xmc.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/xmc.c b/drivers/mtd/spi-nor/xmc.c
> index d5a06054b0dd..963a44c3909a 100644
> --- a/drivers/mtd/spi-nor/xmc.c
> +++ b/drivers/mtd/spi-nor/xmc.c
> @@ -19,7 +19,17 @@ static const struct flash_info xmc_nor_parts[] = {
>  		.name = "XM25QH128A",
>  		.size = SZ_16M,
>  		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> -	},
> +	}, {
> +		.id = SNOR_ID(0x20, 0x40, 0x18),
> +		.name = "XM25QH128C",

for the next version, drop the name and add it just as a comment above
the flash entry definition

> +		.size = SZ_16M,

if flash supports SFDP, drop the size parameter, it will trigger SFDP
parsing.

> +		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
> +	}, {
> +		.id = SNOR_ID(0x20, 0x40, 0x19),
> +		.name = "XM25QH256C",
> +		.size = SZ_32M,
> +		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | SPI_NOR_TB_SR_BIT6,

same here. After switching to flash init based on SFDP, please do the
tests mentioned above.

Cheers,
ta

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Re: [PATCH] mtd: spi-nor: xmc: add support for XM25QH128C and XM25QH256C

[Jakub "Kuba" Czapiga]

On Tue, Mar 18, 2025 at 7:27 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
>
> Hi, Jakub,
>
> Do you have access to these flashes? Can you test them?

Hi Tudor,
I've checked our inventory and it seems that all our devices use
either Winbond or Macronix compatibles, so I'm not able to directly
test these chips. Looks like ODMs default to Winbond chips and all
other variants are a viable second source. I got a list of chips from
our factory team so I assumed we have some devices I can actually test
these changes on, but unfortunately that's not the case. However I
could use EM100 to emulate these chips if needed, but I think I'll
have to put these changes on hold until we actually get some devices
with these chips. Datasheets should be good enough of a reason, but
unfortunately in reality chips might function slightly differently
than described in the documentation.

> We have a minimum testing requirement before updating or adding new
> flashes, here it is:
> https://docs.kernel.org/driver-api/mtd/spi-nor.html#minimum-testing-requirements

Thank you, I'll perform necessary tests on all chips I have access to,
including other patches I submitted alongside this one.

> It's true that we don't have yet locking tests described, but
> contributions to the documentation is welcomed!

I'll see what I can do about this. We need locking to work correctly,
so having a good testing scenario will benefit everyone.

> On 17.03.2025 20:21, Jakub Czapiga wrote:
> > Both chips support SFDP (JESD216).
> > XM25QH128C only supports 3-bit Block-Protection with Top-Bottom
> > configuration bit.
> > XM25QH256C supports 4-bit Block-Protection with Top-Bottom configuration
> > bit on SR(6).
> >
> > Signed-off-by: Jakub Czapiga <czapiga@google.com>
> > ---
> >  drivers/mtd/spi-nor/xmc.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi-nor/xmc.c b/drivers/mtd/spi-nor/xmc.c
> > index d5a06054b0dd..963a44c3909a 100644
> > --- a/drivers/mtd/spi-nor/xmc.c
> > +++ b/drivers/mtd/spi-nor/xmc.c
> > @@ -19,7 +19,17 @@ static const struct flash_info xmc_nor_parts[] = {
> >               .name = "XM25QH128A",
> >               .size = SZ_16M,
> >               .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> > -     },
> > +     }, {
> > +             .id = SNOR_ID(0x20, 0x40, 0x18),
> > +             .name = "XM25QH128C",
>
> for the next version, drop the name and add it just as a comment above
> the flash entry definition
>
> > +             .size = SZ_16M,
>
> if flash supports SFDP, drop the size parameter, it will trigger SFDP
> parsing.
>
> > +             .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
> > +     }, {
> > +             .id = SNOR_ID(0x20, 0x40, 0x19),
> > +             .name = "XM25QH256C",
> > +             .size = SZ_32M,
> > +             .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | SPI_NOR_TB_SR_BIT6,
>
> same here. After switching to flash init based on SFDP, please do the
> tests mentioned above.
>
> Cheers,
> ta

Best regards,
Jakub

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