Re: ARCH_DMA_MINALIGN on PA-RISC

[John David Anglin <dave.anglin@bell.net>]

On 2024-07-25 4:36 p.m., Mikulas Patocka wrote:
>
> On Thu, 25 Jul 2024, John David Anglin wrote:
>
>> On 2024-07-25 3:13 p.m., John David Anglin wrote:
>>>> L1_CACHE_BYTES is a performance hint that is used to avoid cache line
>>>> ping-pong when multiple CPUs modify nearby data.
>>> Our L1_CACHE_BYTES define is wrong.  PA7100 has a L1 length of 16 bytes.
>>> PA7200 to PA7300LC have a length of 32 bytes.  PA8000 to PA8700 have a length of 64
>>> bytes.  PA8800 and PA8900 have a L1 length of 128 bytes (this is from ERS D_Stride).
>>>
>> The attached patch fixes the defines for L1_CACHE_SHIFT, L1_CACHE_BYTES and
>> ARCH_DMA_MINALIGN.  I left ARCH_DMA_MINALIGN at 16 as I believe this gives
>> 128-byte alignment.
>>
>> Testing.
>>
>> Dave
>>
>> -- 
>> John David Anglin  dave.anglin@bell.net
> How does ARCH_DMA_MINALIGN == 16 give 128-byte alignment? I think that
> ARCH_DMA_MINALIGN needs to be 128 to avoid the possibility of DMA transfer
> corruption.
You are right.  It should be 128.
>
> L1_CACHE_SHIFT can be set to arbitrary value - setting it badly could
> degrade performance, but it shouldn't cause data corruption.
If we set to an arbitrary value, we need to document why we do it. The naming
suggests that L1_CACHE_BYTES should be the L1 cache length.
>
> The commit d93277b9839b0bde06238a7a7f644114edb2ad4a says that setting
> L1_CACHE_SHIFT == 7 causes networking performance degradation on arm64. I
> don't know how much is this related to parisc.
Some other architectures have L1_CACHE_SHIFT == 7.

Dave

-- 
John David Anglin  dave.anglin@bell.net