Re: ARCH_DMA_MINALIGN on PA-RISC

[John David Anglin <dave.anglin@bell.net>]

On 2024-07-27 6:24 a.m., Mikulas Patocka wrote:
>>> L1_CACHE_SHIFT can be set to arbitrary value - setting it badly could
>>> degrade performance, but it shouldn't cause data corruption.
>> If we set to an arbitrary value, we need to document why we do it. The naming
>> suggests that L1_CACHE_BYTES should be the L1 cache length.
> It's hard to say what should we set it to, if we have different
> microarchitectures with different cache line size. ARM64 sets it to 64,
> despite the fact that there are some ARM64 machines with 128-byte cache
> line.
>
> L1_CACHE_BYTES is a matter of performance. Do you have some benchmarks, so
> that you could try to tune it?
>
> The commit a01fece2e4185ac173abd16d10304d73d47ebf00 says that setting
> L1_CACHE_BYTES == 16 improves performance.
I can't recall what tests were used at the time.  However, L1_CACHE_BYTES == 16 reduces
the kernel size and this probably helps performance.  16 bytes would be the minimum alignment
for ldcw locks.

The comment about the L1 line length being 16 bytes is wrong.  The notes we have from the
PA8800 ERS clearly state that the L1 stride is 128 bytes.  The notes show how to flush the L1
cache.  I think the L1 and L2 lengths have always been the same.

Dave

-- 
John David Anglin  dave.anglin@bell.net