Re: ARCH_DMA_MINALIGN on PA-RISC

[John David Anglin <dave.anglin@bell.net>]

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On 2024-07-25 3:13 p.m., John David Anglin wrote:
>> L1_CACHE_BYTES is a performance hint that is used to avoid cache line
>> ping-pong when multiple CPUs modify nearby data.
> Our L1_CACHE_BYTES define is wrong.  PA7100 has a L1 length of 16 bytes.
> PA7200 to PA7300LC have a length of 32 bytes.  PA8000 to PA8700 have a length of 64
> bytes.  PA8800 and PA8900 have a L1 length of 128 bytes (this is from ERS D_Stride).
>
The attached patch fixes the defines for L1_CACHE_SHIFT, L1_CACHE_BYTES and
ARCH_DMA_MINALIGN.  I left ARCH_DMA_MINALIGN at 16 as I believe this gives
128-byte alignment.

Testing.

Dave

-- 
John David Anglin  dave.anglin@bell.net

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diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 2a60d7a72f1f..e9b0081546c9 100644
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -9,18 +9,21 @@
 #include <asm/alternative.h>
 
 /*
- * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
- * have 32-byte cachelines.  The L1 length appears to be 16 bytes but this
- * is not clearly documented.
+ * PA 2.0 processors have 64 and 128-byte cachelines; PA 1.1 processors
+ * have 32-byte cachelines.
  */
-#define L1_CACHE_BYTES 16
-#define L1_CACHE_SHIFT 4
+#ifdef CONFIG_PA20
+#define L1_CACHE_SHIFT 7
+#else
+#define L1_CACHE_SHIFT 5
+#endif
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
 
 #ifndef __ASSEMBLY__
 
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 
-#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+#define ARCH_DMA_MINALIGN	16
 
 #define __read_mostly __section(".data..read_mostly")