Re: [RFC V2 0/9] hw/pci: hw/cxl: Add UIO support in CXL and PCIe stack.

[Shrihari E S <shrihari.s@samsung.com>]

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On 30/08/26 03:19PM, Junjie Cao wrote:
>Hi Shrihari,
>
>On Wed, 26 Aug 2026 11:04:00 +0530, Shrihari E S wrote:
>> This series is written on top of:
>>
>> Base commit: 3c99db7705c1a885c795b7c14f751c7a3ba29ed8
>> Repository: https://gitlab.com/jic23/qemu
>> Branch: cxl-2026-01-09-draft
>
>Applies clean there and builds; x86_64 cxl-test still passes.  I
>booted the patch-10 example topology and walked the extended
>capability chains and the HDM decoder registers: the v1 SVC/AER
>collision is fixed.  Two things are broken, both on 7/10: the
>switch USP never advertises HDM UIO -- its uio gate reads a flitmode
>field that nothing sets -- so the example topology can't advertise UIO
>end to end, and "-device ioh3420,x-svc=on" aborts QEMU.  Per-patch
>comments on 2, 3 and 5 through 10.
>
>Testing point 3 looks at whether existing configurations still work;
>the compat question is whether they still look the same to a guest.
>2/10 moves x-256b-flit onto pcie-root-port with the default left on,
>so every pcie-root-port on q35 comes up in flit mode with no compat
>entry -- an inbound migration already fails at that patch, I tried
>it -- and 7/10 shifts the CXL DVSEC offsets whether or not x-svc is set.
>
>Worth adding the PCI maintainers on v3 -- eight of the ten patches
>touch files under their entry, and both new capabilities land in
>hw/pci.
>
>I'll re-run the topology once the USP gate is settled.
>
>Many thanks,
>Junjie

Hi Junjie,

Thank you for the detailed review and testing. Your feedback helped
catch several issues that were missing in this patch series
(particularly the derived ports abort scenario). Will address your
comments in the next version of this patch series.

Thanks and regards,
Shrihari


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