[PATCH v3 0/2] PCI: dwc: ep: Multi-function endpoint configuration fixes

[PATCH v3 0/2] PCI: dwc: ep: Multi-function endpoint configuration fixes

[Aksh Garg]

This series addresses multi-function endpoint configuration issues in
the DWC PCIe controller driver. The changes enable proper operations
for physical functions and enhance the multi-function endpoint support.

This patch series can be seen as an extension of the patch series:
https://lore.kernel.org/all/20260130115516.515082-1-a-garg7@ti.com/

Changes from v2 to v3:
- Wrap the patches to fit within 80 columns

Changes from v1 to v2:
- Fixed the minor nits in the patches

v2: https://lore.kernel.org/all/20260219064511.695086-1-a-garg7@ti.com/
v1: https://lore.kernel.org/all/20260202072758.101845-1-a-garg7@ti.com/

Aksh Garg (2):
  PCI: dwc: ep: Fix MSI-X configuration to write to correct physical
    function
  PCI: dwc: ep: Mirror the max link width and speed fields to all
    functions

 .../pci/controller/dwc/pcie-designware-ep.c   | 31 +++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v3 1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function

[Aksh Garg]

The MSI-X configuration code reads from the correct physical function's
register space using dw_pcie_ep_readw_dbi(), but writes back only to
PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
MSI-X configuration for other PFs.

Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
register space, matching the read operation.

Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers")
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Aksh Garg <a-garg7@ti.com>
---

Changes since v1:
- None

v1: https://lore.kernel.org/all/20260202072758.101845-2-a-garg7@ti.com/

 drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7e7844ff0f7e..771241e1a2c9 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 	val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
 	val &= ~PCI_MSIX_FLAGS_QSIZE;
 	val |= nr_irqs - 1; /* encoded as N-1 */
-	dw_pcie_writew_dbi(pci, reg, val);
+	dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
 
 	reg = ep_func->msix_cap + PCI_MSIX_TABLE;
 	val = offset | bir;
-- 
2.34.1

Re: [PATCH v3 1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function

[Bjorn Helgaas]

On Tue, Feb 24, 2026 at 02:08:16PM +0530, Aksh Garg wrote:
> The MSI-X configuration code reads from the correct physical function's
> register space using dw_pcie_ep_readw_dbi(), but writes back only to
> PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
> MSI-X configuration for other PFs.
> 
> Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
> register space, matching the read operation.

Is this another case of using "PF" in a non-SR-IOV context, as I asked
about here?

  https://lore.kernel.org/all/20260223185558.GA3701139@bhelgaas

I do not want to use "PF" unless we're talking about a device with an
SR-IOV Capability and we're doing something specific to SR-IOV.

> Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers")
> Reviewed-by: Niklas Cassel <cassel@kernel.org>
> Signed-off-by: Aksh Garg <a-garg7@ti.com>
> ---
> 
> Changes since v1:
> - None
> 
> v1: https://lore.kernel.org/all/20260202072758.101845-2-a-garg7@ti.com/
> 
>  drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7e7844ff0f7e..771241e1a2c9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>  	val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
>  	val &= ~PCI_MSIX_FLAGS_QSIZE;
>  	val |= nr_irqs - 1; /* encoded as N-1 */
> -	dw_pcie_writew_dbi(pci, reg, val);
> +	dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
>  
>  	reg = ep_func->msix_cap + PCI_MSIX_TABLE;
>  	val = offset | bir;
> -- 
> 2.34.1
> 

Re: [PATCH v3 1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function

[Aksh Garg]

On 07/03/26 00:15, Bjorn Helgaas wrote:
> On Tue, Feb 24, 2026 at 02:08:16PM +0530, Aksh Garg wrote:
>> The MSI-X configuration code reads from the correct physical function's
>> register space using dw_pcie_ep_readw_dbi(), but writes back only to
>> PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
>> MSI-X configuration for other PFs.
>>
>> Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
>> register space, matching the read operation.
> 
> Is this another case of using "PF" in a non-SR-IOV context, as I asked
> about here?
> 
>    https://lore.kernel.org/all/20260223185558.GA3701139@bhelgaas
> 
> I do not want to use "PF" unless we're talking about a device with an
> SR-IOV Capability and we're doing something specific to SR-IOV.

I apologize to commit the same mistake here after your feedback. While
posting this series again, I made changes to patch 2/2, but forgot to
look at the commit message for this patch.

> 
>> Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers")
>> Reviewed-by: Niklas Cassel <cassel@kernel.org>
>> Signed-off-by: Aksh Garg <a-garg7@ti.com>
>> ---
>>
>> Changes since v1:
>> - None
>>
>> v1: https://lore.kernel.org/all/20260202072758.101845-2-a-garg7@ti.com/
>>
>>   drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
>> index 7e7844ff0f7e..771241e1a2c9 100644
>> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
>> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
>> @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>   	val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
>>   	val &= ~PCI_MSIX_FLAGS_QSIZE;
>>   	val |= nr_irqs - 1; /* encoded as N-1 */
>> -	dw_pcie_writew_dbi(pci, reg, val);
>> +	dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
>>   
>>   	reg = ep_func->msix_cap + PCI_MSIX_TABLE;
>>   	val = offset | bir;
>> -- 
>> 2.34.1
>>

Re: [PATCH v3 1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function

[Manivannan Sadhasivam]

On Fri, Mar 06, 2026 at 12:45:19PM -0600, Bjorn Helgaas wrote:
> On Tue, Feb 24, 2026 at 02:08:16PM +0530, Aksh Garg wrote:
> > The MSI-X configuration code reads from the correct physical function's
> > register space using dw_pcie_ep_readw_dbi(), but writes back only to
> > PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
> > MSI-X configuration for other PFs.
> > 
> > Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
> > register space, matching the read operation.
> 
> Is this another case of using "PF" in a non-SR-IOV context, as I asked
> about here?
> 
>   https://lore.kernel.org/all/20260223185558.GA3701139@bhelgaas
> 
> I do not want to use "PF" unless we're talking about a device with an
> SR-IOV Capability and we're doing something specific to SR-IOV.
> 

Fixed the subject and commit log:
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=controller/dwc&id=271d0b1f058ae9815e75233d04b23e3558c3e4f4

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v3 2/2] PCI: dwc: ep: Mirror the max link width and speed fields to all functions

[Aksh Garg]

PCIe r7.0, section 7.5.3.6 states that for multi-function devices, the
Max Link Width and Max Link Speed fields in the Link Capabilities
Register must report the same values for all functions.

Currently, dw_pcie_setup() programs these fields only for Function 0
via dw_pcie_link_set_max_speed() and dw_pcie_link_set_max_link_width().
For multi-function endpoint configurations, Function 1 and beyond retain
their default values, violating the PCIe specification.

Fix this by reading the Max Link Width and Max Link Speed fields from
Link Capabilities Register of Function 0 after dw_pcie_setup() completes,
then mirroring these values to all other functions.

Fixes: 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support for DWC")
Fixes: 89db0793c9f2 ("PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling")
Signed-off-by: Aksh Garg <a-garg7@ti.com>
---

The link speed and width would be negotiated through PF0 during
initialization that controls the link behaviour, hence it didn't broke
the driver. However, the change is proposed just to make the driver
compatible with the PCIe base specifications.

The fix is implemented in pcie-designware-ep.c rather than modifying
dw_pcie_setup() directly to keep pcie-designware.c independent of RC/EP
specifics and maintain it as common code.

Changes from v2 to v3:
- Wrapped the patches to fit within 80 columns
- Updated the term 'physical function' to 'Function'

Changes from v1 to v2:
- Used FIELD_* macros

v2: https://lore.kernel.org/all/20260219064511.695086-3-a-garg7@ti.com/
v1: https://lore.kernel.org/all/20260202072758.101845-3-a-garg7@ti.com/

 .../pci/controller/dwc/pcie-designware-ep.c   | 29 ++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 771241e1a2c9..8041c7a0d381 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -1094,7 +1094,8 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)
 {
 	struct dw_pcie_ep *ep = &pci->ep;
 	u8 funcs = ep->epc->max_functions;
-	u8 func_no;
+	u32 ref_lnkcap, lnkcap;
+	u8 func_no, offset;
 
 	dw_pcie_dbi_ro_wr_en(pci);
 
@@ -1102,6 +1103,32 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)
 		dw_pcie_ep_init_rebar_registers(ep, func_no);
 
 	dw_pcie_setup(pci);
+
+	/*
+	 * PCIe r7.0, section 7.5.3.6 states that for multi-function
+	 * endpoints, max link width and speed fields must report same
+	 * values for all functions. However, dw_pcie_setup() programs
+	 * these fields only for function 0. Hence, mirror these fields
+	 * to all other functions as well.
+	 */
+	if (funcs > 1) {
+		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+		ref_lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
+		ref_lnkcap = FIELD_GET(PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS,
+				       ref_lnkcap);
+
+		for (func_no = 1; func_no < funcs; func_no++) {
+			offset = dw_pcie_ep_find_capability(ep, func_no,
+							    PCI_CAP_ID_EXP);
+			lnkcap = dw_pcie_ep_readl_dbi(ep, func_no,
+						      offset + PCI_EXP_LNKCAP);
+			FIELD_MODIFY(PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS,
+				     &lnkcap, ref_lnkcap);
+			dw_pcie_ep_writel_dbi(ep, func_no,
+					      offset + PCI_EXP_LNKCAP, lnkcap);
+		}
+	}
+
 	dw_pcie_dbi_ro_wr_dis(pci);
 }
 
-- 
2.34.1

Re: [PATCH v3 0/2] PCI: dwc: ep: Multi-function endpoint configuration fixes

[Manivannan Sadhasivam]

On Tue, 24 Feb 2026 14:08:15 +0530, Aksh Garg wrote:
> This series addresses multi-function endpoint configuration issues in
> the DWC PCIe controller driver. The changes enable proper operations
> for physical functions and enhance the multi-function endpoint support.
> 
> This patch series can be seen as an extension of the patch series:
> https://lore.kernel.org/all/20260130115516.515082-1-a-garg7@ti.com/
> 
> [...]

Applied, thanks!

[1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function
      commit: 63ec1248387818f6190569b36d9815699ab5f10e
[2/2] PCI: dwc: ep: Mirror the max link width and speed fields to all functions
      commit: 05d013c151d858cc96baa9aa0d19539237435246

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>