Re: [PATCH v3 6/7] PCI: mediatek-gen3: Add 100 ms delay after link up

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The patch completely bypasses the mandatory 100 ms link training delay when the 'max-link-speed' property is omitted from the Device Tree.
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commit a93442038658e8edd35c1ce148da1ebe3644bfd1
Author: Hans Zhang <18255117159@163.com>

PCI: mediatek-gen3: Add 100 ms delay after link up

The MediaTek Gen3 PCIe host driver lacks the required 100 ms delay after
link training completes for speeds > 5.0 GT/s, as specified in PCIe r6.0
sec 6.6.1. This commit adds the pci_host_common_link_train_delay() call
after the link is successfully brought up.

> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index b0accd8285892..5abddec4e9bec 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
[ ... ]
> @@ -570,6 +571,8 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
>  		goto err_power_down_device;
>  	}
>  
> +	pci_host_common_link_train_delay(pcie->max_link_speed);

Does this code bypass the delay when the max-link-speed property is omitted
from the device tree?

If pcie->max_link_speed is 0 (unspecified in the device tree), the controller
defaults to its native hardware capability (Gen3). However, passing 0 to
pci_host_common_link_train_delay() will cause its internal check to evaluate
to false and skip the delay entirely:

static inline void pci_host_common_link_train_delay(int max_link_speed)
{
	if (max_link_speed > 2)
		msleep(PCIE_RESET_CONFIG_WAIT_MS);
}

Should the driver evaluate the actual controller capability or pass the known
maximum speed when pcie->max_link_speed is 0?

> +
>  	return 0;
>  
>  err_power_down_device:

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Sashiko AI review · https://sashiko.dev/#/patchset/20260511055923.37117-1-18255117159@163.com?part=6