Re: [PATCH v3 7/7] PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The mandatory link training delay is bypassed when 'max-link-speed' is missing from the device tree, violating PCIe r6.0 requirements for Gen3+ devices.
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commit afb29b744bdf8f1be85fd9c879cf2af33e736d5a
Author: Hans Zhang <18255117159@163.com>

PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper

Replace the unconditional msleep(100) with the common helper
pci_host_common_link_train_delay(). The helper only waits when
max_link_speed > 2, as required by PCIe r6.0 sec 6.6.1.

> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index d86e7516dcc29..66f687304c1cb 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c

[ ... ]

> @@ -1663,7 +1664,7 @@ rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host,
>  	if (ret)
>  		dev_info(dev, "Failed to set max link speed\n");
>  
> -	msleep(PCIE_RESET_CONFIG_WAIT_MS);
> +	pci_host_common_link_train_delay(host->max_link_speed);

If the max-link-speed property is missing from the device tree,
of_pci_get_max_link_speed() returns -EINVAL.

While rzg3s_pcie_set_max_link_speed() correctly handles this negative
value by falling back to hardware capabilities, host->max_link_speed
remains -EINVAL.

When this negative value is passed to pci_host_common_link_train_delay(),
the internal check (max_link_speed > 2) evaluates to false.

Could this cause a regression by inadvertently bypassing the mandatory link
training delay for Gen3 or higher devices that lack the max-link-speed
device tree property?

>  
>  	return 0;

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Sashiko AI review · https://sashiko.dev/#/patchset/20260511055923.37117-1-18255117159@163.com?part=7