[PATCH v2] PCI: Allow D3 for native Hotplug capable Root Ports on non-x86 platforms

[PATCH v2] PCI: Allow D3 for native Hotplug capable Root Ports on non-x86 platforms

[Manivannan Sadhasivam]

Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
prevented native Hotplug capable Root Ports from entering D3 citing issues
on old Intel SkyLake Xeon-SP platform.

But there is no reason to restrict D3 for native Hotplug capable Root
Ports on non-x86 platforms. We recently enabled D3 on non-Hotplug capable
Root Ports on non-x86 platforms (specifically for DT platforms) in commit
a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
do the same for native Hotplug capable Root Ports as well.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---

Changes in v2:

* Switched to CONFIG_X86 check instead of of_have_populated_dt() as per comments
  from Lukas.

 drivers/pci/pci.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 77b17b13ee61..94f8a4da6009 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3020,11 +3020,11 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
 			return true;
 
 		/*
-		 * Hotplug ports handled natively by the OS were not validated
-		 * by vendors for runtime D3 at least until 2018 because there
-		 * was no OS support.
+		 * Hotplug ports handled natively by the OS on x86 platforms
+		 * were not validated by vendors for runtime D3 at least until
+		 * 2018 because there was no OS support.
 		 */
-		if (bridge->is_pciehp)
+		if (IS_ENABLED(CONFIG_X86) && bridge->is_pciehp)
 			return false;
 
 		if (dmi_check_system(bridge_d3_blacklist))
-- 
2.43.0

Re: [PATCH v2] PCI: Allow D3 for native Hotplug capable Root Ports on non-x86 platforms

[sashiko-bot]

> Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
> prevented native Hotplug capable Root Ports from entering D3 citing issues
> on old Intel SkyLake Xeon-SP platform.
> 
> But there is no reason to restrict D3 for native Hotplug capable Root
> Ports on non-x86 platforms. We recently enabled D3 on non-Hotplug capable
> Root Ports on non-x86 platforms (specifically for DT platforms) in commit
> a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
> do the same for native Hotplug capable Root Ports as well.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260729165005.896725-1-manivannan.sadhasivam@oss.qualcomm.com?part=1

Re: [PATCH v2] PCI: Allow D3 for native Hotplug capable Root Ports on non-x86 platforms

[Bjorn Helgaas]

On Wed, Jul 29, 2026 at 06:50:05PM +0200, Manivannan Sadhasivam wrote:
> Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
> prevented native Hotplug capable Root Ports from entering D3 citing issues
> on old Intel SkyLake Xeon-SP platform.
> 
> But there is no reason to restrict D3 for native Hotplug capable Root
> Ports on non-x86 platforms. We recently enabled D3 on non-Hotplug capable
> Root Ports on non-x86 platforms (specifically for DT platforms) in commit
> a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
> do the same for native Hotplug capable Root Ports as well.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

Applied to pci/pm for v7.3, thanks!

> ---
> 
> Changes in v2:
> 
> * Switched to CONFIG_X86 check instead of of_have_populated_dt() as per comments
>   from Lukas.
> 
>  drivers/pci/pci.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 77b17b13ee61..94f8a4da6009 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -3020,11 +3020,11 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
>  			return true;
>  
>  		/*
> -		 * Hotplug ports handled natively by the OS were not validated
> -		 * by vendors for runtime D3 at least until 2018 because there
> -		 * was no OS support.
> +		 * Hotplug ports handled natively by the OS on x86 platforms
> +		 * were not validated by vendors for runtime D3 at least until
> +		 * 2018 because there was no OS support.
>  		 */
> -		if (bridge->is_pciehp)
> +		if (IS_ENABLED(CONFIG_X86) && bridge->is_pciehp)
>  			return false;
>  
>  		if (dmi_check_system(bridge_d3_blacklist))
> -- 
> 2.43.0
> 

Re: [PATCH v2] PCI: Allow D3 for native Hotplug capable Root Ports on non-x86 platforms

[Konrad Dybcio]

On 8/12/26 1:22 AM, Bjorn Helgaas wrote:
> On Wed, Jul 29, 2026 at 06:50:05PM +0200, Manivannan Sadhasivam wrote:
>> Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
>> prevented native Hotplug capable Root Ports from entering D3 citing issues
>> on old Intel SkyLake Xeon-SP platform.
>>
>> But there is no reason to restrict D3 for native Hotplug capable Root
>> Ports on non-x86 platforms. We recently enabled D3 on non-Hotplug capable
>> Root Ports on non-x86 platforms (specifically for DT platforms) in commit
>> a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
>> do the same for native Hotplug capable Root Ports as well.
>>
>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> 
> Applied to pci/pm for v7.3, thanks!

This breaks system suspend entry (crashes the system) on Qualcomm SC8280XP
CRD.. this SoC is known for fragile PCIe.

It doesn't repro on e.g. the Qualcomm Glymur CRD (2 gens newer), perhaps we
need an explicit opt-out like

if (of_machine_is_compatible("qcom,sc8280xp"))

or some targetted fix inside the qcom driver

Konrad

Re: [PATCH v2] PCI: Allow D3 for native Hotplug capable Root Ports on non-x86 platforms

[Lukas Wunner]

On Wed, Sep 02, 2026 at 07:09:58PM +0200, Konrad Dybcio wrote:
> > On Wed, Jul 29, 2026 at 06:50:05PM +0200, Manivannan Sadhasivam wrote:
> >> Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
> >> prevented native Hotplug capable Root Ports from entering D3 citing issues
> >> on old Intel SkyLake Xeon-SP platform.
> >>
> >> But there is no reason to restrict D3 for native Hotplug capable Root
> >> Ports on non-x86 platforms. We recently enabled D3 on non-Hotplug capable
> >> Root Ports on non-x86 platforms (specifically for DT platforms) in commit
> >> a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
> >> do the same for native Hotplug capable Root Ports as well.
> 
> This breaks system suspend entry (crashes the system) on Qualcomm SC8280XP
> CRD.. this SoC is known for fragile PCIe.
> 
> It doesn't repro on e.g. the Qualcomm Glymur CRD (2 gens newer), perhaps we
> need an explicit opt-out like
> 
> if (of_machine_is_compatible("qcom,sc8280xp"))
> 
> or some targetted fix inside the qcom driver

That's precisely the reason why x86 uses a BIOS cut-off date of 2015
in pci_bridge_d3_possible():  Root Ports on older SoCs were never
validated for D3hot and are known to cause crashes etc when low
power states are used.

Thanks,

Lukas

Re: [PATCH v2] PCI: Allow D3 for native Hotplug capable Root Ports on non-x86 platforms

[Manivannan Sadhasivam]

On Wed, Sep 02, 2026 at 07:09:58PM +0200, Konrad Dybcio wrote:
> On 8/12/26 1:22 AM, Bjorn Helgaas wrote:
> > On Wed, Jul 29, 2026 at 06:50:05PM +0200, Manivannan Sadhasivam wrote:
> >> Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
> >> prevented native Hotplug capable Root Ports from entering D3 citing issues
> >> on old Intel SkyLake Xeon-SP platform.
> >>
> >> But there is no reason to restrict D3 for native Hotplug capable Root
> >> Ports on non-x86 platforms. We recently enabled D3 on non-Hotplug capable
> >> Root Ports on non-x86 platforms (specifically for DT platforms) in commit
> >> a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
> >> do the same for native Hotplug capable Root Ports as well.
> >>
> >> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > 
> > Applied to pci/pm for v7.3, thanks!
> 
> This breaks system suspend entry (crashes the system) on Qualcomm SC8280XP
> CRD.. this SoC is known for fragile PCIe.
> 

If RP D3 is what breaking the suspend, then the breakage should've been present
between below commits:

a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86")
33a76fc3c3e6 ("PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion support")

First one allowed D3 on all non-x86 platforms and should've broke suspend. Then
second commit enabled Hotplug for RPs, which prevented D3 until *this* patch
landed.

> It doesn't repro on e.g. the Qualcomm Glymur CRD (2 gens newer), perhaps we
> need an explicit opt-out like
> 
> if (of_machine_is_compatible("qcom,sc8280xp"))
> 
> or some targetted fix inside the qcom driver
> 

Will investigate a bit more and come back. Thanks for reporting!

- Mani

-- 
மணிவண்ணன் சதாசிவம்