[PATCH v4 0/2] PCI: cadence: Add LTSSM debugfs

Linux PCI subsystem development
 help / color / mirror / Atom feed

* [PATCH v4 0/2] PCI: cadence: Add LTSSM debugfs
@ 2026-05-08  3:40 Hans Zhang
  2026-05-08  3:41 ` [PATCH v4 1/2] PCI: cadence: Add HPA architecture flag Hans Zhang
  2026-05-08  3:41 ` [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link Hans Zhang
  0 siblings, 2 replies; 19+ messages in thread
From: Hans Zhang @ 2026-05-08  3:40 UTC (permalink / raw)
  To: bhelgaas, lpieralisi, kwilczynski, mani, hans.zhang
  Cc: robh, mpillai, linux-pci, linux-kernel, Hans Zhang

Hi,

This series adds debugfs support to the Cadence PCIe controller driver,
allowing users to read the current LTSSM state of the link for debugging
purposes.

Patch 1 introduces a new flag 'is_hpa' in the cdns_pcie structure to
distinguish HPA (High Performance Architecture IP) platforms, which
have a different register layout for LTSSM status.

Patch 2 implements the debugfs file "ltssm_status" under a per-device
directory. It reads the LTSSM state from the appropriate hardware register
based on the 'is_hpa' flag and displays both a descriptive string and the
raw value.

=====================
Test:
root@orangepi6plus:~# ls -l /sys/kernel/debug/cdns_pcie_a0*
/sys/kernel/debug/cdns_pcie_a010000.pcie:
total 0
-r--r--r-- 1 root root 0 Jan  1  1970 ltssm_status

/sys/kernel/debug/cdns_pcie_a0c0000.pcie:
total 0
-r--r--r-- 1 root root 0 Jan  1  1970 ltssm_status

/sys/kernel/debug/cdns_pcie_a0e0000.pcie:
total 0
-r--r--r-- 1 root root 0 Jan  1  1970 ltssm_status
root@orangepi6plus:~# 
root@orangepi6plus:~# 
root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
L0_STATE (0x29)
L0_STATE (0x29)
L0_STATE (0x29)
root@orangepi6plus:~# 
root@orangepi6plus:~# uname -a
Linux orangepi6plus 7.1.0-rc2-00377-gb898336dec53-dirty #43 SMP PREEMPT Fri May  8 11:15:00 CST 2026 aarch64 aarch64 aarch64 GNU/Linux
=====================

---
Changes for v4:
- Remove the copyright email address of the author of pcie-cadence-debugfs.c (Mani)
- Add cdns_pcie_hpa_host_disable() (Mani)
- Use DEFINE_SHOW_ATTRIBUTE() (Mani & Sashiko)

Changes for v3:
https://patchwork.kernel.org/project/linux-pci/patch/20260406103237.1203127-1-18255117159@163.com/

- Export cdns_pcie_debugfs_deinit (Mani)
- pcie-cadence-ep.c pcie-cadence-host.c pci-sky1.c call cdns_pcie_debugfs_deinit

Changes for v2:
https://patchwork.kernel.org/project/linux-pci/patch/20260321033035.3008585-3-18255117159@163.com/

- s/DW_PCIE_LTSSM_NAME/CDNS_PCIE_LTSSM_NAME/
- S/January 2026/March 2026/
- EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_init); // Resolve the following error issues.
  >> ERROR: modpost: "cdns_pcie_debugfs_init" [drivers/pci/controller/cadence/pcie-cadence-host-mod.ko] undefined!
  >> ERROR: modpost: "cdns_pcie_debugfs_init" [drivers/pci/controller/cadence/pcie-cadence-ep-mod.ko] undefined!

v1:
https://patchwork.kernel.org/project/linux-pci/cover/20260315155514.127255-1-18255117159@163.com/

Hans Zhang (2):
  PCI: cadence: Add HPA architecture flag
  PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe
    link

 Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
 drivers/pci/controller/cadence/Kconfig        |   9 +
 drivers/pci/controller/cadence/Makefile       |   1 +
 drivers/pci/controller/cadence/pci-sky1.c     |   4 +
 .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
 .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
 .../cadence/pcie-cadence-host-hpa.c           |  20 +-
 .../controller/cadence/pcie-cadence-host.c    |   9 +-
 drivers/pci/controller/cadence/pcie-cadence.h | 152 +++++++++++++
 9 files changed, 409 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
 create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c


base-commit: 917719c412c48687d4a176965d1fa35320ec457c
-- 
2.34.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v4 1/2] PCI: cadence: Add HPA architecture flag
  2026-05-08  3:40 [PATCH v4 0/2] PCI: cadence: Add LTSSM debugfs Hans Zhang
@ 2026-05-08  3:41 ` Hans Zhang
  2026-05-08  3:41 ` [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link Hans Zhang
  1 sibling, 0 replies; 19+ messages in thread
From: Hans Zhang @ 2026-05-08  3:41 UTC (permalink / raw)
  To: bhelgaas, lpieralisi, kwilczynski, mani, hans.zhang
  Cc: robh, mpillai, linux-pci, linux-kernel, Hans Zhang

Add a boolean flag 'is_hpa' to the cdns_pcie structure to indicate
that the controller is part of a Heterogeneous Processor Architecture
(HPA) system. This flag will be used by subsequent patches to handle
HPA-specific register layouts and behaviors.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 drivers/pci/controller/cadence/pci-sky1.c     | 1 +
 drivers/pci/controller/cadence/pcie-cadence.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/controller/cadence/pci-sky1.c
index cd55c64e58a9..e1f4a98e2ab6 100644
--- a/drivers/pci/controller/cadence/pci-sky1.c
+++ b/drivers/pci/controller/cadence/pci-sky1.c
@@ -174,6 +174,7 @@ static int sky1_pcie_probe(struct platform_device *pdev)
 	cdns_pcie->reg_base = pcie->reg_base;
 	cdns_pcie->msg_res = pcie->msg_res;
 	cdns_pcie->is_rc = true;
+	cdns_pcie->is_hpa = true;
 
 	reg_off = devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL);
 	if (!reg_off) {
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 574e9cf4d003..9a464cbaf073 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -80,6 +80,7 @@ struct cdns_plat_pcie_of_data {
  * @msg_res: Region for send message to map PCI accesses
  * @dev: PCIe controller
  * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
+ * @is_hpa: indicates if the architecture is HPA
  * @phy_count: number of supported PHY devices
  * @phy: list of pointers to specific PHY control blocks
  * @link: list of pointers to corresponding device link representations
@@ -93,6 +94,7 @@ struct cdns_pcie {
 	struct resource                      *msg_res;
 	struct device		             *dev;
 	bool			             is_rc;
+	bool				     is_hpa;
 	int			             phy_count;
 	struct phy		             **phy;
 	struct device_link	             **link;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-08  3:40 [PATCH v4 0/2] PCI: cadence: Add LTSSM debugfs Hans Zhang
  2026-05-08  3:41 ` [PATCH v4 1/2] PCI: cadence: Add HPA architecture flag Hans Zhang
@ 2026-05-08  3:41 ` Hans Zhang
  2026-05-08  4:19   ` sashiko-bot
  2026-05-13  5:23   ` Aksh Garg
  1 sibling, 2 replies; 19+ messages in thread
From: Hans Zhang @ 2026-05-08  3:41 UTC (permalink / raw)
  To: bhelgaas, lpieralisi, kwilczynski, mani, hans.zhang
  Cc: robh, mpillai, linux-pci, linux-kernel, Hans Zhang

Add the debugfs property to provide a view of the current link's LTSSM
status from the Root Port device.

Test example:
  # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
  L0_STATE (0x29)

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
 drivers/pci/controller/cadence/Kconfig        |   9 +
 drivers/pci/controller/cadence/Makefile       |   1 +
 drivers/pci/controller/cadence/pci-sky1.c     |   3 +
 .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
 .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
 .../cadence/pcie-cadence-host-hpa.c           |  20 +-
 .../controller/cadence/pcie-cadence-host.c    |   9 +-
 drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
 9 files changed, 406 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
 create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c

diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/Documentation/ABI/testing/debugfs-cdns-pcie
new file mode 100644
index 000000000000..659ad2ab70e4
--- /dev/null
+++ b/Documentation/ABI/testing/debugfs-cdns-pcie
@@ -0,0 +1,5 @@
+What:		/sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
+Date:		March 2026
+Contact:	Hans Zhang <18255117159@163.com>
+Description:	(RO) Read will return the current PCIe LTSSM state in both
+		string and raw value.
diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
index 9e651d545973..cb010bc97aad 100644
--- a/drivers/pci/controller/cadence/Kconfig
+++ b/drivers/pci/controller/cadence/Kconfig
@@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
 config PCIE_CADENCE
 	tristate
 
+config PCIE_CADENCE_DEBUGFS
+	tristate "Cadence PCIe debugfs entries"
+	depends on DEBUG_FS
+	depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
+	help
+	  Say Y here to enable debugfs entries for the PCIe controller. These
+	  entries provide various debug features related to the controller and
+	  the LTSSM status of link can be displayed.
+
 config PCIE_CADENCE_HOST
 	tristate
 	depends on OF
diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile
index b8ec1cecfaa8..2cdc4617e0c2 100644
--- a/drivers/pci/controller/cadence/Makefile
+++ b/drivers/pci/controller/cadence/Makefile
@@ -4,6 +4,7 @@ pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-c
 pcie-cadence-ep-mod-y := pcie-cadence-ep.o
 
 obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o
+obj-$(CONFIG_PCIE_CADENCE_DEBUGFS) += pcie-cadence-debugfs.o
 obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o
 obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o
 obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/controller/cadence/pci-sky1.c
index e1f4a98e2ab6..56147ba33c9c 100644
--- a/drivers/pci/controller/cadence/pci-sky1.c
+++ b/drivers/pci/controller/cadence/pci-sky1.c
@@ -221,7 +221,10 @@ MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);
 static void sky1_pcie_remove(struct platform_device *pdev)
 {
 	struct sky1_pcie *pcie = platform_get_drvdata(pdev);
+	struct cdns_pcie_rc *rc;
 
+	rc = container_of(pcie->cdns_pcie, struct cdns_pcie_rc, pcie);
+	cdns_pcie_hpa_host_disable(rc);
 	pci_ecam_free(pcie->cfg);
 }
 
diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
new file mode 100644
index 000000000000..a4f0c4f6f98f
--- /dev/null
+++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence PCIe controller debugfs driver
+ *
+ * Copyright (C) 2026 Hans Zhang <18255117159@163.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include "pcie-cadence.h"
+
+#define CDNS_DEBUGFS_BUF_MAX		128
+#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK	GENMASK(29, 24)
+#define CDNS_PCIE_HPA_LTSSM_STATUS_MASK	GENMASK(27, 20)
+
+static const char *cdns_pcie_ltssm_status_string(enum cdns_pcie_ltssm ltssm)
+{
+	const char *str;
+
+	switch (ltssm) {
+#define CDNS_PCIE_LTSSM_NAME(n) case n: str = #n; break
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_QUIET);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_ACTIVE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_ACTIVE_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_ACTIVE_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_ACTIVE_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RCVR_DETECTED_ST);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RCVR_DETECTED_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_ACTIVE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_ACTIVE_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_ACTIVE_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_ACTIVE_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_CONFIG);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_CONFIG_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_CONFIG_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_RC);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_EP);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DUMMY_STATE_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_COMPLETE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_IDLE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_IDLE_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DUMMY_STATE_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DUMMY_STATE_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DUMMY_STATE_4);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0_STATE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_IDLE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_IDLE_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_4);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_5);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_6);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_7);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_HOT_RESET);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_HOT_RESET_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_HOT_RESET_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_HOT_RESET_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_ENTRY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_4);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_5);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_FTS_ENTRY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_FTS_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_FTS_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_SPEED);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_SPEED_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_SPEED_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_SPEED_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_ENTRY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_4);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_IDLE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_EXIT);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_ENTRY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_4);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_5);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_IDLE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1);
+	CDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2);
+	default:
+		str = "CDNS_PCIE_LTSSM_UNKNOWN";
+		break;
+	}
+
+	return str + strlen("CDNS_PCIE_LTSSM_");
+}
+
+static int ltssm_status_show(struct seq_file *s, void *v)
+{
+	struct cdns_pcie *pci = s->private;
+	enum cdns_pcie_ltssm ltssm;
+	u32 reg;
+
+	if (pci->is_hpa) {
+		reg = cdns_pcie_hpa_readl(pci, REG_BANK_IP_REG,
+					CDNS_PCIE_HPA_PHY_DBG_STS_REG0);
+		ltssm = FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, reg);
+	} else {
+		reg = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
+		ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, reg);
+	}
+
+	seq_printf(s, "%s (0x%02x)\n", cdns_pcie_ltssm_status_string(ltssm), ltssm);
+
+	return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(ltssm_status);
+
+static void cdns_pcie_ltssm_debugfs_init(struct cdns_pcie *pci, struct dentry *dir)
+{
+	debugfs_create_file("ltssm_status", 0444, dir, pci,
+			    &ltssm_status_fops);
+}
+
+void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)
+{
+	if (!pci->debug_dir)
+		return;
+
+	debugfs_remove_recursive(pci->debug_dir);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_deinit);
+
+void cdns_pcie_debugfs_init(struct cdns_pcie *pci)
+{
+	char dirname[CDNS_DEBUGFS_BUF_MAX];
+	struct device *dev = pci->dev;
+
+	/* Create main directory for each platform driver. */
+	snprintf(dirname, CDNS_DEBUGFS_BUF_MAX, "cdns_pcie_%s", dev_name(dev));
+	pci->debug_dir = debugfs_create_dir(dirname, NULL);
+
+	cdns_pcie_ltssm_debugfs_init(pci, pci->debug_dir);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_init);
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index c0e1194a936b..38a0157b60dc 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -659,6 +659,7 @@ void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)
 	pci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr,
 			      SZ_128K);
 	pci_epc_mem_exit(epc);
+	cdns_pcie_debugfs_deinit(&ep->pcie);
 }
 EXPORT_SYMBOL_GPL(cdns_pcie_ep_disable);
 
@@ -761,6 +762,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 
 	pci_epc_init_notify(epc);
 
+	cdns_pcie_debugfs_init(pcie);
+
 	return 0;
 
  free_epc_mem:
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
index 0f540bed58e8..8bf7cc106413 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
@@ -309,6 +309,18 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc)
 }
 EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup);
 
+void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
+{
+	struct pci_host_bridge *bridge;
+
+	bridge = pci_host_bridge_from_priv(rc);
+	pci_stop_root_bus(bridge->bus);
+	pci_remove_root_bus(bridge->bus);
+
+	cdns_pcie_debugfs_deinit(&rc->pcie);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_disable);
+
 int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)
 {
 	struct device *dev = rc->pcie.dev;
@@ -360,7 +372,13 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)
 	if (!bridge->ops)
 		bridge->ops = &cdns_pcie_hpa_host_ops;
 
-	return pci_host_probe(bridge);
+	ret = pci_host_probe(bridge);
+	if (ret)
+		return ret;
+
+	cdns_pcie_debugfs_init(pcie);
+
+	return 0;
 }
 EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup);
 
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 0bc9e6e90e0e..873d496c440f 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -370,6 +370,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
 
 	cdns_pcie_host_deinit(rc);
 	cdns_pcie_host_link_disable(rc);
+	cdns_pcie_debugfs_deinit(&rc->pcie);
 }
 EXPORT_SYMBOL_GPL(cdns_pcie_host_disable);
 
@@ -423,7 +424,13 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	if (!bridge->ops)
 		bridge->ops = &cdns_pcie_host_ops;
 
-	return pci_host_probe(bridge);
+	ret = pci_host_probe(bridge);
+	if (ret)
+		return ret;
+
+	cdns_pcie_debugfs_init(pcie);
+
+	return 0;
 }
 EXPORT_SYMBOL_GPL(cdns_pcie_host_setup);
 
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 9a464cbaf073..a1c531fd2061 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
 	REG_BANKS_MAX,
 };
 
+enum cdns_pcie_ltssm {
+	CDNS_PCIE_LTSSM_DETECT_QUIET		= 0,
+	CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY	= 1,
+	CDNS_PCIE_LTSSM_DETECT_ACTIVE		= 2,
+	CDNS_PCIE_LTSSM_DETECT_ACTIVE_1		= 3,
+	CDNS_PCIE_LTSSM_DETECT_ACTIVE_2		= 4,
+	CDNS_PCIE_LTSSM_DETECT_ACTIVE_3		= 5,
+	CDNS_PCIE_LTSSM_RCVR_DETECTED_ST	= 6,
+	CDNS_PCIE_LTSSM_RCVR_DETECTED_1		= 7,
+	CDNS_PCIE_LTSSM_POLLING_ACTIVE		= 8,
+	CDNS_PCIE_LTSSM_POLLING_ACTIVE_1	= 9,
+	CDNS_PCIE_LTSSM_POLLING_ACTIVE_2	= 10,
+	CDNS_PCIE_LTSSM_POLLING_ACTIVE_3	= 11,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE	= 12,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1	= 13,
+	CDNS_PCIE_LTSSM_POLLING_CONFIG		= 14,
+	CDNS_PCIE_LTSSM_POLLING_CONFIG_1	= 15,
+	CDNS_PCIE_LTSSM_POLLING_CONFIG_2	= 16,
+	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC	= 17,
+	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1	= 18,
+	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2	= 19,
+	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC	= 20,
+	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC	= 21,
+	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
+	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC	= 23,
+	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP	= 24,
+	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1	= 25,
+	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2	= 26,
+	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP	= 27,
+	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP	= 28,
+	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
+	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP	= 30,
+	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1	= 31,
+	CDNS_PCIE_LTSSM_DUMMY_STATE_1		= 32,
+	CDNS_PCIE_LTSSM_CONFIG_COMPLETE		= 33,
+	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1	= 34,
+	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2	= 35,
+	CDNS_PCIE_LTSSM_CONFIG_IDLE		= 36,
+	CDNS_PCIE_LTSSM_CONFIG_IDLE_1		= 37,
+	CDNS_PCIE_LTSSM_DUMMY_STATE_2		= 38,
+	CDNS_PCIE_LTSSM_DUMMY_STATE_3		= 39,
+	CDNS_PCIE_LTSSM_DUMMY_STATE_4		= 40,
+	CDNS_PCIE_LTSSM_L0_STATE		= 41,
+	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK	= 42,
+	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1	= 43,
+	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG	= 44,
+	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1	= 45,
+	CDNS_PCIE_LTSSM_RECOVERY_IDLE		= 46,
+	CDNS_PCIE_LTSSM_RECOVERY_IDLE_1		= 47,
+	CDNS_PCIE_LTSSM_DISABLE_LINK		= 48,
+	CDNS_PCIE_LTSSM_DISABLE_LINK_1		= 49,
+	CDNS_PCIE_LTSSM_DISABLE_LINK_2		= 50,
+	CDNS_PCIE_LTSSM_DISABLE_LINK_3		= 51,
+	CDNS_PCIE_LTSSM_DISABLE_LINK_4		= 52,
+	CDNS_PCIE_LTSSM_DISABLE_LINK_5		= 53,
+	CDNS_PCIE_LTSSM_DISABLE_LINK_6		= 54,
+	CDNS_PCIE_LTSSM_DISABLE_LINK_7		= 55,
+	CDNS_PCIE_LTSSM_HOT_RESET		= 56,
+	CDNS_PCIE_LTSSM_HOT_RESET_1		= 57,
+	CDNS_PCIE_LTSSM_HOT_RESET_2		= 58,
+	CDNS_PCIE_LTSSM_HOT_RESET_3		= 59,
+	CDNS_PCIE_LTSSM_L0S_ENTRY		= 60,
+	CDNS_PCIE_LTSSM_L0S_1			= 61,
+	CDNS_PCIE_LTSSM_L0S_2			= 62,
+	CDNS_PCIE_LTSSM_L0S_3			= 63,
+	CDNS_PCIE_LTSSM_L0S_4			= 64,
+	CDNS_PCIE_LTSSM_L0S_5			= 65,
+	CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX	= 66,
+	CDNS_PCIE_LTSSM_TX_FTS_ENTRY		= 67,
+	CDNS_PCIE_LTSSM_TX_FTS_1		= 68,
+	CDNS_PCIE_LTSSM_TX_FTS_2		= 69,
+	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST		= 70,
+	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1		= 71,
+	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2		= 72,
+	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3		= 73,
+	CDNS_PCIE_LTSSM_RECOVERY_SPEED		= 74,
+	CDNS_PCIE_LTSSM_RECOVERY_SPEED_1	= 75,
+	CDNS_PCIE_LTSSM_RECOVERY_SPEED_2	= 76,
+	CDNS_PCIE_LTSSM_RECOVERY_SPEED_3	= 77,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
+	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY	= 87,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1	= 89,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT	= 90,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1	= 91,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2	= 92,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3	= 93,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4	= 94,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5	= 95,
+	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE	= 96,
+	CDNS_PCIE_LTSSM_L1_ENTRY		= 97,
+	CDNS_PCIE_LTSSM_L1_1			= 98,
+	CDNS_PCIE_LTSSM_L1_2			= 99,
+	CDNS_PCIE_LTSSM_L1_3			= 100,
+	CDNS_PCIE_LTSSM_L1_4			= 101,
+	CDNS_PCIE_LTSSM_L1_IDLE			= 102,
+	CDNS_PCIE_LTSSM_L1_EXIT			= 103,
+	CDNS_PCIE_LTSSM_L2_ENTRY		= 104,
+	CDNS_PCIE_LTSSM_L2_1			= 105,
+	CDNS_PCIE_LTSSM_L2_2			= 106,
+	CDNS_PCIE_LTSSM_L2_3			= 107,
+	CDNS_PCIE_LTSSM_L2_4			= 108,
+	CDNS_PCIE_LTSSM_L2_5			= 109,
+	CDNS_PCIE_LTSSM_L2_IDLE			= 110,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY	= 111,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1	= 112,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2	= 113,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3	= 114,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4	= 115,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5	= 116,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY = 117,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE	= 118,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT	= 119,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1	= 120,
+	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2	= 121,
+	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
+	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
+	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
+	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
+	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
+	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
+};
+
 struct cdns_pcie_ops {
 	int     (*start_link)(struct cdns_pcie *pcie);
 	void    (*stop_link)(struct cdns_pcie *pcie);
@@ -87,6 +218,7 @@ struct cdns_plat_pcie_of_data {
  * @ops: Platform-specific ops to control various inputs from Cadence PCIe
  *       wrapper
  * @cdns_pcie_reg_offsets: Register bank offsets for different SoC
+ * @debug_dir: debugfs node
  */
 struct cdns_pcie {
 	void __iomem		             *reg_base;
@@ -100,6 +232,7 @@ struct cdns_pcie {
 	struct device_link	             **link;
 	const  struct cdns_pcie_ops          *ops;
 	const  struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
+	struct dentry			     *debug_dir;
 };
 
 /**
@@ -447,6 +580,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc);
 void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
 			       int where);
 int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc);
+void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc);
 #else
 static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
 {
@@ -472,6 +606,10 @@ static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
 {
 }
 
+static inline void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
+{
+}
+
 static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
 					     int where)
 {
@@ -535,4 +673,16 @@ bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie);
 
 extern const struct dev_pm_ops cdns_pcie_pm_ops;
 
+#ifdef CONFIG_PCIE_CADENCE_DEBUGFS
+void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci);
+void cdns_pcie_debugfs_init(struct cdns_pcie *pci);
+#else
+static inline void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)
+{
+}
+static inline void cdns_pcie_debugfs_init(struct cdns_pcie *pci)
+{
+}
+#endif
+
 #endif /* _PCIE_CADENCE_H */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-08  3:41 ` [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link Hans Zhang
@ 2026-05-08  4:19   ` sashiko-bot
  2026-05-08  4:31     ` Hans Zhang
  2026-05-13  5:23   ` Aksh Garg
  1 sibling, 1 reply; 19+ messages in thread
From: sashiko-bot @ 2026-05-08  4:19 UTC (permalink / raw)
  To: Hans Zhang; +Cc: linux-pci

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] PCIE_CADENCE_DEBUGFS tristate configuration causes build failure and module linkage issues.
- [High] Race condition in debugfs deinitialization leads to unprotected hardware access.
- [High] Missing Runtime PM reference in debugfs read handler causes system crash.
- [Medium] Missing link teardown in `cdns_pcie_hpa_host_disable`.
- [Medium] Incorrect bitmask `CDNS_PCIE_LGA_LTSSM_STATUS_MASK` truncates LTSSM states.
--

commit b032928b3c42715d7bb97e0bd26a99d252cd98d9
Author: Hans Zhang <18255117159@163.com>

PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link

Add the debugfs property to provide a view of the current link's LTSSM
status from the Root Port device.

> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> index 9e651d5459735..cb010bc97aad3 100644
> --- a/drivers/pci/controller/cadence/Kconfig
> +++ b/drivers/pci/controller/cadence/Kconfig
> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>  config PCIE_CADENCE
>  	tristate
>  
> +config PCIE_CADENCE_DEBUGFS
> +	tristate "Cadence PCIe debugfs entries"

Could this Kconfig option be changed to a bool?

When configured as a module (=m), Kbuild defines
CONFIG_PCIE_CADENCE_DEBUGFS_MODULE, not CONFIG_PCIE_CADENCE_DEBUGFS. As a
result, the preprocessor check in pcie-cadence.h evaluates to false, causing
the header to declare empty static inline stubs. When pcie-cadence-debugfs.c
defines the non-static versions, the build fails with a function redefinition
error.

Furthermore, changing the check to IS_ENABLED(CONFIG_PCIE_CADENCE_DEBUGFS)
would cause linkage errors if the core drivers are built-in while the debugfs
feature is a module, since built-in code cannot call module functions.

[ ... ]

> diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
> new file mode 100644
> index 0000000000000..a4f0c4f6f98f4
> --- /dev/null
> +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
> @@ -0,0 +1,208 @@
[ ... ]
> +#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK	GENMASK(29, 24)

Does this mask need to be extended to cover all possible states?

This mask covers only 6 bits, allowing it to extract values up to 63.
However, the cdns_pcie_ltssm enum defines states up to 127. If the
hardware enters a state 64 or higher, FIELD_GET will silently truncate
the value, making state 65 appear as state 1.

[ ... ]
> +static int ltssm_status_show(struct seq_file *s, void *v)
> +{
> +	struct cdns_pcie *pci = s->private;
> +	enum cdns_pcie_ltssm ltssm;
> +	u32 reg;
> +
> +	if (pci->is_hpa) {
> +		reg = cdns_pcie_hpa_readl(pci, REG_BANK_IP_REG,
> +					CDNS_PCIE_HPA_PHY_DBG_STS_REG0);
> +		ltssm = FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, reg);
> +	} else {
> +		reg = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
> +		ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, reg);
> +	}

Is a runtime PM reference required here before accessing the hardware?

Since the driver supports power management, the controller might be in a
low-power, clock-gated state when this debugfs file is read. Reading the
registers without calling pm_runtime_get_sync() first could cause a bus fault
and crash the system.

[ ... ]

> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index c0e1194a936b3..38a0157b60dc7 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -659,6 +659,7 @@ void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)
>  	pci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr,
>  			      SZ_128K);
>  	pci_epc_mem_exit(epc);
> +	cdns_pcie_debugfs_deinit(&ep->pcie);
>  }

Should cdns_pcie_debugfs_deinit() be called earlier in the teardown process?

If a userspace process is currently reading the debugfs file while the module
is being removed, ltssm_status_show() could attempt to read registers after
the hardware has been deactivated, potentially resulting in a bus fault.
Removing the debugfs entries first ensures no new reads can begin while the
hardware is shut down.

[ ... ]

> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
> index 0f540bed58e88..8bf7cc106413b 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
> @@ -309,6 +309,18 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc)
>  }
>  EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup);
>  
> +void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
> +{
> +	struct pci_host_bridge *bridge;
> +
> +	bridge = pci_host_bridge_from_priv(rc);
> +	pci_stop_root_bus(bridge->bus);
> +	pci_remove_root_bus(bridge->bus);
> +

Is it necessary to stop the PCIe link here?

The setup path explicitly starts the link with cdns_pcie_start_link(),
but this teardown function omits stopping it or disabling PTM responses.
Leaving the link active after the bus is unregistered could lead to
spurious interrupts or unhandled DMA requests.

> +	cdns_pcie_debugfs_deinit(&rc->pcie);

Similar to the endpoint path, should debugfs teardown happen before
the hardware is disabled to avoid concurrent access faults?

> +}

[ ... ]

> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 0bc9e6e90e0e0..873d496c440f0 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -370,6 +370,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
>  
>  	cdns_pcie_host_deinit(rc);
>  	cdns_pcie_host_link_disable(rc);
> +	cdns_pcie_debugfs_deinit(&rc->pcie);
>  }

Should this debugfs teardown be moved to the beginning of the function
for the same reason mentioned above?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260508034101.1910036-1-18255117159@163.com?part=2

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-08  4:19   ` sashiko-bot
@ 2026-05-08  4:31     ` Hans Zhang
  0 siblings, 0 replies; 19+ messages in thread
From: Hans Zhang @ 2026-05-08  4:31 UTC (permalink / raw)
  To: sashiko, Manikandan K Pillai; +Cc: linux-pci



On 5/8/26 12:19, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
> - [High] PCIE_CADENCE_DEBUGFS tristate configuration causes build failure and module linkage issues.
> - [High] Race condition in debugfs deinitialization leads to unprotected hardware access.
> - [High] Missing Runtime PM reference in debugfs read handler causes system crash.
> - [Medium] Missing link teardown in `cdns_pcie_hpa_host_disable`.
> - [Medium] Incorrect bitmask `CDNS_PCIE_LGA_LTSSM_STATUS_MASK` truncates LTSSM states.
> --
> 
> commit b032928b3c42715d7bb97e0bd26a99d252cd98d9
> Author: Hans Zhang <18255117159@163.com>
> 
> PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
> 
> Add the debugfs property to provide a view of the current link's LTSSM
> status from the Root Port device.
> 
>> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
>> index 9e651d5459735..cb010bc97aad3 100644
>> --- a/drivers/pci/controller/cadence/Kconfig
>> +++ b/drivers/pci/controller/cadence/Kconfig
>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>>   config PCIE_CADENCE
>>   	tristate
>>   
>> +config PCIE_CADENCE_DEBUGFS
>> +	tristate "Cadence PCIe debugfs entries"
> 
> Could this Kconfig option be changed to a bool?

This is the reminder from Mani that I made the necessary modifications 
for, because the Cadence PCIe driver is a support module.

> 
> When configured as a module (=m), Kbuild defines
> CONFIG_PCIE_CADENCE_DEBUGFS_MODULE, not CONFIG_PCIE_CADENCE_DEBUGFS. As a
> result, the preprocessor check in pcie-cadence.h evaluates to false, causing
> the header to declare empty static inline stubs. When pcie-cadence-debugfs.c
> defines the non-static versions, the build fails with a function redefinition
> error.
> 
> Furthermore, changing the check to IS_ENABLED(CONFIG_PCIE_CADENCE_DEBUGFS)
> would cause linkage errors if the core drivers are built-in while the debugfs
> feature is a module, since built-in code cannot call module functions.
> 
> [ ... ]
> 
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>> new file mode 100644
>> index 0000000000000..a4f0c4f6f98f4
>> --- /dev/null
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>> @@ -0,0 +1,208 @@
> [ ... ]
>> +#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK	GENMASK(29, 24)
> 
> Does this mask need to be extended to cover all possible states?
> 
> This mask covers only 6 bits, allowing it to extract values up to 63.
> However, the cdns_pcie_ltssm enum defines states up to 127. If the
> hardware enters a state 64 or higher, FIELD_GET will silently truncate
> the value, making state 65 appear as state 1.

Hi Manikandan,

I have already confirmed this with Manikandan. You can ask Manikandan to 
confirm it again.


> 
> [ ... ]
>> +static int ltssm_status_show(struct seq_file *s, void *v)
>> +{
>> +	struct cdns_pcie *pci = s->private;
>> +	enum cdns_pcie_ltssm ltssm;
>> +	u32 reg;
>> +
>> +	if (pci->is_hpa) {
>> +		reg = cdns_pcie_hpa_readl(pci, REG_BANK_IP_REG,
>> +					CDNS_PCIE_HPA_PHY_DBG_STS_REG0);
>> +		ltssm = FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, reg);
>> +	} else {
>> +		reg = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
>> +		ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, reg);
>> +	}
> 
> Is a runtime PM reference required here before accessing the hardware?
> 
> Since the driver supports power management, the controller might be in a
> low-power, clock-gated state when this debugfs file is read. Reading the
> registers without calling pm_runtime_get_sync() first could cause a bus fault
> and crash the system.
> 
> [ ... ]
> 
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
>> index c0e1194a936b3..38a0157b60dc7 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
>> @@ -659,6 +659,7 @@ void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)
>>   	pci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr,
>>   			      SZ_128K);
>>   	pci_epc_mem_exit(epc);
>> +	cdns_pcie_debugfs_deinit(&ep->pcie);
>>   }
> 
> Should cdns_pcie_debugfs_deinit() be called earlier in the teardown process?

Will change.

> 
> If a userspace process is currently reading the debugfs file while the module
> is being removed, ltssm_status_show() could attempt to read registers after
> the hardware has been deactivated, potentially resulting in a bus fault.
> Removing the debugfs entries first ensures no new reads can begin while the
> hardware is shut down.
> 
> [ ... ]
> 
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
>> index 0f540bed58e88..8bf7cc106413b 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
>> @@ -309,6 +309,18 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc)
>>   }
>>   EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup);
>>   
>> +void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
>> +{
>> +	struct pci_host_bridge *bridge;
>> +
>> +	bridge = pci_host_bridge_from_priv(rc);
>> +	pci_stop_root_bus(bridge->bus);
>> +	pci_remove_root_bus(bridge->bus);
>> +
> 
> Is it necessary to stop the PCIe link here?
The HPA driver does not yet provide the "stop the PCIe link" function. 
More will be added later.

> 
> The setup path explicitly starts the link with cdns_pcie_start_link(),
> but this teardown function omits stopping it or disabling PTM responses.
> Leaving the link active after the bus is unregistered could lead to
> spurious interrupts or unhandled DMA requests.
> 
>> +	cdns_pcie_debugfs_deinit(&rc->pcie);
> 
> Similar to the endpoint path, should debugfs teardown happen before
> the hardware is disabled to avoid concurrent access faults?

Will change.

> 
>> +}
> 
> [ ... ]
> 
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> index 0bc9e6e90e0e0..873d496c440f0 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> @@ -370,6 +370,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
>>   
>>   	cdns_pcie_host_deinit(rc);
>>   	cdns_pcie_host_link_disable(rc);
>> +	cdns_pcie_debugfs_deinit(&rc->pcie);
>>   }
> 
> Should this debugfs teardown be moved to the beginning of the function
> for the same reason mentioned above?


Will change.


Best regards,
Hans
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-08  3:41 ` [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link Hans Zhang
  2026-05-08  4:19   ` sashiko-bot
@ 2026-05-13  5:23   ` Aksh Garg
  2026-05-13  6:11     ` Manikandan Karunakaran Pillai
  2026-05-13  6:37     ` Hans Zhang
  1 sibling, 2 replies; 19+ messages in thread
From: Aksh Garg @ 2026-05-13  5:23 UTC (permalink / raw)
  To: Hans Zhang, bhelgaas, lpieralisi, kwilczynski, mani, hans.zhang
  Cc: robh, mpillai, linux-pci, linux-kernel, Siddharth Vadapalli



On 08/05/26 09:11, Hans Zhang wrote:
> Add the debugfs property to provide a view of the current link's LTSSM
> status from the Root Port device.
> 
> Test example:
>    # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
>    L0_STATE (0x29)
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
>   Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
>   drivers/pci/controller/cadence/Kconfig        |   9 +
>   drivers/pci/controller/cadence/Makefile       |   1 +
>   drivers/pci/controller/cadence/pci-sky1.c     |   3 +
>   .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
>   .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
>   .../cadence/pcie-cadence-host-hpa.c           |  20 +-
>   .../controller/cadence/pcie-cadence-host.c    |   9 +-
>   drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
>   9 files changed, 406 insertions(+), 2 deletions(-)
>   create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>   create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c
> 
> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/Documentation/ABI/testing/debugfs-cdns-pcie
> new file mode 100644
> index 000000000000..659ad2ab70e4
> --- /dev/null
> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
> @@ -0,0 +1,5 @@
> +What:		/sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
> +Date:		March 2026
> +Contact:	Hans Zhang <18255117159@163.com>
> +Description:	(RO) Read will return the current PCIe LTSSM state in both
> +		string and raw value.
> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> index 9e651d545973..cb010bc97aad 100644
> --- a/drivers/pci/controller/cadence/Kconfig
> +++ b/drivers/pci/controller/cadence/Kconfig
> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>   config PCIE_CADENCE
>   	tristate
>   
> +config PCIE_CADENCE_DEBUGFS
> +	tristate "Cadence PCIe debugfs entries"
> +	depends on DEBUG_FS
> +	depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
> +	help
> +	  Say Y here to enable debugfs entries for the PCIe controller. These
> +	  entries provide various debug features related to the controller and
> +	  the LTSSM status of link can be displayed.
> +
>   config PCIE_CADENCE_HOST
>   	tristate
>   	depends on OF

[...]

>   
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 9a464cbaf073..a1c531fd2061 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
>   	REG_BANKS_MAX,
>   };
>   
> +enum cdns_pcie_ltssm {
> +	CDNS_PCIE_LTSSM_DETECT_QUIET		= 0,
> +	CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY	= 1,
> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE		= 2,
> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_1		= 3,
> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_2		= 4,
> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_3		= 5,
> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_ST	= 6,
> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_1		= 7,
> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE		= 8,
> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_1	= 9,
> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_2	= 10,
> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_3	= 11,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE	= 12,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1	= 13,
> +	CDNS_PCIE_LTSSM_POLLING_CONFIG		= 14,
> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_1	= 15,
> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_2	= 16,
> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC	= 17,
> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1	= 18,
> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2	= 19,
> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC	= 20,
> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC	= 21,
> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC	= 23,
> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP	= 24,
> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1	= 25,
> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2	= 26,
> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP	= 27,
> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP	= 28,
> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP	= 30,
> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1	= 31,
> +	CDNS_PCIE_LTSSM_DUMMY_STATE_1		= 32,
> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE		= 33,
> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1	= 34,
> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2	= 35,
> +	CDNS_PCIE_LTSSM_CONFIG_IDLE		= 36,
> +	CDNS_PCIE_LTSSM_CONFIG_IDLE_1		= 37,
> +	CDNS_PCIE_LTSSM_DUMMY_STATE_2		= 38,
> +	CDNS_PCIE_LTSSM_DUMMY_STATE_3		= 39,
> +	CDNS_PCIE_LTSSM_DUMMY_STATE_4		= 40,
> +	CDNS_PCIE_LTSSM_L0_STATE		= 41,
> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK	= 42,
> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1	= 43,
> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG	= 44,
> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1	= 45,
> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE		= 46,
> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE_1		= 47,
> +	CDNS_PCIE_LTSSM_DISABLE_LINK		= 48,
> +	CDNS_PCIE_LTSSM_DISABLE_LINK_1		= 49,
> +	CDNS_PCIE_LTSSM_DISABLE_LINK_2		= 50,
> +	CDNS_PCIE_LTSSM_DISABLE_LINK_3		= 51,
> +	CDNS_PCIE_LTSSM_DISABLE_LINK_4		= 52,
> +	CDNS_PCIE_LTSSM_DISABLE_LINK_5		= 53,
> +	CDNS_PCIE_LTSSM_DISABLE_LINK_6		= 54,
> +	CDNS_PCIE_LTSSM_DISABLE_LINK_7		= 55,
> +	CDNS_PCIE_LTSSM_HOT_RESET		= 56,
> +	CDNS_PCIE_LTSSM_HOT_RESET_1		= 57,
> +	CDNS_PCIE_LTSSM_HOT_RESET_2		= 58,
> +	CDNS_PCIE_LTSSM_HOT_RESET_3		= 59,
> +	CDNS_PCIE_LTSSM_L0S_ENTRY		= 60,
> +	CDNS_PCIE_LTSSM_L0S_1			= 61,
> +	CDNS_PCIE_LTSSM_L0S_2			= 62,
> +	CDNS_PCIE_LTSSM_L0S_3			= 63,
> +	CDNS_PCIE_LTSSM_L0S_4			= 64,
> +	CDNS_PCIE_LTSSM_L0S_5			= 65,
> +	CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX	= 66,
> +	CDNS_PCIE_LTSSM_TX_FTS_ENTRY		= 67,
> +	CDNS_PCIE_LTSSM_TX_FTS_1		= 68,
> +	CDNS_PCIE_LTSSM_TX_FTS_2		= 69,
> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST		= 70,
> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1		= 71,
> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2		= 72,
> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3		= 73,
> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED		= 74,
> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_1	= 75,
> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_2	= 76,
> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_3	= 77,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY	= 87,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1	= 89,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT	= 90,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1	= 91,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2	= 92,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3	= 93,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4	= 94,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5	= 95,
> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE	= 96,
> +	CDNS_PCIE_LTSSM_L1_ENTRY		= 97,
> +	CDNS_PCIE_LTSSM_L1_1			= 98,
> +	CDNS_PCIE_LTSSM_L1_2			= 99,
> +	CDNS_PCIE_LTSSM_L1_3			= 100,
> +	CDNS_PCIE_LTSSM_L1_4			= 101,
> +	CDNS_PCIE_LTSSM_L1_IDLE			= 102,
> +	CDNS_PCIE_LTSSM_L1_EXIT			= 103,
> +	CDNS_PCIE_LTSSM_L2_ENTRY		= 104,
> +	CDNS_PCIE_LTSSM_L2_1			= 105,
> +	CDNS_PCIE_LTSSM_L2_2			= 106,
> +	CDNS_PCIE_LTSSM_L2_3			= 107,
> +	CDNS_PCIE_LTSSM_L2_4			= 108,
> +	CDNS_PCIE_LTSSM_L2_5			= 109,
> +	CDNS_PCIE_LTSSM_L2_IDLE			= 110,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY	= 111,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1	= 112,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2	= 113,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3	= 114,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4	= 115,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5	= 116,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY = 117,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE	= 118,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT	= 119,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1	= 120,
> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2	= 121,
> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
> +};

Hi Hans,

The LTSSM state encoding in your patches do not align with the state 
encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
applied your patches, the LTSSM value in the debugfs for the PCIe
subsystem (which have an EP connected to it) came out to be 0x10, which
points to the state "PCIE_L0". However, the debugfs prints the state as
"POLLING_CONFIG_2 (0x10)", which seems to be incorrect.

The LTSSM state encodings for TI SoCs using Cadence PCIe IP is provided 
in the J7200 TRM section 12.2.3.4.14 at:
https://www.ti.com/lit/pdf/spruiu1

Regards,
Aksh Garg


> +
>   struct cdns_pcie_ops {



^ permalink raw reply	[flat|nested] 19+ messages in thread

* RE: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  5:23   ` Aksh Garg
@ 2026-05-13  6:11     ` Manikandan Karunakaran Pillai
  2026-05-13  6:39       ` Hans Zhang
  2026-05-13  8:34       ` Aksh Garg
  2026-05-13  6:37     ` Hans Zhang
  1 sibling, 2 replies; 19+ messages in thread
From: Manikandan Karunakaran Pillai @ 2026-05-13  6:11 UTC (permalink / raw)
  To: Aksh Garg, Hans Zhang, bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, hans.zhang@cixtech.com
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli

>On 08/05/26 09:11, Hans Zhang wrote:
>> Add the debugfs property to provide a view of the current link's LTSSM
>> status from the Root Port device.
>>
>> Test example:
>>    # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
>>    L0_STATE (0x29)
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> ---
>>   Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
>>   drivers/pci/controller/cadence/Kconfig        |   9 +
>>   drivers/pci/controller/cadence/Makefile       |   1 +
>>   drivers/pci/controller/cadence/pci-sky1.c     |   3 +
>>   .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
>>   .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
>>   .../cadence/pcie-cadence-host-hpa.c           |  20 +-
>>   .../controller/cadence/pcie-cadence-host.c    |   9 +-
>>   drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
>>   9 files changed, 406 insertions(+), 2 deletions(-)
>>   create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>>   create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>
>> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie
>b/Documentation/ABI/testing/debugfs-cdns-pcie
>> new file mode 100644
>> index 000000000000..659ad2ab70e4
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
>> @@ -0,0 +1,5 @@
>> +What:		/sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
>> +Date:		March 2026
>> +Contact:	Hans Zhang <18255117159@163.com>
>> +Description:	(RO) Read will return the current PCIe LTSSM state in both
>> +		string and raw value.
>> diff --git a/drivers/pci/controller/cadence/Kconfig
>b/drivers/pci/controller/cadence/Kconfig
>> index 9e651d545973..cb010bc97aad 100644
>> --- a/drivers/pci/controller/cadence/Kconfig
>> +++ b/drivers/pci/controller/cadence/Kconfig
>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>>   config PCIE_CADENCE
>>   	tristate
>>
>> +config PCIE_CADENCE_DEBUGFS
>> +	tristate "Cadence PCIe debugfs entries"
>> +	depends on DEBUG_FS
>> +	depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
>> +	help
>> +	  Say Y here to enable debugfs entries for the PCIe controller. These
>> +	  entries provide various debug features related to the controller and
>> +	  the LTSSM status of link can be displayed.
>> +
>>   config PCIE_CADENCE_HOST
>>   	tristate
>>   	depends on OF
>
>[...]
>
>>
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
>b/drivers/pci/controller/cadence/pcie-cadence.h
>> index 9a464cbaf073..a1c531fd2061 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>> @@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
>>   	REG_BANKS_MAX,
>>   };
>>
>> +enum cdns_pcie_ltssm {
>> +	CDNS_PCIE_LTSSM_DETECT_QUIET		= 0,
>> +	CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY	= 1,
>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE		= 2,
>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_1		= 3,
>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_2		= 4,
>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_3		= 5,
>> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_ST	= 6,
>> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_1		= 7,
>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE		= 8,
>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_1	= 9,
>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_2	= 10,
>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_3	= 11,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE	= 12,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1	= 13,
>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG		= 14,
>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_1	= 15,
>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_2	= 16,
>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC	= 17,
>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1	= 18,
>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2	= 19,
>> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC	= 20,
>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC	= 21,
>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC	= 23,
>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP	= 24,
>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1	= 25,
>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2	= 26,
>> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP	= 27,
>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP	= 28,
>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP	= 30,
>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1	= 31,
>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_1		= 32,
>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE		= 33,
>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1	= 34,
>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2	= 35,
>> +	CDNS_PCIE_LTSSM_CONFIG_IDLE		= 36,
>> +	CDNS_PCIE_LTSSM_CONFIG_IDLE_1		= 37,
>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_2		= 38,
>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_3		= 39,
>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_4		= 40,
>> +	CDNS_PCIE_LTSSM_L0_STATE		= 41,
>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK	= 42,
>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1	= 43,
>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG	= 44,
>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1	= 45,
>> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE		= 46,
>> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE_1		= 47,
>> +	CDNS_PCIE_LTSSM_DISABLE_LINK		= 48,
>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_1		= 49,
>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_2		= 50,
>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_3		= 51,
>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_4		= 52,
>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_5		= 53,
>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_6		= 54,
>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_7		= 55,
>> +	CDNS_PCIE_LTSSM_HOT_RESET		= 56,
>> +	CDNS_PCIE_LTSSM_HOT_RESET_1		= 57,
>> +	CDNS_PCIE_LTSSM_HOT_RESET_2		= 58,
>> +	CDNS_PCIE_LTSSM_HOT_RESET_3		= 59,
>> +	CDNS_PCIE_LTSSM_L0S_ENTRY		= 60,
>> +	CDNS_PCIE_LTSSM_L0S_1			= 61,
>> +	CDNS_PCIE_LTSSM_L0S_2			= 62,
>> +	CDNS_PCIE_LTSSM_L0S_3			= 63,
>> +	CDNS_PCIE_LTSSM_L0S_4			= 64,
>> +	CDNS_PCIE_LTSSM_L0S_5			= 65,
>> +	CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX	= 66,
>> +	CDNS_PCIE_LTSSM_TX_FTS_ENTRY		= 67,
>> +	CDNS_PCIE_LTSSM_TX_FTS_1		= 68,
>> +	CDNS_PCIE_LTSSM_TX_FTS_2		= 69,
>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST		= 70,
>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1		= 71,
>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2		= 72,
>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3		= 73,
>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED		= 74,
>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_1	= 75,
>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_2	= 76,
>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_3	= 77,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY	= 87,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1	= 89,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT	= 90,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1	= 91,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2	= 92,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3	= 93,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4	= 94,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5	= 95,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE	= 96,
>> +	CDNS_PCIE_LTSSM_L1_ENTRY		= 97,
>> +	CDNS_PCIE_LTSSM_L1_1			= 98,
>> +	CDNS_PCIE_LTSSM_L1_2			= 99,
>> +	CDNS_PCIE_LTSSM_L1_3			= 100,
>> +	CDNS_PCIE_LTSSM_L1_4			= 101,
>> +	CDNS_PCIE_LTSSM_L1_IDLE			= 102,
>> +	CDNS_PCIE_LTSSM_L1_EXIT			= 103,
>> +	CDNS_PCIE_LTSSM_L2_ENTRY		= 104,
>> +	CDNS_PCIE_LTSSM_L2_1			= 105,
>> +	CDNS_PCIE_LTSSM_L2_2			= 106,
>> +	CDNS_PCIE_LTSSM_L2_3			= 107,
>> +	CDNS_PCIE_LTSSM_L2_4			= 108,
>> +	CDNS_PCIE_LTSSM_L2_5			= 109,
>> +	CDNS_PCIE_LTSSM_L2_IDLE			= 110,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY	= 111,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1	= 112,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2	= 113,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3	= 114,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4	= 115,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5	= 116,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY =
>117,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE	= 118,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT	= 119,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1	= 120,
>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2	= 121,
>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
>> +};
>

The above LTSSM states are internal LTSSM encoding states and may not be available for software to use.
The LTSSM states in the document pointed by Aksh (TI Soc) are the states  available in all cadence controllers.

>Hi Hans,
>
>The LTSSM state encoding in your patches do not align with the state
>encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
>applied your patches, the LTSSM value in the debugfs for the PCIe
>subsystem (which have an EP connected to it) came out to be 0x10, which
>points to the state "PCIE_L0". However, the debugfs prints the state as
>"POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
>
>The LTSSM state encodings for TI SoCs using Cadence PCIe IP is provided
>in the J7200 TRM section 12.2.3.4.14 at:
>https://urldefense.com/v3/__https://www.ti.com/lit/pdf/spruiu1__;!!EHscmS1
>ygiU1lA!AudWpZJoYT3_nfvc33jiZrUFh75KB4DU-
>na_9SNZTib3etI9BNC3Jq8RlPxVouCPY2Rt7SyqrNI$
>
>Regards,
>Aksh Garg
>
>
>> +
>>   struct cdns_pcie_ops {
>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  6:11     ` Manikandan Karunakaran Pillai
@ 2026-05-13  6:39       ` Hans Zhang
  2026-05-13  7:08         ` Manikandan Karunakaran Pillai
  2026-05-13  8:34       ` Aksh Garg
  1 sibling, 1 reply; 19+ messages in thread
From: Hans Zhang @ 2026-05-13  6:39 UTC (permalink / raw)
  To: Manikandan Karunakaran Pillai, Aksh Garg, bhelgaas@google.com,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
	hans.zhang@cixtech.com
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli



On 5/13/26 14:11, Manikandan Karunakaran Pillai wrote:
>> On 08/05/26 09:11, Hans Zhang wrote:
>>> Add the debugfs property to provide a view of the current link's LTSSM
>>> status from the Root Port device.
>>>
>>> Test example:
>>>     # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
>>>     L0_STATE (0x29)
>>>
>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>> ---
>>>    Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
>>>    drivers/pci/controller/cadence/Kconfig        |   9 +
>>>    drivers/pci/controller/cadence/Makefile       |   1 +
>>>    drivers/pci/controller/cadence/pci-sky1.c     |   3 +
>>>    .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
>>>    .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
>>>    .../cadence/pcie-cadence-host-hpa.c           |  20 +-
>>>    .../controller/cadence/pcie-cadence-host.c    |   9 +-
>>>    drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
>>>    9 files changed, 406 insertions(+), 2 deletions(-)
>>>    create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>>>    create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>
>>> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie
>> b/Documentation/ABI/testing/debugfs-cdns-pcie
>>> new file mode 100644
>>> index 000000000000..659ad2ab70e4
>>> --- /dev/null
>>> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
>>> @@ -0,0 +1,5 @@
>>> +What:		/sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
>>> +Date:		March 2026
>>> +Contact:	Hans Zhang <18255117159@163.com>
>>> +Description:	(RO) Read will return the current PCIe LTSSM state in both
>>> +		string and raw value.
>>> diff --git a/drivers/pci/controller/cadence/Kconfig
>> b/drivers/pci/controller/cadence/Kconfig
>>> index 9e651d545973..cb010bc97aad 100644
>>> --- a/drivers/pci/controller/cadence/Kconfig
>>> +++ b/drivers/pci/controller/cadence/Kconfig
>>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>>>    config PCIE_CADENCE
>>>    	tristate
>>>
>>> +config PCIE_CADENCE_DEBUGFS
>>> +	tristate "Cadence PCIe debugfs entries"
>>> +	depends on DEBUG_FS
>>> +	depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
>>> +	help
>>> +	  Say Y here to enable debugfs entries for the PCIe controller. These
>>> +	  entries provide various debug features related to the controller and
>>> +	  the LTSSM status of link can be displayed.
>>> +
>>>    config PCIE_CADENCE_HOST
>>>    	tristate
>>>    	depends on OF
>>
>> [...]
>>
>>>
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
>> b/drivers/pci/controller/cadence/pcie-cadence.h
>>> index 9a464cbaf073..a1c531fd2061 100644
>>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>>> @@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
>>>    	REG_BANKS_MAX,
>>>    };
>>>
>>> +enum cdns_pcie_ltssm {
>>> +	CDNS_PCIE_LTSSM_DETECT_QUIET		= 0,
>>> +	CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY	= 1,
>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE		= 2,
>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_1		= 3,
>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_2		= 4,
>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_3		= 5,
>>> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_ST	= 6,
>>> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_1		= 7,
>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE		= 8,
>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_1	= 9,
>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_2	= 10,
>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_3	= 11,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE	= 12,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1	= 13,
>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG		= 14,
>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_1	= 15,
>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_2	= 16,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC	= 17,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1	= 18,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2	= 19,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC	= 20,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC	= 21,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC	= 23,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP	= 24,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1	= 25,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2	= 26,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP	= 27,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP	= 28,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP	= 30,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1	= 31,
>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_1		= 32,
>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE		= 33,
>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1	= 34,
>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2	= 35,
>>> +	CDNS_PCIE_LTSSM_CONFIG_IDLE		= 36,
>>> +	CDNS_PCIE_LTSSM_CONFIG_IDLE_1		= 37,
>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_2		= 38,
>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_3		= 39,
>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_4		= 40,
>>> +	CDNS_PCIE_LTSSM_L0_STATE		= 41,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK	= 42,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1	= 43,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG	= 44,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1	= 45,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE		= 46,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE_1		= 47,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK		= 48,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_1		= 49,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_2		= 50,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_3		= 51,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_4		= 52,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_5		= 53,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_6		= 54,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_7		= 55,
>>> +	CDNS_PCIE_LTSSM_HOT_RESET		= 56,
>>> +	CDNS_PCIE_LTSSM_HOT_RESET_1		= 57,
>>> +	CDNS_PCIE_LTSSM_HOT_RESET_2		= 58,
>>> +	CDNS_PCIE_LTSSM_HOT_RESET_3		= 59,
>>> +	CDNS_PCIE_LTSSM_L0S_ENTRY		= 60,
>>> +	CDNS_PCIE_LTSSM_L0S_1			= 61,
>>> +	CDNS_PCIE_LTSSM_L0S_2			= 62,
>>> +	CDNS_PCIE_LTSSM_L0S_3			= 63,
>>> +	CDNS_PCIE_LTSSM_L0S_4			= 64,
>>> +	CDNS_PCIE_LTSSM_L0S_5			= 65,
>>> +	CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX	= 66,
>>> +	CDNS_PCIE_LTSSM_TX_FTS_ENTRY		= 67,
>>> +	CDNS_PCIE_LTSSM_TX_FTS_1		= 68,
>>> +	CDNS_PCIE_LTSSM_TX_FTS_2		= 69,
>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST		= 70,
>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1		= 71,
>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2		= 72,
>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3		= 73,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED		= 74,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_1	= 75,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_2	= 76,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_3	= 77,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY	= 87,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1	= 89,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT	= 90,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1	= 91,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2	= 92,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3	= 93,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4	= 94,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5	= 95,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE	= 96,
>>> +	CDNS_PCIE_LTSSM_L1_ENTRY		= 97,
>>> +	CDNS_PCIE_LTSSM_L1_1			= 98,
>>> +	CDNS_PCIE_LTSSM_L1_2			= 99,
>>> +	CDNS_PCIE_LTSSM_L1_3			= 100,
>>> +	CDNS_PCIE_LTSSM_L1_4			= 101,
>>> +	CDNS_PCIE_LTSSM_L1_IDLE			= 102,
>>> +	CDNS_PCIE_LTSSM_L1_EXIT			= 103,
>>> +	CDNS_PCIE_LTSSM_L2_ENTRY		= 104,
>>> +	CDNS_PCIE_LTSSM_L2_1			= 105,
>>> +	CDNS_PCIE_LTSSM_L2_2			= 106,
>>> +	CDNS_PCIE_LTSSM_L2_3			= 107,
>>> +	CDNS_PCIE_LTSSM_L2_4			= 108,
>>> +	CDNS_PCIE_LTSSM_L2_5			= 109,
>>> +	CDNS_PCIE_LTSSM_L2_IDLE			= 110,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY	= 111,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1	= 112,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2	= 113,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3	= 114,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4	= 115,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5	= 116,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY =
>> 117,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE	= 118,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT	= 119,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1	= 120,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2	= 121,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
>>> +};
>>
> 
> The above LTSSM states are internal LTSSM encoding states and may not be available for software to use.
> The LTSSM states in the document pointed by Aksh (TI Soc) are the states  available in all cadence controllers.

Hi Manikandan,

For LGA IP, can't the registers be read out through the common registers 
of Cadence IP? Just like the approach of DWC. And the HPA IP is readable.


Best regards,
Hans

> 
>> Hi Hans,
>>
>> The LTSSM state encoding in your patches do not align with the state
>> encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
>> applied your patches, the LTSSM value in the debugfs for the PCIe
>> subsystem (which have an EP connected to it) came out to be 0x10, which
>> points to the state "PCIE_L0". However, the debugfs prints the state as
>> "POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
>>
>> The LTSSM state encodings for TI SoCs using Cadence PCIe IP is provided
>> in the J7200 TRM section 12.2.3.4.14 at:
>> https://urldefense.com/v3/__https://www.ti.com/lit/pdf/spruiu1__;!!EHscmS1
>> ygiU1lA!AudWpZJoYT3_nfvc33jiZrUFh75KB4DU-
>> na_9SNZTib3etI9BNC3Jq8RlPxVouCPY2Rt7SyqrNI$
>>
>> Regards,
>> Aksh Garg
>>
>>
>>> +
>>>    struct cdns_pcie_ops {
>>
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* RE: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  6:39       ` Hans Zhang
@ 2026-05-13  7:08         ` Manikandan Karunakaran Pillai
  0 siblings, 0 replies; 19+ messages in thread
From: Manikandan Karunakaran Pillai @ 2026-05-13  7:08 UTC (permalink / raw)
  To: Hans Zhang, Aksh Garg, bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli



>EXTERNAL MAIL
>
>
>
>
>On 5/13/26 14:11, Manikandan Karunakaran Pillai wrote:
>>> On 08/05/26 09:11, Hans Zhang wrote:
>>>> Add the debugfs property to provide a view of the current link's LTSSM
>>>> status from the Root Port device.
>>>>
>>>> Test example:
>>>>     # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
>>>>     L0_STATE (0x29)
>>>>
>>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>>> ---
>>>>    Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
>>>>    drivers/pci/controller/cadence/Kconfig        |   9 +
>>>>    drivers/pci/controller/cadence/Makefile       |   1 +
>>>>    drivers/pci/controller/cadence/pci-sky1.c     |   3 +
>>>>    .../controller/cadence/pcie-cadence-debugfs.c | 208
>++++++++++++++++++
>>>>    .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
>>>>    .../cadence/pcie-cadence-host-hpa.c           |  20 +-
>>>>    .../controller/cadence/pcie-cadence-host.c    |   9 +-
>>>>    drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
>>>>    9 files changed, 406 insertions(+), 2 deletions(-)
>>>>    create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>>>>    create mode 100644 drivers/pci/controller/cadence/pcie-cadence-
>debugfs.c
>>>>
>>>> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie
>>> b/Documentation/ABI/testing/debugfs-cdns-pcie
>>>> new file mode 100644
>>>> index 000000000000..659ad2ab70e4
>>>> --- /dev/null
>>>> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
>>>> @@ -0,0 +1,5 @@
>>>> +What:		/sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
>>>> +Date:		March 2026
>>>> +Contact:	Hans Zhang <18255117159@163.com>
>>>> +Description:	(RO) Read will return the current PCIe LTSSM state in
>both
>>>> +		string and raw value.
>>>> diff --git a/drivers/pci/controller/cadence/Kconfig
>>> b/drivers/pci/controller/cadence/Kconfig
>>>> index 9e651d545973..cb010bc97aad 100644
>>>> --- a/drivers/pci/controller/cadence/Kconfig
>>>> +++ b/drivers/pci/controller/cadence/Kconfig
>>>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>>>>    config PCIE_CADENCE
>>>>    	tristate
>>>>
>>>> +config PCIE_CADENCE_DEBUGFS
>>>> +	tristate "Cadence PCIe debugfs entries"
>>>> +	depends on DEBUG_FS
>>>> +	depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
>>>> +	help
>>>> +	  Say Y here to enable debugfs entries for the PCIe controller. These
>>>> +	  entries provide various debug features related to the controller and
>>>> +	  the LTSSM status of link can be displayed.
>>>> +
>>>>    config PCIE_CADENCE_HOST
>>>>    	tristate
>>>>    	depends on OF
>>>
>>> [...]
>>>
>>>>
>>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
>>> b/drivers/pci/controller/cadence/pcie-cadence.h
>>>> index 9a464cbaf073..a1c531fd2061 100644
>>>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>>>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>>>> @@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
>>>>    	REG_BANKS_MAX,
>>>>    };
>>>>
>>>> +enum cdns_pcie_ltssm {
>>>> +	CDNS_PCIE_LTSSM_DETECT_QUIET		= 0,
>>>> +	CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY	= 1,
>>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE		= 2,
>>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_1		= 3,
>>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_2		= 4,
>>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_3		= 5,
>>>> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_ST	= 6,
>>>> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_1		= 7,
>>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE		= 8,
>>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_1	= 9,
>>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_2	= 10,
>>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_3	= 11,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE	= 12,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1	= 13,
>>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG		= 14,
>>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_1	= 15,
>>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_2	= 16,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC	= 17,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1	= 18,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2	= 19,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC	= 20,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC	= 21,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC	= 23,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP	= 24,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1	= 25,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2	= 26,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP	= 27,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP	= 28,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP	= 30,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1	= 31,
>>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_1		= 32,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE		= 33,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1	= 34,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2	= 35,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_IDLE		= 36,
>>>> +	CDNS_PCIE_LTSSM_CONFIG_IDLE_1		= 37,
>>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_2		= 38,
>>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_3		= 39,
>>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_4		= 40,
>>>> +	CDNS_PCIE_LTSSM_L0_STATE		= 41,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK	= 42,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1	= 43,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG	= 44,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1	= 45,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE		= 46,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE_1		= 47,
>>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK		= 48,
>>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_1		= 49,
>>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_2		= 50,
>>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_3		= 51,
>>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_4		= 52,
>>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_5		= 53,
>>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_6		= 54,
>>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_7		= 55,
>>>> +	CDNS_PCIE_LTSSM_HOT_RESET		= 56,
>>>> +	CDNS_PCIE_LTSSM_HOT_RESET_1		= 57,
>>>> +	CDNS_PCIE_LTSSM_HOT_RESET_2		= 58,
>>>> +	CDNS_PCIE_LTSSM_HOT_RESET_3		= 59,
>>>> +	CDNS_PCIE_LTSSM_L0S_ENTRY		= 60,
>>>> +	CDNS_PCIE_LTSSM_L0S_1			= 61,
>>>> +	CDNS_PCIE_LTSSM_L0S_2			= 62,
>>>> +	CDNS_PCIE_LTSSM_L0S_3			= 63,
>>>> +	CDNS_PCIE_LTSSM_L0S_4			= 64,
>>>> +	CDNS_PCIE_LTSSM_L0S_5			= 65,
>>>> +	CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX	= 66,
>>>> +	CDNS_PCIE_LTSSM_TX_FTS_ENTRY		= 67,
>>>> +	CDNS_PCIE_LTSSM_TX_FTS_1		= 68,
>>>> +	CDNS_PCIE_LTSSM_TX_FTS_2		= 69,
>>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST		= 70,
>>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1		= 71,
>>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2		= 72,
>>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3		= 73,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED		= 74,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_1	= 75,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_2	= 76,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_3	= 77,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
>>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY	= 87,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1	= 89,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT	= 90,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1	= 91,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2	= 92,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3	= 93,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4	= 94,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5	= 95,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE	= 96,
>>>> +	CDNS_PCIE_LTSSM_L1_ENTRY		= 97,
>>>> +	CDNS_PCIE_LTSSM_L1_1			= 98,
>>>> +	CDNS_PCIE_LTSSM_L1_2			= 99,
>>>> +	CDNS_PCIE_LTSSM_L1_3			= 100,
>>>> +	CDNS_PCIE_LTSSM_L1_4			= 101,
>>>> +	CDNS_PCIE_LTSSM_L1_IDLE			= 102,
>>>> +	CDNS_PCIE_LTSSM_L1_EXIT			= 103,
>>>> +	CDNS_PCIE_LTSSM_L2_ENTRY		= 104,
>>>> +	CDNS_PCIE_LTSSM_L2_1			= 105,
>>>> +	CDNS_PCIE_LTSSM_L2_2			= 106,
>>>> +	CDNS_PCIE_LTSSM_L2_3			= 107,
>>>> +	CDNS_PCIE_LTSSM_L2_4			= 108,
>>>> +	CDNS_PCIE_LTSSM_L2_5			= 109,
>>>> +	CDNS_PCIE_LTSSM_L2_IDLE			= 110,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY	= 111,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1	= 112,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2	= 113,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3	= 114,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4	= 115,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5	= 116,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY =
>>> 117,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE	= 118,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT	= 119,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1	= 120,
>>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2	= 121,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
>>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
>>>> +};
>>>
>>
>> The above LTSSM states are internal LTSSM encoding states and may not be
>available for software to use.
>> The LTSSM states in the document pointed by Aksh (TI Soc) are the states
>available in all cadence controllers.
>
>Hi Manikandan,
>
>For LGA IP, can't the registers be read out through the common registers
>of Cadence IP? Just like the approach of DWC. And the HPA IP is readable.
>
>

The LTSSM status is available at offset IP_REG_I_DBG_STS_0 where the link status is being read from.
There may be other location in the SoC where vendor might be mapping LTSSM status also.

>Best regards,
>Hans
>
>>
>>> Hi Hans,
>>>
>>> The LTSSM state encoding in your patches do not align with the state
>>> encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
>>> applied your patches, the LTSSM value in the debugfs for the PCIe
>>> subsystem (which have an EP connected to it) came out to be 0x10, which
>>> points to the state "PCIE_L0". However, the debugfs prints the state as
>>> "POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
>>>
>>> The LTSSM state encodings for TI SoCs using Cadence PCIe IP is provided
>>> in the J7200 TRM section 12.2.3.4.14 at:
>>>
>https://urldefense.com/v3/__https://www.ti.com/lit/pdf/spruiu1__;!!EHscmS1
>>> ygiU1lA!AudWpZJoYT3_nfvc33jiZrUFh75KB4DU-
>>> na_9SNZTib3etI9BNC3Jq8RlPxVouCPY2Rt7SyqrNI$
>>>
>>> Regards,
>>> Aksh Garg
>>>
>>>
>>>> +
>>>>    struct cdns_pcie_ops {
>>>
>>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  6:11     ` Manikandan Karunakaran Pillai
  2026-05-13  6:39       ` Hans Zhang
@ 2026-05-13  8:34       ` Aksh Garg
  2026-05-13  8:55         ` Hans Zhang
  1 sibling, 1 reply; 19+ messages in thread
From: Aksh Garg @ 2026-05-13  8:34 UTC (permalink / raw)
  To: Manikandan Karunakaran Pillai, Hans Zhang, bhelgaas@google.com,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
	hans.zhang@cixtech.com
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli



On 13/05/26 11:41, Manikandan Karunakaran Pillai wrote:
>> On 08/05/26 09:11, Hans Zhang wrote:
>>> Add the debugfs property to provide a view of the current link's LTSSM
>>> status from the Root Port device.
>>>
>>> Test example:
>>>     # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
>>>     L0_STATE (0x29)
>>>
>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>> ---
>>>    Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
>>>    drivers/pci/controller/cadence/Kconfig        |   9 +
>>>    drivers/pci/controller/cadence/Makefile       |   1 +
>>>    drivers/pci/controller/cadence/pci-sky1.c     |   3 +
>>>    .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
>>>    .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
>>>    .../cadence/pcie-cadence-host-hpa.c           |  20 +-
>>>    .../controller/cadence/pcie-cadence-host.c    |   9 +-
>>>    drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
>>>    9 files changed, 406 insertions(+), 2 deletions(-)
>>>    create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>>>    create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c
>>>
>>> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie
>> b/Documentation/ABI/testing/debugfs-cdns-pcie
>>> new file mode 100644
>>> index 000000000000..659ad2ab70e4
>>> --- /dev/null
>>> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
>>> @@ -0,0 +1,5 @@
>>> +What:		/sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
>>> +Date:		March 2026
>>> +Contact:	Hans Zhang <18255117159@163.com>
>>> +Description:	(RO) Read will return the current PCIe LTSSM state in both
>>> +		string and raw value.
>>> diff --git a/drivers/pci/controller/cadence/Kconfig
>> b/drivers/pci/controller/cadence/Kconfig
>>> index 9e651d545973..cb010bc97aad 100644
>>> --- a/drivers/pci/controller/cadence/Kconfig
>>> +++ b/drivers/pci/controller/cadence/Kconfig
>>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>>>    config PCIE_CADENCE
>>>    	tristate
>>>
>>> +config PCIE_CADENCE_DEBUGFS
>>> +	tristate "Cadence PCIe debugfs entries"
>>> +	depends on DEBUG_FS
>>> +	depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
>>> +	help
>>> +	  Say Y here to enable debugfs entries for the PCIe controller. These
>>> +	  entries provide various debug features related to the controller and
>>> +	  the LTSSM status of link can be displayed.
>>> +
>>>    config PCIE_CADENCE_HOST
>>>    	tristate
>>>    	depends on OF
>>
>> [...]
>>
>>>
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
>> b/drivers/pci/controller/cadence/pcie-cadence.h
>>> index 9a464cbaf073..a1c531fd2061 100644
>>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>>> @@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
>>>    	REG_BANKS_MAX,
>>>    };
>>>
>>> +enum cdns_pcie_ltssm {
>>> +	CDNS_PCIE_LTSSM_DETECT_QUIET		= 0,
>>> +	CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY	= 1,
>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE		= 2,
>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_1		= 3,
>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_2		= 4,
>>> +	CDNS_PCIE_LTSSM_DETECT_ACTIVE_3		= 5,
>>> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_ST	= 6,
>>> +	CDNS_PCIE_LTSSM_RCVR_DETECTED_1		= 7,
>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE		= 8,
>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_1	= 9,
>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_2	= 10,
>>> +	CDNS_PCIE_LTSSM_POLLING_ACTIVE_3	= 11,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE	= 12,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1	= 13,
>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG		= 14,
>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_1	= 15,
>>> +	CDNS_PCIE_LTSSM_POLLING_CONFIG_2	= 16,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC	= 17,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1	= 18,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2	= 19,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC	= 20,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC	= 21,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC	= 23,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP	= 24,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1	= 25,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2	= 26,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP	= 27,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP	= 28,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP	= 30,
>>> +	CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1	= 31,
>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_1		= 32,
>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE		= 33,
>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1	= 34,
>>> +	CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2	= 35,
>>> +	CDNS_PCIE_LTSSM_CONFIG_IDLE		= 36,
>>> +	CDNS_PCIE_LTSSM_CONFIG_IDLE_1		= 37,
>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_2		= 38,
>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_3		= 39,
>>> +	CDNS_PCIE_LTSSM_DUMMY_STATE_4		= 40,
>>> +	CDNS_PCIE_LTSSM_L0_STATE		= 41,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK	= 42,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1	= 43,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG	= 44,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1	= 45,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE		= 46,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_IDLE_1		= 47,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK		= 48,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_1		= 49,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_2		= 50,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_3		= 51,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_4		= 52,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_5		= 53,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_6		= 54,
>>> +	CDNS_PCIE_LTSSM_DISABLE_LINK_7		= 55,
>>> +	CDNS_PCIE_LTSSM_HOT_RESET		= 56,
>>> +	CDNS_PCIE_LTSSM_HOT_RESET_1		= 57,
>>> +	CDNS_PCIE_LTSSM_HOT_RESET_2		= 58,
>>> +	CDNS_PCIE_LTSSM_HOT_RESET_3		= 59,
>>> +	CDNS_PCIE_LTSSM_L0S_ENTRY		= 60,
>>> +	CDNS_PCIE_LTSSM_L0S_1			= 61,
>>> +	CDNS_PCIE_LTSSM_L0S_2			= 62,
>>> +	CDNS_PCIE_LTSSM_L0S_3			= 63,
>>> +	CDNS_PCIE_LTSSM_L0S_4			= 64,
>>> +	CDNS_PCIE_LTSSM_L0S_5			= 65,
>>> +	CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX	= 66,
>>> +	CDNS_PCIE_LTSSM_TX_FTS_ENTRY		= 67,
>>> +	CDNS_PCIE_LTSSM_TX_FTS_1		= 68,
>>> +	CDNS_PCIE_LTSSM_TX_FTS_2		= 69,
>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST		= 70,
>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1		= 71,
>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2		= 72,
>>> +	CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3		= 73,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED		= 74,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_1	= 75,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_2	= 76,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_SPEED_3	= 77,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
>>> +	CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY	= 87,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1	= 89,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT	= 90,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1	= 91,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2	= 92,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3	= 93,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4	= 94,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5	= 95,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE	= 96,
>>> +	CDNS_PCIE_LTSSM_L1_ENTRY		= 97,
>>> +	CDNS_PCIE_LTSSM_L1_1			= 98,
>>> +	CDNS_PCIE_LTSSM_L1_2			= 99,
>>> +	CDNS_PCIE_LTSSM_L1_3			= 100,
>>> +	CDNS_PCIE_LTSSM_L1_4			= 101,
>>> +	CDNS_PCIE_LTSSM_L1_IDLE			= 102,
>>> +	CDNS_PCIE_LTSSM_L1_EXIT			= 103,
>>> +	CDNS_PCIE_LTSSM_L2_ENTRY		= 104,
>>> +	CDNS_PCIE_LTSSM_L2_1			= 105,
>>> +	CDNS_PCIE_LTSSM_L2_2			= 106,
>>> +	CDNS_PCIE_LTSSM_L2_3			= 107,
>>> +	CDNS_PCIE_LTSSM_L2_4			= 108,
>>> +	CDNS_PCIE_LTSSM_L2_5			= 109,
>>> +	CDNS_PCIE_LTSSM_L2_IDLE			= 110,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY	= 111,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1	= 112,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2	= 113,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3	= 114,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4	= 115,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5	= 116,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY =
>> 117,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE	= 118,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT	= 119,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1	= 120,
>>> +	CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2	= 121,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
>>> +	CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
>>> +};
>>
> 
> The above LTSSM states are internal LTSSM encoding states and may not be available for software to use.
> The LTSSM states in the document pointed by Aksh (TI Soc) are the states  available in all cadence controllers.

Is this true for HPA IPs as well? The test performed by Hans:
root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
L0_STATE (0x29)
L0_STATE (0x29)
L0_STATE (0x29)

This implies that the L0_STATE LTSSM state is mapped to 0x29 (41) there,
which according to your response is internal LTSSM encoding, and hence
the register read should have resulted in 0x10 instead of 0x29.


> 
>> Hi Hans,
>>
>> The LTSSM state encoding in your patches do not align with the state
>> encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
>> applied your patches, the LTSSM value in the debugfs for the PCIe
>> subsystem (which have an EP connected to it) came out to be 0x10, which
>> points to the state "PCIE_L0". However, the debugfs prints the state as
>> "POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
>>
>> The LTSSM state encodings for TI SoCs using Cadence PCIe IP is provided
>> in the J7200 TRM section 12.2.3.4.14 at:
>> https://urldefense.com/v3/__https://www.ti.com/lit/pdf/spruiu1__;!!EHscmS1
>> ygiU1lA!AudWpZJoYT3_nfvc33jiZrUFh75KB4DU-
>> na_9SNZTib3etI9BNC3Jq8RlPxVouCPY2Rt7SyqrNI$
>>
>> Regards,
>> Aksh Garg
>>
>>
>>> +
>>>    struct cdns_pcie_ops {
>>
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  8:34       ` Aksh Garg
@ 2026-05-13  8:55         ` Hans Zhang
  2026-05-13 11:30           ` Aksh Garg
  0 siblings, 1 reply; 19+ messages in thread
From: Hans Zhang @ 2026-05-13  8:55 UTC (permalink / raw)
  To: Aksh Garg, Manikandan Karunakaran Pillai, bhelgaas@google.com,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
	hans.zhang@cixtech.com
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli



On 5/13/26 16:34, Aksh Garg wrote:

>>>
>>
>> The above LTSSM states are internal LTSSM encoding states and may not 
>> be available for software to use.
>> The LTSSM states in the document pointed by Aksh (TI Soc) are the 
>> states  available in all cadence controllers.
> 
> Is this true for HPA IPs as well? The test performed by Hans:
> root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
> L0_STATE (0x29)
> L0_STATE (0x29)
> L0_STATE (0x29)
> 
> This implies that the L0_STATE LTSSM state is mapped to 0x29 (41) there,
> which according to your response is internal LTSSM encoding, and hence
> the register read should have resulted in 0x10 instead of 0x29.
> 

Hi Aksh,


For HPA, my view is similar to that of DWC - it requires a common 
internal LTSSM state. For each of its own Root Port drivers, a callback 
can be used to implement the reading of LTSSM. This part can be referred 
to as the implementation of the function in DWC.


static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
{
	u32 val;

	if (pci->ops && pci->ops->get_ltssm)
		return pci->ops->get_ltssm(pci);

	val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);

	return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val);
}


static int ltssm_status_show(struct seq_file *s, void *v)
{
	struct dw_pcie *pci = s->private;
	enum dw_pcie_ltssm val;

	val = dw_pcie_get_ltssm(pci);
	seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), val);

	return 0;
}



For example, it can be modified as follows. Of course, the function name 
will start with "cdns".

For LGA IP, currently we will allow each Root Port driver to implement 
the corresponding ops::get_ltssm() by itself.

static int ltssm_status_show(struct seq_file *s, void *v)
{
	struct dw_pcie *pci = s->private;
	enum dw_pcie_ltssm val;

	if (pci->ops && pci->ops->get_ltssm)
		val = pci->ops->get_ltssm(pci);
	else
		val = dw_pcie_get_ltssm(pci);
	seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), val);

	return 0;
}


Best regards,
Hans


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  8:55         ` Hans Zhang
@ 2026-05-13 11:30           ` Aksh Garg
  2026-05-13 12:04             ` Hans Zhang
  0 siblings, 1 reply; 19+ messages in thread
From: Aksh Garg @ 2026-05-13 11:30 UTC (permalink / raw)
  To: Hans Zhang, Manikandan Karunakaran Pillai, bhelgaas@google.com,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli



On 13/05/26 14:25, Hans Zhang wrote:
> 
> 
> On 5/13/26 16:34, Aksh Garg wrote:
> 
>>>>
>>>
>>> The above LTSSM states are internal LTSSM encoding states and may not 
>>> be available for software to use.
>>> The LTSSM states in the document pointed by Aksh (TI Soc) are the 
>>> states  available in all cadence controllers.
>>
>> Is this true for HPA IPs as well? The test performed by Hans:
>> root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
>> L0_STATE (0x29)
>> L0_STATE (0x29)
>> L0_STATE (0x29)
>>
>> This implies that the L0_STATE LTSSM state is mapped to 0x29 (41) there,
>> which according to your response is internal LTSSM encoding, and hence
>> the register read should have resulted in 0x10 instead of 0x29.
>>
> 
> Hi Aksh,
> 
> 
> For HPA, my view is similar to that of DWC - it requires a common 
> internal LTSSM state. For each of its own Root Port drivers, a callback 
> can be used to implement the reading of LTSSM. This part can be referred 
> to as the implementation of the function in DWC.
> 
> 
> static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
> {
>      u32 val;
> 
>      if (pci->ops && pci->ops->get_ltssm)
>          return pci->ops->get_ltssm(pci);
> 
>      val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
> 
>      return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, 
> val);
> }
> 
> 
> static int ltssm_status_show(struct seq_file *s, void *v)
> {
>      struct dw_pcie *pci = s->private;
>      enum dw_pcie_ltssm val;
> 
>      val = dw_pcie_get_ltssm(pci);
>      seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), val);
> 
>      return 0;
> }
> 
> 
> 
> For example, it can be modified as follows. Of course, the function name 
> will start with "cdns".
> 
> For LGA IP, currently we will allow each Root Port driver to implement 
> the corresponding ops::get_ltssm() by itself.
> 
> static int ltssm_status_show(struct seq_file *s, void *v)
> {
>      struct dw_pcie *pci = s->private;
>      enum dw_pcie_ltssm val;
> 
>      if (pci->ops && pci->ops->get_ltssm)
>          val = pci->ops->get_ltssm(pci);
>      else
>          val = dw_pcie_get_ltssm(pci);
>      seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), val);
> 
>      return 0;
> }
> 

The process above tells how to read the register and get the LTSSM
state values. However, my concern is whether we require different LTSSM
state encoding in your debugfs patch, one for LGA, and other for HPA.
This is because the L0_state seems to have different values in the LTSSM
fields of different IPs. On LGA, the L0_state seems to have value as
0x10 in the register (as can be seen in the J7200 TRM). On HPA, the
L0_state seems to have value of 0x29 in the register (as can be seen in
your test logs in the cover letter). Hence, if we want to print the
LTSSM state string in the debugfs, then for LGA IPs, 0x10 value should
print L0_STATE, and for HPA IPs, 0x41 value should print L0_state.

Please correct me if I am missing something here.

> 
> Best regards,
> Hans
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13 11:30           ` Aksh Garg
@ 2026-05-13 12:04             ` Hans Zhang
  2026-05-14  1:39               ` Manikandan Karunakaran Pillai
  0 siblings, 1 reply; 19+ messages in thread
From: Hans Zhang @ 2026-05-13 12:04 UTC (permalink / raw)
  To: Aksh Garg, Manikandan Karunakaran Pillai, bhelgaas@google.com,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli



On 5/13/26 19:30, Aksh Garg wrote:
> 
> 
> On 13/05/26 14:25, Hans Zhang wrote:
>>
>>
>> On 5/13/26 16:34, Aksh Garg wrote:
>>
>>>>>
>>>>
>>>> The above LTSSM states are internal LTSSM encoding states and may 
>>>> not be available for software to use.
>>>> The LTSSM states in the document pointed by Aksh (TI Soc) are the 
>>>> states  available in all cadence controllers.
>>>
>>> Is this true for HPA IPs as well? The test performed by Hans:
>>> root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
>>> L0_STATE (0x29)
>>> L0_STATE (0x29)
>>> L0_STATE (0x29)
>>>
>>> This implies that the L0_STATE LTSSM state is mapped to 0x29 (41) there,
>>> which according to your response is internal LTSSM encoding, and hence
>>> the register read should have resulted in 0x10 instead of 0x29.
>>>
>>
>> Hi Aksh,
>>
>>
>> For HPA, my view is similar to that of DWC - it requires a common 
>> internal LTSSM state. For each of its own Root Port drivers, a 
>> callback can be used to implement the reading of LTSSM. This part can 
>> be referred to as the implementation of the function in DWC.
>>
>>
>> static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
>> {
>>      u32 val;
>>
>>      if (pci->ops && pci->ops->get_ltssm)
>>          return pci->ops->get_ltssm(pci);
>>
>>      val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
>>
>>      return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, 
>> val);
>> }
>>
>>
>> static int ltssm_status_show(struct seq_file *s, void *v)
>> {
>>      struct dw_pcie *pci = s->private;
>>      enum dw_pcie_ltssm val;
>>
>>      val = dw_pcie_get_ltssm(pci);
>>      seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), 
>> val);
>>
>>      return 0;
>> }
>>
>>
>>
>> For example, it can be modified as follows. Of course, the function 
>> name will start with "cdns".
>>
>> For LGA IP, currently we will allow each Root Port driver to implement 
>> the corresponding ops::get_ltssm() by itself.
>>
>> static int ltssm_status_show(struct seq_file *s, void *v)
>> {
>>      struct dw_pcie *pci = s->private;
>>      enum dw_pcie_ltssm val;
>>
>>      if (pci->ops && pci->ops->get_ltssm)
>>          val = pci->ops->get_ltssm(pci);
>>      else
>>          val = dw_pcie_get_ltssm(pci);
>>      seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), 
>> val);
>>
>>      return 0;
>> }
>>
> 
> The process above tells how to read the register and get the LTSSM
> state values. However, my concern is whether we require different LTSSM
> state encoding in your debugfs patch, one for LGA, and other for HPA.
> This is because the L0_state seems to have different values in the LTSSM
> fields of different IPs. On LGA, the L0_state seems to have value as
> 0x10 in the register (as can be seen in the J7200 TRM). On HPA, the
> L0_state seems to have value of 0x29 in the register (as can be seen in
> your test logs in the cover letter). Hence, if we want to print the
> LTSSM state string in the debugfs, then for LGA IPs, 0x10 value should
> print L0_STATE, and for HPA IPs, 0x41 value should print L0_state.
> 

Hi Aksh,

Yes, different codes will be used. The reason for this was because of 
the result I obtained from consulting Manikandan. This time, it was a 
problem identified by Sashiko's review. So, we need to ask you and 
Manikandan to confirm this LTSSM code again.


Best regards,
Hans


^ permalink raw reply	[flat|nested] 19+ messages in thread

* RE: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13 12:04             ` Hans Zhang
@ 2026-05-14  1:39               ` Manikandan Karunakaran Pillai
  2026-05-14  1:46                 ` Hans Zhang
  0 siblings, 1 reply; 19+ messages in thread
From: Manikandan Karunakaran Pillai @ 2026-05-14  1:39 UTC (permalink / raw)
  To: Hans Zhang, Aksh Garg, bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli



>
>
>
>
>On 5/13/26 19:30, Aksh Garg wrote:
>>
>>
>> On 13/05/26 14:25, Hans Zhang wrote:
>>>
>>>
>>> On 5/13/26 16:34, Aksh Garg wrote:
>>>
>>>>>>
>>>>>
>>>>> The above LTSSM states are internal LTSSM encoding states and may
>>>>> not be available for software to use.
>>>>> The LTSSM states in the document pointed by Aksh (TI Soc) are the
>>>>> states  available in all cadence controllers.
>>>>
>>>> Is this true for HPA IPs as well? The test performed by Hans:
>>>> root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
>>>> L0_STATE (0x29)
>>>> L0_STATE (0x29)
>>>> L0_STATE (0x29)
>>>>
>>>> This implies that the L0_STATE LTSSM state is mapped to 0x29 (41) there,
>>>> which according to your response is internal LTSSM encoding, and hence
>>>> the register read should have resulted in 0x10 instead of 0x29.
>>>>
>>>
>>> Hi Aksh,
>>>
>>>
>>> For HPA, my view is similar to that of DWC - it requires a common
>>> internal LTSSM state. For each of its own Root Port drivers, a
>>> callback can be used to implement the reading of LTSSM. This part can
>>> be referred to as the implementation of the function in DWC.
>>>
>>>
>>> static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
>>> {
>>>      u32 val;
>>>
>>>      if (pci->ops && pci->ops->get_ltssm)
>>>          return pci->ops->get_ltssm(pci);
>>>
>>>      val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
>>>
>>>      return (enum
>dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK,
>>> val);
>>> }
>>>
>>>
>>> static int ltssm_status_show(struct seq_file *s, void *v)
>>> {
>>>      struct dw_pcie *pci = s->private;
>>>      enum dw_pcie_ltssm val;
>>>
>>>      val = dw_pcie_get_ltssm(pci);
>>>      seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val),
>>> val);
>>>
>>>      return 0;
>>> }
>>>
>>>
>>>
>>> For example, it can be modified as follows. Of course, the function
>>> name will start with "cdns".
>>>
>>> For LGA IP, currently we will allow each Root Port driver to implement
>>> the corresponding ops::get_ltssm() by itself.
>>>
>>> static int ltssm_status_show(struct seq_file *s, void *v)
>>> {
>>>      struct dw_pcie *pci = s->private;
>>>      enum dw_pcie_ltssm val;
>>>
>>>      if (pci->ops && pci->ops->get_ltssm)
>>>          val = pci->ops->get_ltssm(pci);
>>>      else
>>>          val = dw_pcie_get_ltssm(pci);
>>>      seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val),
>>> val);
>>>
>>>      return 0;
>>> }
>>>
>>
>> The process above tells how to read the register and get the LTSSM
>> state values. However, my concern is whether we require different LTSSM
>> state encoding in your debugfs patch, one for LGA, and other for HPA.
>> This is because the L0_state seems to have different values in the LTSSM
>> fields of different IPs. On LGA, the L0_state seems to have value as
>> 0x10 in the register (as can be seen in the J7200 TRM). On HPA, the
>> L0_state seems to have value of 0x29 in the register (as can be seen in
>> your test logs in the cover letter). Hence, if we want to print the
>> LTSSM state string in the debugfs, then for LGA IPs, 0x10 value should
>> print L0_STATE, and for HPA IPs, 0x41 value should print L0_state.
>>
>
>Hi Aksh,
>
>Yes, different codes will be used. The reason for this was because of
>the result I obtained from consulting Manikandan. This time, it was a
>problem identified by Sashiko's review. So, we need to ask you and
>Manikandan to confirm this LTSSM code again.
>
>
>Best regards,
>Hans

The LTSSM codes are the same across HPA and LGA. You have to refer to "External LTSSM state encoding" table in
the specification given by cadence.


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-14  1:39               ` Manikandan Karunakaran Pillai
@ 2026-05-14  1:46                 ` Hans Zhang
  2026-05-14  4:25                   ` Manikandan Karunakaran Pillai
  0 siblings, 1 reply; 19+ messages in thread
From: Hans Zhang @ 2026-05-14  1:46 UTC (permalink / raw)
  To: Manikandan Karunakaran Pillai, Aksh Garg, bhelgaas@google.com,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli



On 5/14/26 09:39, Manikandan Karunakaran Pillai wrote:
>>>> On 5/13/26 16:34, Aksh Garg wrote:
>>>>
>>>>>>>
>>>>>>
>>>>>> The above LTSSM states are internal LTSSM encoding states and may
>>>>>> not be available for software to use.
>>>>>> The LTSSM states in the document pointed by Aksh (TI Soc) are the
>>>>>> states  available in all cadence controllers.
>>>>>
>>>>> Is this true for HPA IPs as well? The test performed by Hans:
>>>>> root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
>>>>> L0_STATE (0x29)
>>>>> L0_STATE (0x29)
>>>>> L0_STATE (0x29)
>>>>>
>>>>> This implies that the L0_STATE LTSSM state is mapped to 0x29 (41) there,
>>>>> which according to your response is internal LTSSM encoding, and hence
>>>>> the register read should have resulted in 0x10 instead of 0x29.
>>>>>
>>>>
>>>> Hi Aksh,
>>>>
>>>>
>>>> For HPA, my view is similar to that of DWC - it requires a common
>>>> internal LTSSM state. For each of its own Root Port drivers, a
>>>> callback can be used to implement the reading of LTSSM. This part can
>>>> be referred to as the implementation of the function in DWC.
>>>>
>>>>
>>>> static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
>>>> {
>>>>       u32 val;
>>>>
>>>>       if (pci->ops && pci->ops->get_ltssm)
>>>>           return pci->ops->get_ltssm(pci);
>>>>
>>>>       val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
>>>>
>>>>       return (enum
>> dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK,
>>>> val);
>>>> }
>>>>
>>>>
>>>> static int ltssm_status_show(struct seq_file *s, void *v)
>>>> {
>>>>       struct dw_pcie *pci = s->private;
>>>>       enum dw_pcie_ltssm val;
>>>>
>>>>       val = dw_pcie_get_ltssm(pci);
>>>>       seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val),
>>>> val);
>>>>
>>>>       return 0;
>>>> }
>>>>
>>>>
>>>>
>>>> For example, it can be modified as follows. Of course, the function
>>>> name will start with "cdns".
>>>>
>>>> For LGA IP, currently we will allow each Root Port driver to implement
>>>> the corresponding ops::get_ltssm() by itself.
>>>>
>>>> static int ltssm_status_show(struct seq_file *s, void *v)
>>>> {
>>>>       struct dw_pcie *pci = s->private;
>>>>       enum dw_pcie_ltssm val;
>>>>
>>>>       if (pci->ops && pci->ops->get_ltssm)
>>>>           val = pci->ops->get_ltssm(pci);
>>>>       else
>>>>           val = dw_pcie_get_ltssm(pci);
>>>>       seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val),
>>>> val);
>>>>
>>>>       return 0;
>>>> }
>>>>
>>>
>>> The process above tells how to read the register and get the LTSSM
>>> state values. However, my concern is whether we require different LTSSM
>>> state encoding in your debugfs patch, one for LGA, and other for HPA.
>>> This is because the L0_state seems to have different values in the LTSSM
>>> fields of different IPs. On LGA, the L0_state seems to have value as
>>> 0x10 in the register (as can be seen in the J7200 TRM). On HPA, the
>>> L0_state seems to have value of 0x29 in the register (as can be seen in
>>> your test logs in the cover letter). Hence, if we want to print the
>>> LTSSM state string in the debugfs, then for LGA IPs, 0x10 value should
>>> print L0_STATE, and for HPA IPs, 0x41 value should print L0_state.
>>>
>>
>> Hi Aksh,
>>
>> Yes, different codes will be used. The reason for this was because of
>> the result I obtained from consulting Manikandan. This time, it was a
>> problem identified by Sashiko's review. So, we need to ask you and
>> Manikandan to confirm this LTSSM code again.
>>
>>
>> Best regards,
>> Hans
> 
> The LTSSM codes are the same across HPA and LGA. You have to refer to "External LTSSM state encoding" table in
> the specification given by cadence.
> 

Hi Manikandan,


Are there 128 different states? If they are the same, for the LGA IP, 
which register should I read?

Previously, Sashiko reported a problem with the review. Please click on 
the following link:

https://lore.kernel.org/linux-pci/20260508041956.C8F10C2BCB0@smtp.kernel.org/


"""
 > +#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK	GENMASK(29, 24)

Does this mask need to be extended to cover all possible states?

This mask covers only 6 bits, allowing it to extract values up to 63.
However, the cdns_pcie_ltssm enum defines states up to 127. If the
hardware enters a state 64 or higher, FIELD_GET will silently truncate
the value, making state 65 appear as state 1.

"""


Best regards,
Hans



^ permalink raw reply	[flat|nested] 19+ messages in thread

* RE: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-14  1:46                 ` Hans Zhang
@ 2026-05-14  4:25                   ` Manikandan Karunakaran Pillai
  0 siblings, 0 replies; 19+ messages in thread
From: Manikandan Karunakaran Pillai @ 2026-05-14  4:25 UTC (permalink / raw)
  To: Hans Zhang, Aksh Garg, bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org
  Cc: robh@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, Siddharth Vadapalli

Sorry for all the confusion. Just checked with design and the HPA has different states from the LGA controller in cadence.
The HPA has the 127 states where 0x29 is the L0_state. So as you mentioned, the codes will have to be different between the 
HPA and LGA controllers.

>EXTERNAL MAIL
>
>
>
>
>On 5/14/26 09:39, Manikandan Karunakaran Pillai wrote:
>>>>> On 5/13/26 16:34, Aksh Garg wrote:
>>>>>
>>>>>>>>
>>>>>>>
>>>>>>> The above LTSSM states are internal LTSSM encoding states and may
>>>>>>> not be available for software to use.
>>>>>>> The LTSSM states in the document pointed by Aksh (TI Soc) are the
>>>>>>> states  available in all cadence controllers.
>>>>>>
>>>>>> Is this true for HPA IPs as well? The test performed by Hans:
>>>>>> root@orangepi6plus:~# cat /sys/kernel/debug/cdns_pcie_a0*/ltss*
>>>>>> L0_STATE (0x29)
>>>>>> L0_STATE (0x29)
>>>>>> L0_STATE (0x29)
>>>>>>
>>>>>> This implies that the L0_STATE LTSSM state is mapped to 0x29 (41) there,
>>>>>> which according to your response is internal LTSSM encoding, and
>hence
>>>>>> the register read should have resulted in 0x10 instead of 0x29.
>>>>>>
>>>>>
>>>>> Hi Aksh,
>>>>>
>>>>>
>>>>> For HPA, my view is similar to that of DWC - it requires a common
>>>>> internal LTSSM state. For each of its own Root Port drivers, a
>>>>> callback can be used to implement the reading of LTSSM. This part can
>>>>> be referred to as the implementation of the function in DWC.
>>>>>
>>>>>
>>>>> static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
>>>>> {
>>>>>       u32 val;
>>>>>
>>>>>       if (pci->ops && pci->ops->get_ltssm)
>>>>>           return pci->ops->get_ltssm(pci);
>>>>>
>>>>>       val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
>>>>>
>>>>>       return (enum
>>> dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK,
>>>>> val);
>>>>> }
>>>>>
>>>>>
>>>>> static int ltssm_status_show(struct seq_file *s, void *v)
>>>>> {
>>>>>       struct dw_pcie *pci = s->private;
>>>>>       enum dw_pcie_ltssm val;
>>>>>
>>>>>       val = dw_pcie_get_ltssm(pci);
>>>>>       seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val),
>>>>> val);
>>>>>
>>>>>       return 0;
>>>>> }
>>>>>
>>>>>
>>>>>
>>>>> For example, it can be modified as follows. Of course, the function
>>>>> name will start with "cdns".
>>>>>
>>>>> For LGA IP, currently we will allow each Root Port driver to implement
>>>>> the corresponding ops::get_ltssm() by itself.
>>>>>
>>>>> static int ltssm_status_show(struct seq_file *s, void *v)
>>>>> {
>>>>>       struct dw_pcie *pci = s->private;
>>>>>       enum dw_pcie_ltssm val;
>>>>>
>>>>>       if (pci->ops && pci->ops->get_ltssm)
>>>>>           val = pci->ops->get_ltssm(pci);
>>>>>       else
>>>>>           val = dw_pcie_get_ltssm(pci);
>>>>>       seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val),
>>>>> val);
>>>>>
>>>>>       return 0;
>>>>> }
>>>>>
>>>>
>>>> The process above tells how to read the register and get the LTSSM
>>>> state values. However, my concern is whether we require different LTSSM
>>>> state encoding in your debugfs patch, one for LGA, and other for HPA.
>>>> This is because the L0_state seems to have different values in the LTSSM
>>>> fields of different IPs. On LGA, the L0_state seems to have value as
>>>> 0x10 in the register (as can be seen in the J7200 TRM). On HPA, the
>>>> L0_state seems to have value of 0x29 in the register (as can be seen in
>>>> your test logs in the cover letter). Hence, if we want to print the
>>>> LTSSM state string in the debugfs, then for LGA IPs, 0x10 value should
>>>> print L0_STATE, and for HPA IPs, 0x41 value should print L0_state.
>>>>
>>>
>>> Hi Aksh,
>>>
>>> Yes, different codes will be used. The reason for this was because of
>>> the result I obtained from consulting Manikandan. This time, it was a
>>> problem identified by Sashiko's review. So, we need to ask you and
>>> Manikandan to confirm this LTSSM code again.
>>>
>>>
>>> Best regards,
>>> Hans
>>
>> The LTSSM codes are the same across HPA and LGA. You have to refer to
>"External LTSSM state encoding" table in
>> the specification given by cadence.
>>
>
>Hi Manikandan,
>
>
>Are there 128 different states? If they are the same, for the LGA IP,
>which register should I read?
>
>Previously, Sashiko reported a problem with the review. Please click on
>the following link:
>
>https://urldefense.com/v3/__https://lore.kernel.org/linux-
>pci/20260508041956.C8F10C2BCB0@smtp.kernel.org/__;!!EHscmS1ygiU1lA!G
>U0U7Ef3eOobw7d7tpj9llgtGrgZdXwgWBd6BpVcZ-9F-KnuwY3gNqJor8iK-
>fPDWLaktvVvrk7QmTRGFSC9$
>
>
>"""
> > +#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK	GENMASK(29, 24)
>
>Does this mask need to be extended to cover all possible states?
>
>This mask covers only 6 bits, allowing it to extract values up to 63.
>However, the cdns_pcie_ltssm enum defines states up to 127. If the
>hardware enters a state 64 or higher, FIELD_GET will silently truncate
>the value, making state 65 appear as state 1.
>
>"""
>
>
>Best regards,
>Hans
>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  5:23   ` Aksh Garg
  2026-05-13  6:11     ` Manikandan Karunakaran Pillai
@ 2026-05-13  6:37     ` Hans Zhang
  2026-05-13  8:25       ` Aksh Garg
  1 sibling, 1 reply; 19+ messages in thread
From: Hans Zhang @ 2026-05-13  6:37 UTC (permalink / raw)
  To: Aksh Garg, bhelgaas, lpieralisi, kwilczynski, mani, hans.zhang
  Cc: robh, mpillai, linux-pci, linux-kernel, Siddharth Vadapalli



On 5/13/26 13:23, Aksh Garg wrote:
> 
> 
> On 08/05/26 09:11, Hans Zhang wrote:
>> Add the debugfs property to provide a view of the current link's LTSSM
>> status from the Root Port device.
>>
>> Test example:
>>    # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
>>    L0_STATE (0x29)
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> ---
>>   Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
>>   drivers/pci/controller/cadence/Kconfig        |   9 +
>>   drivers/pci/controller/cadence/Makefile       |   1 +
>>   drivers/pci/controller/cadence/pci-sky1.c     |   3 +
>>   .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
>>   .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
>>   .../cadence/pcie-cadence-host-hpa.c           |  20 +-
>>   .../controller/cadence/pcie-cadence-host.c    |   9 +-
>>   drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
>>   9 files changed, 406 insertions(+), 2 deletions(-)
>>   create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>>   create mode 100644 drivers/pci/controller/cadence/pcie-cadence- 
>> debugfs.c
>>
>> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/ 
>> Documentation/ABI/testing/debugfs-cdns-pcie
>> new file mode 100644
>> index 000000000000..659ad2ab70e4
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
>> @@ -0,0 +1,5 @@
>> +What:        /sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
>> +Date:        March 2026
>> +Contact:    Hans Zhang <18255117159@163.com>
>> +Description:    (RO) Read will return the current PCIe LTSSM state in 
>> both
>> +        string and raw value.
>> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/ 
>> controller/cadence/Kconfig
>> index 9e651d545973..cb010bc97aad 100644
>> --- a/drivers/pci/controller/cadence/Kconfig
>> +++ b/drivers/pci/controller/cadence/Kconfig
>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>>   config PCIE_CADENCE
>>       tristate
>> +config PCIE_CADENCE_DEBUGFS
>> +    tristate "Cadence PCIe debugfs entries"
>> +    depends on DEBUG_FS
>> +    depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
>> +    help
>> +      Say Y here to enable debugfs entries for the PCIe controller. 
>> These
>> +      entries provide various debug features related to the 
>> controller and
>> +      the LTSSM status of link can be displayed.
>> +
>>   config PCIE_CADENCE_HOST
>>       tristate
>>       depends on OF
> 
> [...]
> 
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/ 
>> pci/controller/cadence/pcie-cadence.h
>> index 9a464cbaf073..a1c531fd2061 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>> @@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
>>       REG_BANKS_MAX,
>>   };
>> +enum cdns_pcie_ltssm {
>> +    CDNS_PCIE_LTSSM_DETECT_QUIET        = 0,
>> +    CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY    = 1,
>> +    CDNS_PCIE_LTSSM_DETECT_ACTIVE        = 2,
>> +    CDNS_PCIE_LTSSM_DETECT_ACTIVE_1        = 3,
>> +    CDNS_PCIE_LTSSM_DETECT_ACTIVE_2        = 4,
>> +    CDNS_PCIE_LTSSM_DETECT_ACTIVE_3        = 5,
>> +    CDNS_PCIE_LTSSM_RCVR_DETECTED_ST    = 6,
>> +    CDNS_PCIE_LTSSM_RCVR_DETECTED_1        = 7,
>> +    CDNS_PCIE_LTSSM_POLLING_ACTIVE        = 8,
>> +    CDNS_PCIE_LTSSM_POLLING_ACTIVE_1    = 9,
>> +    CDNS_PCIE_LTSSM_POLLING_ACTIVE_2    = 10,
>> +    CDNS_PCIE_LTSSM_POLLING_ACTIVE_3    = 11,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE    = 12,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1    = 13,
>> +    CDNS_PCIE_LTSSM_POLLING_CONFIG        = 14,
>> +    CDNS_PCIE_LTSSM_POLLING_CONFIG_1    = 15,
>> +    CDNS_PCIE_LTSSM_POLLING_CONFIG_2    = 16,
>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_RC    = 17,
>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1    = 18,
>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2    = 19,
>> +    CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC    = 20,
>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC    = 21,
>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC    = 23,
>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_EP    = 24,
>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1    = 25,
>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2    = 26,
>> +    CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP    = 27,
>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP    = 28,
>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP    = 30,
>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1    = 31,
>> +    CDNS_PCIE_LTSSM_DUMMY_STATE_1        = 32,
>> +    CDNS_PCIE_LTSSM_CONFIG_COMPLETE        = 33,
>> +    CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1    = 34,
>> +    CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2    = 35,
>> +    CDNS_PCIE_LTSSM_CONFIG_IDLE        = 36,
>> +    CDNS_PCIE_LTSSM_CONFIG_IDLE_1        = 37,
>> +    CDNS_PCIE_LTSSM_DUMMY_STATE_2        = 38,
>> +    CDNS_PCIE_LTSSM_DUMMY_STATE_3        = 39,
>> +    CDNS_PCIE_LTSSM_DUMMY_STATE_4        = 40,
>> +    CDNS_PCIE_LTSSM_L0_STATE        = 41,
>> +    CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK    = 42,
>> +    CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1    = 43,
>> +    CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG    = 44,
>> +    CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1    = 45,
>> +    CDNS_PCIE_LTSSM_RECOVERY_IDLE        = 46,
>> +    CDNS_PCIE_LTSSM_RECOVERY_IDLE_1        = 47,
>> +    CDNS_PCIE_LTSSM_DISABLE_LINK        = 48,
>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_1        = 49,
>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_2        = 50,
>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_3        = 51,
>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_4        = 52,
>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_5        = 53,
>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_6        = 54,
>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_7        = 55,
>> +    CDNS_PCIE_LTSSM_HOT_RESET        = 56,
>> +    CDNS_PCIE_LTSSM_HOT_RESET_1        = 57,
>> +    CDNS_PCIE_LTSSM_HOT_RESET_2        = 58,
>> +    CDNS_PCIE_LTSSM_HOT_RESET_3        = 59,
>> +    CDNS_PCIE_LTSSM_L0S_ENTRY        = 60,
>> +    CDNS_PCIE_LTSSM_L0S_1            = 61,
>> +    CDNS_PCIE_LTSSM_L0S_2            = 62,
>> +    CDNS_PCIE_LTSSM_L0S_3            = 63,
>> +    CDNS_PCIE_LTSSM_L0S_4            = 64,
>> +    CDNS_PCIE_LTSSM_L0S_5            = 65,
>> +    CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX    = 66,
>> +    CDNS_PCIE_LTSSM_TX_FTS_ENTRY        = 67,
>> +    CDNS_PCIE_LTSSM_TX_FTS_1        = 68,
>> +    CDNS_PCIE_LTSSM_TX_FTS_2        = 69,
>> +    CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST        = 70,
>> +    CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1        = 71,
>> +    CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2        = 72,
>> +    CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3        = 73,
>> +    CDNS_PCIE_LTSSM_RECOVERY_SPEED        = 74,
>> +    CDNS_PCIE_LTSSM_RECOVERY_SPEED_1    = 75,
>> +    CDNS_PCIE_LTSSM_RECOVERY_SPEED_2    = 76,
>> +    CDNS_PCIE_LTSSM_RECOVERY_SPEED_3    = 77,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY    = 87,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1    = 89,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT    = 90,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1    = 91,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2    = 92,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3    = 93,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4    = 94,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5    = 95,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE    = 96,
>> +    CDNS_PCIE_LTSSM_L1_ENTRY        = 97,
>> +    CDNS_PCIE_LTSSM_L1_1            = 98,
>> +    CDNS_PCIE_LTSSM_L1_2            = 99,
>> +    CDNS_PCIE_LTSSM_L1_3            = 100,
>> +    CDNS_PCIE_LTSSM_L1_4            = 101,
>> +    CDNS_PCIE_LTSSM_L1_IDLE            = 102,
>> +    CDNS_PCIE_LTSSM_L1_EXIT            = 103,
>> +    CDNS_PCIE_LTSSM_L2_ENTRY        = 104,
>> +    CDNS_PCIE_LTSSM_L2_1            = 105,
>> +    CDNS_PCIE_LTSSM_L2_2            = 106,
>> +    CDNS_PCIE_LTSSM_L2_3            = 107,
>> +    CDNS_PCIE_LTSSM_L2_4            = 108,
>> +    CDNS_PCIE_LTSSM_L2_5            = 109,
>> +    CDNS_PCIE_LTSSM_L2_IDLE            = 110,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY    = 111,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1    = 112,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2    = 113,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3    = 114,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4    = 115,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5    = 116,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY = 117,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE    = 118,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT    = 119,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1    = 120,
>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2    = 121,
>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
>> +};
> 
> Hi Hans,
> 
> The LTSSM state encoding in your patches do not align with the state 
> encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
> applied your patches, the LTSSM value in the debugfs for the PCIe
> subsystem (which have an EP connected to it) came out to be 0x10, which
> points to the state "PCIE_L0". However, the debugfs prints the state as
> "POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
> 
> The LTSSM state encodings for TI SoCs using Cadence PCIe IP is provided 
> in the J7200 TRM section 12.2.3.4.14 at:
> https://www.ti.com/lit/pdf/spruiu1

Hi Aksh,

Thank you for the information you provided. Could you please tell me how 
to read this register? Then I will incorporate it into the next version.

Best regards,
Hans

> 
> Regards,
> Aksh Garg
> 
> 
>> +
>>   struct cdns_pcie_ops {
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  6:37     ` Hans Zhang
@ 2026-05-13  8:25       ` Aksh Garg
  2026-05-13  8:29         ` Hans Zhang
  0 siblings, 1 reply; 19+ messages in thread
From: Aksh Garg @ 2026-05-13  8:25 UTC (permalink / raw)
  To: Hans Zhang, bhelgaas, lpieralisi, kwilczynski, mani, hans.zhang
  Cc: robh, mpillai, linux-pci, linux-kernel, Siddharth Vadapalli



On 13/05/26 12:07, Hans Zhang wrote:
> 
> 
> On 5/13/26 13:23, Aksh Garg wrote:
>>
>>
>> On 08/05/26 09:11, Hans Zhang wrote:
>>> Add the debugfs property to provide a view of the current link's LTSSM
>>> status from the Root Port device.
>>>
>>> Test example:
>>>    # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status
>>>    L0_STATE (0x29)
>>>
>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>> ---
>>>   Documentation/ABI/testing/debugfs-cdns-pcie   |   5 +
>>>   drivers/pci/controller/cadence/Kconfig        |   9 +
>>>   drivers/pci/controller/cadence/Makefile       |   1 +
>>>   drivers/pci/controller/cadence/pci-sky1.c     |   3 +
>>>   .../controller/cadence/pcie-cadence-debugfs.c | 208 ++++++++++++++++++
>>>   .../pci/controller/cadence/pcie-cadence-ep.c  |   3 +
>>>   .../cadence/pcie-cadence-host-hpa.c           |  20 +-
>>>   .../controller/cadence/pcie-cadence-host.c    |   9 +-
>>>   drivers/pci/controller/cadence/pcie-cadence.h | 150 +++++++++++++
>>>   9 files changed, 406 insertions(+), 2 deletions(-)
>>>   create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie
>>>   create mode 100644 drivers/pci/controller/cadence/pcie-cadence- 
>>> debugfs.c
>>>
>>> diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/ 
>>> Documentation/ABI/testing/debugfs-cdns-pcie
>>> new file mode 100644
>>> index 000000000000..659ad2ab70e4
>>> --- /dev/null
>>> +++ b/Documentation/ABI/testing/debugfs-cdns-pcie
>>> @@ -0,0 +1,5 @@
>>> +What:        /sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
>>> +Date:        March 2026
>>> +Contact:    Hans Zhang <18255117159@163.com>
>>> +Description:    (RO) Read will return the current PCIe LTSSM state 
>>> in both
>>> +        string and raw value.
>>> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/ 
>>> controller/cadence/Kconfig
>>> index 9e651d545973..cb010bc97aad 100644
>>> --- a/drivers/pci/controller/cadence/Kconfig
>>> +++ b/drivers/pci/controller/cadence/Kconfig
>>> @@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
>>>   config PCIE_CADENCE
>>>       tristate
>>> +config PCIE_CADENCE_DEBUGFS
>>> +    tristate "Cadence PCIe debugfs entries"
>>> +    depends on DEBUG_FS
>>> +    depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
>>> +    help
>>> +      Say Y here to enable debugfs entries for the PCIe controller. 
>>> These
>>> +      entries provide various debug features related to the 
>>> controller and
>>> +      the LTSSM status of link can be displayed.
>>> +
>>>   config PCIE_CADENCE_HOST
>>>       tristate
>>>       depends on OF
>>
>> [...]
>>
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/ 
>>> pci/controller/cadence/pcie-cadence.h
>>> index 9a464cbaf073..a1c531fd2061 100644
>>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>>> @@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {
>>>       REG_BANKS_MAX,
>>>   };
>>> +enum cdns_pcie_ltssm {
>>> +    CDNS_PCIE_LTSSM_DETECT_QUIET        = 0,
>>> +    CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY    = 1,
>>> +    CDNS_PCIE_LTSSM_DETECT_ACTIVE        = 2,
>>> +    CDNS_PCIE_LTSSM_DETECT_ACTIVE_1        = 3,
>>> +    CDNS_PCIE_LTSSM_DETECT_ACTIVE_2        = 4,
>>> +    CDNS_PCIE_LTSSM_DETECT_ACTIVE_3        = 5,
>>> +    CDNS_PCIE_LTSSM_RCVR_DETECTED_ST    = 6,
>>> +    CDNS_PCIE_LTSSM_RCVR_DETECTED_1        = 7,
>>> +    CDNS_PCIE_LTSSM_POLLING_ACTIVE        = 8,
>>> +    CDNS_PCIE_LTSSM_POLLING_ACTIVE_1    = 9,
>>> +    CDNS_PCIE_LTSSM_POLLING_ACTIVE_2    = 10,
>>> +    CDNS_PCIE_LTSSM_POLLING_ACTIVE_3    = 11,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE    = 12,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1    = 13,
>>> +    CDNS_PCIE_LTSSM_POLLING_CONFIG        = 14,
>>> +    CDNS_PCIE_LTSSM_POLLING_CONFIG_1    = 15,
>>> +    CDNS_PCIE_LTSSM_POLLING_CONFIG_2    = 16,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_RC    = 17,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1    = 18,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2    = 19,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC    = 20,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC    = 21,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC    = 23,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_EP    = 24,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1    = 25,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2    = 26,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP    = 27,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP    = 28,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP    = 30,
>>> +    CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1    = 31,
>>> +    CDNS_PCIE_LTSSM_DUMMY_STATE_1        = 32,
>>> +    CDNS_PCIE_LTSSM_CONFIG_COMPLETE        = 33,
>>> +    CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1    = 34,
>>> +    CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2    = 35,
>>> +    CDNS_PCIE_LTSSM_CONFIG_IDLE        = 36,
>>> +    CDNS_PCIE_LTSSM_CONFIG_IDLE_1        = 37,
>>> +    CDNS_PCIE_LTSSM_DUMMY_STATE_2        = 38,
>>> +    CDNS_PCIE_LTSSM_DUMMY_STATE_3        = 39,
>>> +    CDNS_PCIE_LTSSM_DUMMY_STATE_4        = 40,
>>> +    CDNS_PCIE_LTSSM_L0_STATE        = 41,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK    = 42,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1    = 43,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG    = 44,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1    = 45,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_IDLE        = 46,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_IDLE_1        = 47,
>>> +    CDNS_PCIE_LTSSM_DISABLE_LINK        = 48,
>>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_1        = 49,
>>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_2        = 50,
>>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_3        = 51,
>>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_4        = 52,
>>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_5        = 53,
>>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_6        = 54,
>>> +    CDNS_PCIE_LTSSM_DISABLE_LINK_7        = 55,
>>> +    CDNS_PCIE_LTSSM_HOT_RESET        = 56,
>>> +    CDNS_PCIE_LTSSM_HOT_RESET_1        = 57,
>>> +    CDNS_PCIE_LTSSM_HOT_RESET_2        = 58,
>>> +    CDNS_PCIE_LTSSM_HOT_RESET_3        = 59,
>>> +    CDNS_PCIE_LTSSM_L0S_ENTRY        = 60,
>>> +    CDNS_PCIE_LTSSM_L0S_1            = 61,
>>> +    CDNS_PCIE_LTSSM_L0S_2            = 62,
>>> +    CDNS_PCIE_LTSSM_L0S_3            = 63,
>>> +    CDNS_PCIE_LTSSM_L0S_4            = 64,
>>> +    CDNS_PCIE_LTSSM_L0S_5            = 65,
>>> +    CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX    = 66,
>>> +    CDNS_PCIE_LTSSM_TX_FTS_ENTRY        = 67,
>>> +    CDNS_PCIE_LTSSM_TX_FTS_1        = 68,
>>> +    CDNS_PCIE_LTSSM_TX_FTS_2        = 69,
>>> +    CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST        = 70,
>>> +    CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1        = 71,
>>> +    CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2        = 72,
>>> +    CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3        = 73,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_SPEED        = 74,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_SPEED_1    = 75,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_SPEED_2    = 76,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_SPEED_3    = 77,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
>>> +    CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY    = 87,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1    = 89,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT    = 90,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1    = 91,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2    = 92,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3    = 93,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4    = 94,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5    = 95,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE    = 96,
>>> +    CDNS_PCIE_LTSSM_L1_ENTRY        = 97,
>>> +    CDNS_PCIE_LTSSM_L1_1            = 98,
>>> +    CDNS_PCIE_LTSSM_L1_2            = 99,
>>> +    CDNS_PCIE_LTSSM_L1_3            = 100,
>>> +    CDNS_PCIE_LTSSM_L1_4            = 101,
>>> +    CDNS_PCIE_LTSSM_L1_IDLE            = 102,
>>> +    CDNS_PCIE_LTSSM_L1_EXIT            = 103,
>>> +    CDNS_PCIE_LTSSM_L2_ENTRY        = 104,
>>> +    CDNS_PCIE_LTSSM_L2_1            = 105,
>>> +    CDNS_PCIE_LTSSM_L2_2            = 106,
>>> +    CDNS_PCIE_LTSSM_L2_3            = 107,
>>> +    CDNS_PCIE_LTSSM_L2_4            = 108,
>>> +    CDNS_PCIE_LTSSM_L2_5            = 109,
>>> +    CDNS_PCIE_LTSSM_L2_IDLE            = 110,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY    = 111,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1    = 112,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2    = 113,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3    = 114,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4    = 115,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5    = 116,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY = 117,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE    = 118,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT    = 119,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1    = 120,
>>> +    CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2    = 121,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
>>> +    CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
>>> +};
>>
>> Hi Hans,
>>
>> The LTSSM state encoding in your patches do not align with the state 
>> encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
>> applied your patches, the LTSSM value in the debugfs for the PCIe
>> subsystem (which have an EP connected to it) came out to be 0x10, which
>> points to the state "PCIE_L0". However, the debugfs prints the state as
>> "POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
>>
>> The LTSSM state encodings for TI SoCs using Cadence PCIe IP is 
>> provided in the J7200 TRM section 12.2.3.4.14 at:
>> https://www.ti.com/lit/pdf/spruiu1
> 
> Hi Aksh,
> 
> Thank you for the information you provided. Could you please tell me how 
> to read this register? Then I will incorporate it into the next version.

The code to read the LTSSM state for LGA IPs in your patch:
```
reg = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, reg);
```
correctly reads the LTSSM state for TI SoCs which uses LGA IP.

> 
> Best regards,
> Hans
> 
>>
>> Regards,
>> Aksh Garg
>>
>>
>>> +
>>>   struct cdns_pcie_ops {
>>
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link
  2026-05-13  8:25       ` Aksh Garg
@ 2026-05-13  8:29         ` Hans Zhang
  0 siblings, 0 replies; 19+ messages in thread
From: Hans Zhang @ 2026-05-13  8:29 UTC (permalink / raw)
  To: Aksh Garg, bhelgaas, lpieralisi, kwilczynski, mani, hans.zhang
  Cc: robh, mpillai, linux-pci, linux-kernel, Siddharth Vadapalli



On 5/13/26 16:25, Aksh Garg wrote:
>>> Hi Hans,
>>>
>>> The LTSSM state encoding in your patches do not align with the state 
>>> encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
>>> applied your patches, the LTSSM value in the debugfs for the PCIe
>>> subsystem (which have an EP connected to it) came out to be 0x10, which
>>> points to the state "PCIE_L0". However, the debugfs prints the state as
>>> "POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
>>>
>>> The LTSSM state encodings for TI SoCs using Cadence PCIe IP is 
>>> provided in the J7200 TRM section 12.2.3.4.14 at:
>>> https://www.ti.com/lit/pdf/spruiu1
>>
>> Hi Aksh,
>>
>> Thank you for the information you provided. Could you please tell me 
>> how to read this register? Then I will incorporate it into the next 
>> version.
> 
> The code to read the LTSSM state for LGA IPs in your patch:
> ```
> reg = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
> ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, reg);
> ```
> correctly reads the LTSSM state for TI SoCs which uses LGA IP.

Hi Aksh,


Thank you.


Best regards,
Hans


^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2026-05-14  4:25 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-08  3:40 [PATCH v4 0/2] PCI: cadence: Add LTSSM debugfs Hans Zhang
2026-05-08  3:41 ` [PATCH v4 1/2] PCI: cadence: Add HPA architecture flag Hans Zhang
2026-05-08  3:41 ` [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link Hans Zhang
2026-05-08  4:19   ` sashiko-bot
2026-05-08  4:31     ` Hans Zhang
2026-05-13  5:23   ` Aksh Garg
2026-05-13  6:11     ` Manikandan Karunakaran Pillai
2026-05-13  6:39       ` Hans Zhang
2026-05-13  7:08         ` Manikandan Karunakaran Pillai
2026-05-13  8:34       ` Aksh Garg
2026-05-13  8:55         ` Hans Zhang
2026-05-13 11:30           ` Aksh Garg
2026-05-13 12:04             ` Hans Zhang
2026-05-14  1:39               ` Manikandan Karunakaran Pillai
2026-05-14  1:46                 ` Hans Zhang
2026-05-14  4:25                   ` Manikandan Karunakaran Pillai
2026-05-13  6:37     ` Hans Zhang
2026-05-13  8:25       ` Aksh Garg
2026-05-13  8:29         ` Hans Zhang

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox