[PATCH v12 0/4] Add PCIe support for Qualcomm IPQ5332

[PATCH v12 0/4] Add PCIe support for Qualcomm IPQ5332

[Varadarajan Narayanan]

Patch series adds support for enabling the PCIe controller and
UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and
PCIe1 is Gen3 X2 are added.

This series combines [1] and [2]. [1] introduces IPQ5018 PCIe
support and [2] depends on [1] to introduce IPQ5332 PCIe support.
Since the community was interested in [2] (please see [3]), tried
to revive IPQ5332's PCIe support with v2 of this patch series.

v2 of this series pulled in the phy driver from [1] tried to
address comments/feedback given in both [1] and [2].

1. Enable IPQ5018 PCI support (Nitheesh Sekar) - https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/
2. Add PCIe support for Qualcomm IPQ5332 (Praveenkumar I) - https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/
3. Community interest - https://lore.kernel.org/linux-arm-msm/20240310132915.GE3390@thinkpad/

v12: * Skipped the following (Vinod Koul has picked them)
		dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
		phy: qcom: Introduce PCIe UNIPHY 28LP driver

     * Skipped this (merged)
		dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller

     * Undo combining sdx55 & ipq9574. Discard the following
		dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
		arm64: dts: qcom: ipq9574: Reorder reg and reg-names

     * Append MHI registers to ipq9574 dt-bindings and dts
		dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
		arm64: dts: qcom: ipq9574: Add MHI to pcie nodes

     * ipq5332.dtsi:
		Align reg-names order with ipq9574
		Dropped R-b tag per feedback

     * No new warnings/errors with dt_binding_check and dtbs_check

v11: * phy-qcom-uniphy-pcie-28lp.c
	 * Remove unused #define
	 * Use "250 * MEGA" instead of 250000000

v10: * ipq5332.dtsi: Trim down the list of assigned clocks

     * ipq9574 and ipq5332 DT
	 * Fix 'simple-bus unit address format error' in ipq9574 and
	   ipq5332 DTS
         * Rearrange nodes w.r.t. address sort order

     * Have spoken with 'Manikanta Mylavarapu' [1] for omitting similar
       changes in qcom,pcie.yaml that are handled in this series.

     * Reformat commit messages to 75 character limit

     * controller bindings:
       Fix maxItems for interrupts constraint of sdm845

     1 - https://lore.kernel.org/linux-arm-msm/20250125035920.2651972-2-quic_mmanikan@quicinc.com/

v9: Dont have fallback for num-lanes in driver and return error
    Remove superfluous ipq5332 constraint as the fallback is present

v8: Add reviewed by
    Remove duplication in bindings due to ipq5424 code getting merged

v7: phy bindings:
    * Include data type definition to 'num-lanes'

    controller bindings:
    * Split the ipq9574 and ipq5332 changes into separate patches

    dtsi:
    * Add root port definitions

v6: phy bindings:
    * Fix num-lanes definition

    phy driver:
    * Fix num-lanes handling in probe to use generally followed pattern

    controller bindings:
    * Give more info in commit log

    dtsi:
    * Add assigned-clocks & assigned-clock-rates to controller nodes
    * Add num-lanes to pcie0_phy

v5: phy bindings:
    * Drop '3x1' & '3x2' from compatible string
    * Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
      in compatible string
    * Describe clocks and resets instead of just maxItems

    phy driver:
    * Get num-lanes from DTS
    * Drop compatible specific init data as there is only one
      compatible string

    controller bindings:
    * Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts

    dtsi:
    * Add 'num-lanes' to "pcie1_phy: phy@4b1000"
    * Make ipq5332 as main and ipq9574 as fallback compatible
    * Sort controller nodes per address

    misc:
    Add R-B tag from Konrad to dts and dtsi patches

v4: * phy bindings - Create ipq5332 compatible instead of reusing ipq9574 for bindings
    * phy bindings - Remove reset-names as the resets are handled with bulk APIs
    * phy bindings - Fix order in the 'required' section
    * phy bindings - Remove clock-output-names
    * dtsi - Add missing reset for pcie1_phy
    * dtsi - Convert 'reg-names' to a vertical list
    * dts - Fix nodes sort order
    * dts - Use property-n followed by property-names

v3: * Update the cover letter with the sources of the patches
    * Rename the dt-bindings yaml file similar to other phys
    * Drop ipq5332 specific pcie controllor bindings and reuse
      ipq9574 pcie controller bindings for ipq5332
    * Please see patches for specific changes
    * Set GPL license for phy-qcom-uniphy-pcie-28lp.c

v2: Address review comments from V1
    Drop the 'required clocks' change that would break ABI (in dt-binding, dts, gcc-ipq5332.c)
    Include phy driver from the dependent series

v1: https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/


Praveenkumar I (2):
  arm64: dts: qcom: ipq5332: Add PCIe related nodes
  arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers

Varadarajan Narayanan (2):
  dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
  arm64: dts: qcom: ipq9574: Add MHI to pcie nodes

 .../devicetree/bindings/pci/qcom,pcie.yaml    |   3 +-
 arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts   |  76 ++++++
 arch/arm64/boot/dts/qcom/ipq5332.dtsi         | 252 +++++++++++++++++-
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         |  40 ++-
 4 files changed, 360 insertions(+), 11 deletions(-)


base-commit: eea255893718268e1ab852fb52f70c613d109b99
prerequisite-patch-id: 56fe29d9207ac31ab08ca54712adc2a865b7be89
prerequisite-patch-id: f50f4b13ea072aea4beae5d5ecaf62336d9d2a31
-- 
2.34.1

[PATCH v12 1/4] dt-bindings: PCI: qcom: Add MHI registers for IPQ9574

[Varadarajan Narayanan]

Append the MHI register range to IPQ9574.

Fixes: e0662dae178d ("dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller")
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
New patch introduced in this patchset. MHI range was missed in the
initial post
---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 8f628939209e..77e66ab8764f 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -175,7 +175,7 @@ allOf:
       properties:
         reg:
           minItems: 5
-          maxItems: 5
+          maxItems: 6
         reg-names:
           items:
             - const: dbi # DesignWare PCIe registers
@@ -183,6 +183,7 @@ allOf:
             - const: atu # ATU address space
             - const: parf # Qualcomm specific registers
             - const: config # PCIe configuration space
+            - const: mhi # MHI registers
 
   - if:
       properties:
-- 
2.34.1

[PATCH v12 2/4] arm64: dts: qcom: ipq9574: Add MHI to pcie nodes

[Varadarajan Narayanan]

Append the MHI range to the pcie nodes. Convert reg-names to vertical
list.

Fixes: d80c7fbfa908 ("arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes")
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
New patch introduced in this patchset. MHI range was missed in the
initial post
---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 40 +++++++++++++++++++++------
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index cac58352182e..c27b3a90bd96 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -880,8 +880,14 @@ pcie1: pcie@10000000 {
 			      <0x10000f20 0xa8>,
 			      <0x10001000 0x1000>,
 			      <0x000f8000 0x4000>,
-			      <0x10100000 0x1000>;
-			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			      <0x10100000 0x1000>,
+			      <0x000fe000 0x1000>;
+			reg-names = "dbi",
+				    "elbi",
+				    "atu",
+				    "parf",
+				    "config",
+				    "mhi";
 			device_type = "pci";
 			linux,pci-domain = <1>;
 			bus-range = <0x00 0xff>;
@@ -960,8 +966,14 @@ pcie3: pcie@18000000 {
 			      <0x18000f20 0xa8>,
 			      <0x18001000 0x1000>,
 			      <0x000f0000 0x4000>,
-			      <0x18100000 0x1000>;
-			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			      <0x18100000 0x1000>,
+			      <0x000f6000 0x1000>;
+			reg-names = "dbi",
+				    "elbi",
+				    "atu",
+				    "parf",
+				    "config",
+				    "mhi";
 			device_type = "pci";
 			linux,pci-domain = <3>;
 			bus-range = <0x00 0xff>;
@@ -1040,8 +1052,14 @@ pcie2: pcie@20000000 {
 			      <0x20000f20 0xa8>,
 			      <0x20001000 0x1000>,
 			      <0x00088000 0x4000>,
-			      <0x20100000 0x1000>;
-			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			      <0x20100000 0x1000>,
+			      <0x0008e000 0x1000>;
+			reg-names = "dbi",
+				    "elbi",
+				    "atu",
+				    "parf",
+				    "config",
+				    "mhi";
 			device_type = "pci";
 			linux,pci-domain = <2>;
 			bus-range = <0x00 0xff>;
@@ -1120,8 +1138,14 @@ pcie0: pci@28000000 {
 			      <0x28000f20 0xa8>,
 			      <0x28001000 0x1000>,
 			      <0x00080000 0x4000>,
-			      <0x28100000 0x1000>;
-			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			      <0x28100000 0x1000>,
+			      <0x00086000 0x1000>;
+			reg-names = "dbi",
+				    "elbi",
+				    "atu",
+				    "parf",
+				    "config",
+				    "mhi";
 			device_type = "pci";
 			linux,pci-domain = <0>;
 			bus-range = <0x00 0xff>;
-- 
2.34.1

[PATCH v12 3/4] arm64: dts: qcom: ipq5332: Add PCIe related nodes

[Varadarajan Narayanan]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Add phy and controller nodes for pcie0_x1 and pcie1_x2.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v11: Drop Reviewed-by per feedback
     Use ipq9574 reg-names order and accordingly update the address in pcie@xxx
     Fix dbi reg size 0xf1d -> 0xf1c

v10: Trim down the list of assigned clocks
     Fix arch/arm64/boot/dts/qcom/ipq5332.dtsi:627.24-729.5: Warning (simple_bus_reg): /soc@0/pcie@20000000: simple-bus unit address format error, expected "80000"
     Rearrange nodes w.r.t. address sort order

v7: * Fix IO 'ranges' entry
    * Add root port definitions
    * Not adding 'dma-coherent' as the controller doesn't have that support
    * Remove 'bus-range' as it has default values
    * Group root complex related entries and root port related entries
      separately

v6: * Add 'num-lanes' to "pcie0_phy: phy@4b0000"
    * Earlier, some related clock rates were set in U-Boot. In
      recent versions of U-Boot this has been removed resulting
      in the phy link not coming up. To remove boot loader
      dependency add assigned-clocks and assigned-clock-rates to
      the controller nodes.
    * Not sure if 'Reviewed-by' should be dropped.

v5: Add 'num-lanes' to "pcie1_phy: phy@4b1000"
    Make ipq5332 as main and ipq9574 as fallback compatible
    Move controller nodes per address
    Having Konrad's Reviewed-By

v4: Remove 'reset-names' as driver uses bulk APIs
    Remove 'clock-output-names' as driver uses bulk APIs
    Add missing reset for pcie1_phy
    Convert 'reg-names' to a vertical list
    Move 'msi-map' before interrupts

v3: Fix compatible string for phy nodes
    Use ipq9574 as backup compatible instead of new compatible for ipq5332
    Fix mixed case hex addresses
    Add "mhi" space
    Removed unnecessary comments and stray blank lines

v2: Fix nodes' location per address
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 252 +++++++++++++++++++++++++-
 1 file changed, 250 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 69dda757925d..bd28c490415f 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -252,6 +252,46 @@ tsens: thermal-sensor@4a9000 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		pcie0_phy: phy@4b0000 {
+			compatible = "qcom,ipq5332-uniphy-pcie-phy";
+			reg = <0x004b0000 0x800>;
+
+			clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+				 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+			resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+				 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+				 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			num-lanes = <1>;
+
+			status = "disabled";
+		};
+
+		pcie1_phy: phy@4b1000 {
+			compatible = "qcom,ipq5332-uniphy-pcie-phy";
+			reg = <0x004b1000 0x1000>;
+
+			clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
+				 <&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
+
+			resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
+				 <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>,
+				 <&gcc GCC_PCIE3X2PHY_PHY_BCR>;
+
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			num-lanes = <2>;
+
+			status = "disabled";
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq5332-tlmm";
 			reg = <0x01000000 0x300000>;
@@ -278,8 +318,8 @@ gcc: clock-controller@1800000 {
 			#interconnect-cells = <1>;
 			clocks = <&xo_board>,
 				 <&sleep_clk>,
-				 <0>,
-				 <0>,
+				 <&pcie1_phy>,
+				 <&pcie0_phy>,
 				 <0>;
 		};
 
@@ -545,6 +585,214 @@ frame@b128000 {
 				status = "disabled";
 			};
 		};
+
+		pcie1: pcie@18000000 {
+			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+			reg = <0x18000000 0xf1c>,
+			      <0x18000f20 0xa8>,
+			      <0x18001000 0x1000>,
+			      <0x00088000 0x3000>,
+			      <0x18100000 0x1000>,
+			      <0x0008b000 0x1000>;
+			reg-names = "dbi",
+				    "elbi",
+				    "atu",
+				    "parf",
+				    "config",
+				    "mhi";
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			num-lanes = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>,
+				 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>;
+
+			msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+			interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7",
+					  "global";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+				 <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+				 <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE3X2_RCHG_CLK>,
+				 <&gcc GCC_PCIE3X2_AHB_CLK>,
+				 <&gcc GCC_PCIE3X2_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>;
+
+			assigned-clock-rates = <2000000>;
+
+			resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
+				 <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
+				 <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
+				 <&gcc GCC_PCIE3X2_AUX_CLK_ARES>,
+				 <&gcc GCC_PCIE3X2_AHB_CLK_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+
+			interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>,
+					<&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
+			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
+
+		pcie0: pcie@20000000 {
+			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+			reg = <0x20000000 0xf1c>,
+			      <0x20000f20 0xa8>,
+			      <0x20001000 0x1000>,
+			      <0x00080000 0x3000>,
+			      <0x20100000 0x1000>,
+			      <0x00083000 0x1000>;
+			reg-names = "dbi",
+				    "elbi",
+				    "atu",
+				    "parf",
+				    "config",
+				    "mhi";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>,
+				 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>;
+
+			msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7",
+					  "global";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+				 <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+				 <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE3X1_0_RCHG_CLK>,
+				 <&gcc GCC_PCIE3X1_0_AHB_CLK>,
+				 <&gcc GCC_PCIE3X1_0_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>;
+
+			assigned-clock-rates = <2000000>;
+
+			resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
+				 <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+
+			interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
+					<&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
+			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
 	};
 
 	thermal-zones {
-- 
2.34.1

[PATCH v12 4/4] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers

[Varadarajan Narayanan]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Enable the PCIe controller and PHY nodes for RDP 441.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
index 846413817e9a..79ec77cfe552 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
@@ -32,6 +32,34 @@ &sdhc {
 	status = "okay";
 };
 
+&pcie0 {
+	pinctrl-0 = <&pcie0_default>;
+	pinctrl-names = "default";
+
+	perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+};
+
+&pcie0_phy {
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-0 = <&pcie1_default>;
+	pinctrl-names = "default";
+
+	perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+};
+
+&pcie1_phy {
+	status = "okay";
+};
+
 &tlmm {
 	i2c_1_pins: i2c-1-state {
 		pins = "gpio29", "gpio30";
@@ -40,6 +68,54 @@ i2c_1_pins: i2c-1-state {
 		bias-pull-up;
 	};
 
+	pcie0_default: pcie0-default-state {
+		clkreq-n-pins {
+			pins = "gpio37";
+			function = "pcie0_clk";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio38";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+			output-low;
+		};
+
+		wake-n-pins {
+			pins = "gpio39";
+			function = "pcie0_wake";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	pcie1_default: pcie1-default-state {
+		clkreq-n-pins {
+			pins = "gpio46";
+			function = "pcie1_clk";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio47";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+			output-low;
+		};
+
+		wake-n-pins {
+			pins = "gpio48";
+			function = "pcie1_wake";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
 	sdc_default_state: sdc-default-state {
 		clk-pins {
 			pins = "gpio13";
-- 
2.34.1

Re: [PATCH v12 1/4] dt-bindings: PCI: qcom: Add MHI registers for IPQ9574

[Krzysztof Kozlowski]

On 12/03/2025 09:43, Varadarajan Narayanan wrote:
> Append the MHI register range to IPQ9574.

Why?

> 
> Fixes: e0662dae178d ("dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller")

What is being fixed here?

> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> New patch introduced in this patchset. MHI range was missed in the
> initial post
> ---
>  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 8f628939209e..77e66ab8764f 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -175,7 +175,7 @@ allOf:
>        properties:
>          reg:
>            minItems: 5
> -          maxItems: 5
> +          maxItems: 6

Why qcom,pcie-ipq6018 gets mhi? Nothing in commit msg mentions ipq6018.

>          reg-names:
>            items:
>              - const: dbi # DesignWare PCIe registers
> @@ -183,6 +183,7 @@ allOf:
>              - const: atu # ATU address space
>              - const: parf # Qualcomm specific registers
>              - const: config # PCIe configuration space
> +            - const: mhi # MHI registers

Never tested - you introduce new warnings. AGAIN.

Properties xxx and xxx-names must have always the same constraints.


Best regards,
Krzysztof

Re: [PATCH v12 1/4] dt-bindings: PCI: qcom: Add MHI registers for IPQ9574

[Varadarajan Narayanan]

On Wed, Mar 12, 2025 at 09:46:41AM +0100, Krzysztof Kozlowski wrote:
> On 12/03/2025 09:43, Varadarajan Narayanan wrote:
> > Append the MHI register range to IPQ9574.
>
> Why?

This is needed for ipq5332 to use ipq9574 as fallback compatible.

> > Fixes: e0662dae178d ("dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller")
>
> What is being fixed here?

Ok, will remove this.

> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > New patch introduced in this patchset. MHI range was missed in the
> > initial post
> > ---
> >  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > index 8f628939209e..77e66ab8764f 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > @@ -175,7 +175,7 @@ allOf:
> >        properties:
> >          reg:
> >            minItems: 5
> > -          maxItems: 5
> > +          maxItems: 6
>
> Why qcom,pcie-ipq6018 gets mhi? Nothing in commit msg mentions ipq6018.

Didn't mention ipq6018 as I was under the impression that 'minItems: 5' would
apply for ipq6018.

> >          reg-names:
> >            items:
> >              - const: dbi # DesignWare PCIe registers
> > @@ -183,6 +183,7 @@ allOf:
> >              - const: atu # ATU address space
> >              - const: parf # Qualcomm specific registers
> >              - const: config # PCIe configuration space
> > +            - const: mhi # MHI registers
>
> Never tested - you introduce new warnings. AGAIN.
>
> Properties xxx and xxx-names must have always the same constraints.

Ok, will add 'minItems: 5' here.

Thanks
Varada

Re: [PATCH v12 1/4] dt-bindings: PCI: qcom: Add MHI registers for IPQ9574

[Krzysztof Kozlowski]

On 12/03/2025 10:39, Varadarajan Narayanan wrote:
> On Wed, Mar 12, 2025 at 09:46:41AM +0100, Krzysztof Kozlowski wrote:
>> On 12/03/2025 09:43, Varadarajan Narayanan wrote:
>>> Append the MHI register range to IPQ9574.
>>
>> Why?
> 
> This is needed for ipq5332 to use ipq9574 as fallback compatible.

This sounds like you incorrect hardware description, because some other
device needs this.

Your commit msg must explain why you do things, not me keep asking the
same question over and over.

In the same time reason "ipq5332 needs it" is not correct reason.
ipq5332 is not related anyhow to this hardware. Write bindings matching
the hardware, not some other patches.


> 
>>> Fixes: e0662dae178d ("dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller")
>>
>> What is being fixed here?
> 
> Ok, will remove this.
> 
>>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>>> ---
>>> New patch introduced in this patchset. MHI range was missed in the
>>> initial post
>>> ---
>>>  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>> index 8f628939209e..77e66ab8764f 100644
>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>> @@ -175,7 +175,7 @@ allOf:
>>>        properties:
>>>          reg:
>>>            minItems: 5
>>> -          maxItems: 5
>>> +          maxItems: 6
>>
>> Why qcom,pcie-ipq6018 gets mhi? Nothing in commit msg mentions ipq6018.
> 
> Didn't mention ipq6018 as I was under the impression that 'minItems: 5' would
> apply for ipq6018.

items=5 applies to all of them and there is nothing here claiming that
items=6 does not apply...

Best regards,
Krzysztof

Re: [PATCH v12 0/4] Add PCIe support for Qualcomm IPQ5332

[Rob Herring (Arm)]

On Wed, 12 Mar 2025 14:13:26 +0530, Varadarajan Narayanan wrote:
> Patch series adds support for enabling the PCIe controller and
> UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and
> PCIe1 is Gen3 X2 are added.
> 
> This series combines [1] and [2]. [1] introduces IPQ5018 PCIe
> support and [2] depends on [1] to introduce IPQ5332 PCIe support.
> Since the community was interested in [2] (please see [3]), tried
> to revive IPQ5332's PCIe support with v2 of this patch series.
> 
> v2 of this series pulled in the phy driver from [1] tried to
> address comments/feedback given in both [1] and [2].
> 
> 1. Enable IPQ5018 PCI support (Nitheesh Sekar) - https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/
> 2. Add PCIe support for Qualcomm IPQ5332 (Praveenkumar I) - https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/
> 3. Community interest - https://lore.kernel.org/linux-arm-msm/20240310132915.GE3390@thinkpad/
> 
> v12: * Skipped the following (Vinod Koul has picked them)
> 		dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
> 		phy: qcom: Introduce PCIe UNIPHY 28LP driver
> 
>      * Skipped this (merged)
> 		dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
> 
>      * Undo combining sdx55 & ipq9574. Discard the following
> 		dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
> 		arm64: dts: qcom: ipq9574: Reorder reg and reg-names
> 
>      * Append MHI registers to ipq9574 dt-bindings and dts
> 		dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
> 		arm64: dts: qcom: ipq9574: Add MHI to pcie nodes
> 
>      * ipq5332.dtsi:
> 		Align reg-names order with ipq9574
> 		Dropped R-b tag per feedback
> 
>      * No new warnings/errors with dt_binding_check and dtbs_check
> 
> v11: * phy-qcom-uniphy-pcie-28lp.c
> 	 * Remove unused #define
> 	 * Use "250 * MEGA" instead of 250000000
> 
> v10: * ipq5332.dtsi: Trim down the list of assigned clocks
> 
>      * ipq9574 and ipq5332 DT
> 	 * Fix 'simple-bus unit address format error' in ipq9574 and
> 	   ipq5332 DTS
>          * Rearrange nodes w.r.t. address sort order
> 
>      * Have spoken with 'Manikanta Mylavarapu' [1] for omitting similar
>        changes in qcom,pcie.yaml that are handled in this series.
> 
>      * Reformat commit messages to 75 character limit
> 
>      * controller bindings:
>        Fix maxItems for interrupts constraint of sdm845
> 
>      1 - https://lore.kernel.org/linux-arm-msm/20250125035920.2651972-2-quic_mmanikan@quicinc.com/
> 
> v9: Dont have fallback for num-lanes in driver and return error
>     Remove superfluous ipq5332 constraint as the fallback is present
> 
> v8: Add reviewed by
>     Remove duplication in bindings due to ipq5424 code getting merged
> 
> v7: phy bindings:
>     * Include data type definition to 'num-lanes'
> 
>     controller bindings:
>     * Split the ipq9574 and ipq5332 changes into separate patches
> 
>     dtsi:
>     * Add root port definitions
> 
> v6: phy bindings:
>     * Fix num-lanes definition
> 
>     phy driver:
>     * Fix num-lanes handling in probe to use generally followed pattern
> 
>     controller bindings:
>     * Give more info in commit log
> 
>     dtsi:
>     * Add assigned-clocks & assigned-clock-rates to controller nodes
>     * Add num-lanes to pcie0_phy
> 
> v5: phy bindings:
>     * Drop '3x1' & '3x2' from compatible string
>     * Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
>       in compatible string
>     * Describe clocks and resets instead of just maxItems
> 
>     phy driver:
>     * Get num-lanes from DTS
>     * Drop compatible specific init data as there is only one
>       compatible string
> 
>     controller bindings:
>     * Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
> 
>     dtsi:
>     * Add 'num-lanes' to "pcie1_phy: phy@4b1000"
>     * Make ipq5332 as main and ipq9574 as fallback compatible
>     * Sort controller nodes per address
> 
>     misc:
>     Add R-B tag from Konrad to dts and dtsi patches
> 
> v4: * phy bindings - Create ipq5332 compatible instead of reusing ipq9574 for bindings
>     * phy bindings - Remove reset-names as the resets are handled with bulk APIs
>     * phy bindings - Fix order in the 'required' section
>     * phy bindings - Remove clock-output-names
>     * dtsi - Add missing reset for pcie1_phy
>     * dtsi - Convert 'reg-names' to a vertical list
>     * dts - Fix nodes sort order
>     * dts - Use property-n followed by property-names
> 
> v3: * Update the cover letter with the sources of the patches
>     * Rename the dt-bindings yaml file similar to other phys
>     * Drop ipq5332 specific pcie controllor bindings and reuse
>       ipq9574 pcie controller bindings for ipq5332
>     * Please see patches for specific changes
>     * Set GPL license for phy-qcom-uniphy-pcie-28lp.c
> 
> v2: Address review comments from V1
>     Drop the 'required clocks' change that would break ABI (in dt-binding, dts, gcc-ipq5332.c)
>     Include phy driver from the dependent series
> 
> v1: https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/
> 
> 
> Praveenkumar I (2):
>   arm64: dts: qcom: ipq5332: Add PCIe related nodes
>   arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers
> 
> Varadarajan Narayanan (2):
>   dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
>   arm64: dts: qcom: ipq9574: Add MHI to pcie nodes
> 
>  .../devicetree/bindings/pci/qcom,pcie.yaml    |   3 +-
>  arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts   |  76 ++++++
>  arch/arm64/boot/dts/qcom/ipq5332.dtsi         | 252 +++++++++++++++++-
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi         |  40 ++-
>  4 files changed, 360 insertions(+), 11 deletions(-)
> 
> 
> base-commit: eea255893718268e1ab852fb52f70c613d109b99
> prerequisite-patch-id: 56fe29d9207ac31ab08ca54712adc2a865b7be89
> prerequisite-patch-id: f50f4b13ea072aea4beae5d5ecaf62336d9d2a31
> --
> 2.34.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250312084330.873994-1-quic_varada@quicinc.com:

arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: pcie@20000000: reg-names: ['dbi', 'elbi', 'atu', 'parf', 'config'] is too short
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: pcie@20000000: reg-names: ['dbi', 'elbi', 'atu', 'parf', 'config'] is too short
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dtb: pcie@20000000: reg-names: ['dbi', 'elbi', 'atu', 'parf', 'config'] is too short
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: pcie@20000000: reg-names: ['dbi', 'elbi', 'atu', 'parf', 'config'] is too short
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#