Re: [PATCH for-linus v3 1/2] PCI: Honor Max Link Speed when determining supported speeds

[Lukas Wunner <lukas@wunner.de>]

On Thu, Dec 19, 2024 at 12:50:59PM -0500, Bjorn Helgaas wrote:
> On Thu, Dec 19, 2024, 11:37AM Krzysztof Wilczynski <kw@linux.com> wrote:
> > > > > > I'd also add reference to r6.2 section 7.5.3 which states those
> > > > > > registers are required for RPs, Switch Ports, Bridges, and
> > > > > > Endpoints _that are not RCiEPs_. My reading is that implies
> > > > > > they're not required from RCiEPs.
> 
> Don't have the spec with me, but I don't know what link-related registers
> would even mean for RCiEPs. Why would we look at them at all?

We don't:  pcie_capability_read_dword() checks whether the register
being read is actually implemented by the device:

pcie_capability_read_dword()
  pcie_capability_reg_implemented()
    pcie_cap_has_lnkctl()

And pcie_cap_has_lnkctl() returns false for PCI_EXP_TYPE_RC_END,
in which case pcie_capability_read_dword() just returns zero
without accessing Config Space.

Likewise accesses to PCI_EXP_LNKCAP2_SLS are short-circuited to zero
if the device only conforms to PCIe r1.1 or earlier and thus doesn't
implement the Link Capabilities 2 Register.  (Recognizable by
PCI_EXP_FLAGS_VERS being 1 instead of 2.)

So pcie_get_supported_speeds() returns zero for such devices and
that's the value assigned to dev->supported_speeds for RCiEPs on probe.

Thanks,

Lukas