[PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[Inochi Amaoto]

Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enable ASPM on all device tree
platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
and L1 capabilities without supporting it.

Override the L0s and L1 Support advertised in Link Capabilities by the
SG2042/SG2044 Root Ports so we don't try to enable those states.

Inochi Amaoto (2):
  PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
  PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports

 drivers/pci/quirks.c    | 2 ++
 include/linux/pci_ids.h | 2 ++
 2 files changed, 4 insertions(+)

--
2.52.0

[PATCH 1/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports

[Inochi Amaoto]

Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enable ASPM on all device tree
platform, the SG2042 root port breaks as it advertises L0s and L1
capabilities without supporting it.

Override the L0s and L1 Support advertised in Link Capabilities by the
SG2042 Root Ports ([1f1c:2042]), so we don't try to enable those states.

Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
---
 drivers/pci/quirks.c    | 1 +
 include/linux/pci_ids.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index b9c252aa6fe0..d775ff567d1b 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2526,6 +2526,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_disable_aspm_l0s_l1);
 
 /*
  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index a9a089566b7c..78638cbf2780 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2631,6 +2631,8 @@
 
 #define PCI_VENDOR_ID_CXL		0x1e98
 
+#define PCI_VENDOR_ID_SOPHGO		0x1f1c
+
 #define PCI_VENDOR_ID_TEHUTI		0x1fc9
 #define PCI_DEVICE_ID_TEHUTI_3009	0x3009
 #define PCI_DEVICE_ID_TEHUTI_3010	0x3010
-- 
2.52.0

[PATCH 2/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports

[Inochi Amaoto]

Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enable ASPM on all device tree
platform, the SG2044 root port breaks as it advertises L0s and L1
capabilities without supporting it.

Override the L0s and L1 Support advertised in Link Capabilities by the
SG2044 Root Ports ([1f1c:2044]), so we don't try to enable those states.

Fixes: 3309df45e6b5 ("riscv: dts: sophgo: sg2044: add PCIe device support for SG2044")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
---
 drivers/pci/quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index d775ff567d1b..855e74203ca9 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2527,6 +2527,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_disable_aspm_l0s_l1);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOPHGO, 0x2044, quirk_disable_aspm_l0s_l1);
 
 /*
  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
-- 
2.52.0

Re: [PATCH 1/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports

[Chen Wang]

On 12/25/2025 6:05 PM, Inochi Amaoto wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
>
> Override the L0s and L1 Support advertised in Link Capabilities by the
> SG2042 Root Ports ([1f1c:2042]), so we don't try to enable those states.
>
> Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Tested-by: Han Gao <gaohan@iscas.ac.cn>

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>

Thanks,

Chen

> ---
>   drivers/pci/quirks.c    | 1 +
>   include/linux/pci_ids.h | 2 ++
>   2 files changed, 3 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index b9c252aa6fe0..d775ff567d1b 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2526,6 +2526,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l
>   DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1);
>   DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1);
>   DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_disable_aspm_l0s_l1);
>   
>   /*
>    * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index a9a089566b7c..78638cbf2780 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -2631,6 +2631,8 @@
>   
>   #define PCI_VENDOR_ID_CXL		0x1e98
>   
> +#define PCI_VENDOR_ID_SOPHGO		0x1f1c
> +
>   #define PCI_VENDOR_ID_TEHUTI		0x1fc9
>   #define PCI_DEVICE_ID_TEHUTI_3009	0x3009
>   #define PCI_DEVICE_ID_TEHUTI_3010	0x3010

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[Bjorn Helgaas]

On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> and L1 capabilities without supporting it.
> 
> Override the L0s and L1 Support advertised in Link Capabilities by the
> SG2042/SG2044 Root Ports so we don't try to enable those states.
> 
> Inochi Amaoto (2):
>   PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
>   PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> 
>  drivers/pci/quirks.c    | 2 ++
>  include/linux/pci_ids.h | 2 ++
>  2 files changed, 4 insertions(+)

1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
just want to make rule out some kind of OS bug in configuring L0s/L1.

2) Why don't we have a MAINTAINERS entry for this driver?  I failed to
notice that the series we applied
(https://lore.kernel.org/all/cover.1757643388.git.unicorn_wang@outlook.com/)
does not include a maintainer.  Chen, since you posted that series,
are you willing to sign up to maintain it?

Bjorn

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[Chen Wang]

On 12/27/2025 12:30 AM, Bjorn Helgaas wrote:
> On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
>> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
>> states for devicetree platforms") force enable ASPM on all device tree
>> platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
>> and L1 capabilities without supporting it.
>>
>> Override the L0s and L1 Support advertised in Link Capabilities by the
>> SG2042/SG2044 Root Ports so we don't try to enable those states.
>>
>> Inochi Amaoto (2):
>>    PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
>>    PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
>>
>>   drivers/pci/quirks.c    | 2 ++
>>   include/linux/pci_ids.h | 2 ++
>>   2 files changed, 4 insertions(+)
> 1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
> just want to make rule out some kind of OS bug in configuring L0s/L1.
>
> 2) Why don't we have a MAINTAINERS entry for this driver?  I failed to
> notice that the series we applied
> (https://lore.kernel.org/all/cover.1757643388.git.unicorn_wang@outlook.com/)
> does not include a maintainer.  Chen, since you posted that series,
> are you willing to sign up to maintain it?
Sorry, I didn't realize I needed to submit maintainer information 
separately for each driver when I submitted the PCIe driver code.

Yes, I will be maintaining the SG2042 PCIe driver. Do I need to add an 
entry to the MAINTAINERS file?

Chen

>
> Bjorn

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[Bjorn Helgaas]

On Mon, Dec 29, 2025 at 08:17:40AM +0800, Chen Wang wrote:
> On 12/27/2025 12:30 AM, Bjorn Helgaas wrote:
> > On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> > > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > > states for devicetree platforms") force enable ASPM on all device tree
> > > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> > > and L1 capabilities without supporting it.
> > > 
> > > Override the L0s and L1 Support advertised in Link Capabilities by the
> > > SG2042/SG2044 Root Ports so we don't try to enable those states.
> > > 
> > > Inochi Amaoto (2):
> > >    PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
> > >    PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> > > 
> > >   drivers/pci/quirks.c    | 2 ++
> > >   include/linux/pci_ids.h | 2 ++
> > >   2 files changed, 4 insertions(+)
> ...

> > 2) Why don't we have a MAINTAINERS entry for this driver?  I failed to
> > notice that the series we applied
> > (https://lore.kernel.org/all/cover.1757643388.git.unicorn_wang@outlook.com/)
> > does not include a maintainer.  Chen, since you posted that series,
> > are you willing to sign up to maintain it?
>
> Sorry, I didn't realize I needed to submit maintainer information
> separately for each driver when I submitted the PCIe driver code.
> 
> Yes, I will be maintaining the SG2042 PCIe driver. Do I need to add
> an entry to the MAINTAINERS file?

Yes, please.

  $ ./scripts/get_maintainer.pl drivers/pci/controller/cadence/pcie-sg2042.c
  Lorenzo Pieralisi <lpieralisi@kernel.org> (maintainer:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS)
  "Krzysztof Wilczyński" <kwilczynski@kernel.org> (maintainer:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS)
  Manivannan Sadhasivam <mani@kernel.org> (maintainer:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS,commit_signer:2/2=100%)
  ...
  Chen Wang <unicorn_wang@outlook.com> (commit_signer:2/2=100%,authored:1/2=50%,added_lines:134/134=100%)

This does list you, but only as a commit signer.  It should list you
as a maintainer of the driver so people know to send patches to you
(and cc linux-pci, of course).

Bjorn

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[Inochi Amaoto]

On Fri, Dec 26, 2025 at 10:30:31AM -0600, Bjorn Helgaas wrote:
> On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > states for devicetree platforms") force enable ASPM on all device tree
> > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> > and L1 capabilities without supporting it.
> > 
> > Override the L0s and L1 Support advertised in Link Capabilities by the
> > SG2042/SG2044 Root Ports so we don't try to enable those states.
> > 
> > Inochi Amaoto (2):
> >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
> >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> > 
> >  drivers/pci/quirks.c    | 2 ++
> >  include/linux/pci_ids.h | 2 ++
> >  2 files changed, 4 insertions(+)
> 
> 1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
> just want to make rule out some kind of OS bug in configuring L0s/L1.
> 

Hi Bjorn,

I have asked for the Sophgo staff, and they already confirmed this 
hardware errata.

Regards,
Inochi

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[Manivannan Sadhasivam]

On Tue, Dec 30, 2025 at 05:45:39PM +0800, Inochi Amaoto wrote:
> On Fri, Dec 26, 2025 at 10:30:31AM -0600, Bjorn Helgaas wrote:
> > On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> > > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > > states for devicetree platforms") force enable ASPM on all device tree
> > > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> > > and L1 capabilities without supporting it.
> > > 
> > > Override the L0s and L1 Support advertised in Link Capabilities by the
> > > SG2042/SG2044 Root Ports so we don't try to enable those states.
> > > 
> > > Inochi Amaoto (2):
> > >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
> > >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> > > 
> > >  drivers/pci/quirks.c    | 2 ++
> > >  include/linux/pci_ids.h | 2 ++
> > >  2 files changed, 4 insertions(+)
> > 
> > 1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
> > just want to make rule out some kind of OS bug in configuring L0s/L1.
> > 
> 
> Hi Bjorn,
> 
> I have asked for the Sophgo staff, and they already confirmed this 
> hardware errata.
> 

Okay. If the hardware (Root Port) doesn't support L0s and L1, you should disable
the capability in the sophgo controller driver instead. You can use this as a
reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-qcom.c#n331

Quirks is mostly meant for PCI endpoint devices (sometimes Root Ports also if
there is no host controller driver).

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[Inochi Amaoto]

On Tue, Dec 30, 2025 at 03:38:11PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Dec 30, 2025 at 05:45:39PM +0800, Inochi Amaoto wrote:
> > On Fri, Dec 26, 2025 at 10:30:31AM -0600, Bjorn Helgaas wrote:
> > > On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> > > > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > > > states for devicetree platforms") force enable ASPM on all device tree
> > > > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> > > > and L1 capabilities without supporting it.
> > > > 
> > > > Override the L0s and L1 Support advertised in Link Capabilities by the
> > > > SG2042/SG2044 Root Ports so we don't try to enable those states.
> > > > 
> > > > Inochi Amaoto (2):
> > > >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
> > > >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> > > > 
> > > >  drivers/pci/quirks.c    | 2 ++
> > > >  include/linux/pci_ids.h | 2 ++
> > > >  2 files changed, 4 insertions(+)
> > > 
> > > 1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
> > > just want to make rule out some kind of OS bug in configuring L0s/L1.
> > > 
> > 
> > Hi Bjorn,
> > 
> > I have asked for the Sophgo staff, and they already confirmed this 
> > hardware errata.
> > 
> 
> Okay. If the hardware (Root Port) doesn't support L0s and L1, you should disable
> the capability in the sophgo controller driver instead. You can use this as a
> reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-qcom.c#n331
> 
> Quirks is mostly meant for PCI endpoint devices (sometimes Root Ports also if
> there is no host controller driver).
> 
> - Mani
> 

Good to know, I will switch to quirks, thanks.

Regards,
Inochi