From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset
Date: Sun, 11 Oct 2026 02:24:49 +0000 [thread overview]
Message-ID: <sashiko-outbox-166974@kernel.org> (raw)
In-Reply-To: <20261011021422.3428136-16-smadhavan@nvidia.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] pci: cxl_reset_bus_function() incorrectly bypasses SBR topology checks on probe
--
commit 3639cffcefe2a45e59bbab7de2628286c4acba6c
Author: Srirangan Madhavan <smadhavan@nvidia.com>
Subject: PCI/CXL: Restore CXL state after CXL bus reset
This commit restores CXL state after a successful cxl_bus reset while IOMMU
exclusion remains active. It allocates HDM state storage ahead of a bus
reset, restoring the PCI configuration first so HDM MMIO is accessible.
Link: https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/commit/?id=b93f0c8e67b198a63786fd3721b7177ab9df60be
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index b58a6a6133119..cecf8e681e69b 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5014,6 +5014,7 @@ static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
>
> static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
> {
> + struct cxl_hdm_info *snapshot __free(kfree) = NULL;
[Severity: Medium]
Does this function incorrectly bypass the topology and hardware constraints
checked in pci_reset_bus_function() when probe is true?
For reference, the code in cxl_reset_bus_function() returns early for probes:
if (probe)
return 0;
The pci_dev_reset_methods subsystem uses the probe argument to query whether
a specific reset method is supported and safe for a given device topology. By
returning 0 unconditionally when probe is true, the call to
pci_reset_bus_function() located further down is skipped.
Because pci_reset_bus_function() enforces critical constraints, such as
checking if SBR is enabled and ensuring the device is the only device on the
secondary bus, bypassing these checks during probe can cause the kernel to
falsely advertise the cxl_bus reset method via sysfs for devices that share a
bus or have SBR masked.
If this occurs, when userspace attempts the reset, it will deterministically
fail with -ENOTTY during the actual execution phase, breaking the API contract
of the probe step.
> struct pci_dev *bridge;
> u16 dvsec, reg, val;
> int rc;
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261011021422.3428136-1-smadhavan@nvidia.com?part=15
next prev parent reply other threads:[~2026-10-11 2:24 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-11 2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-11 2:16 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11 2:19 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-11 2:22 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-11 2:21 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-11 2:23 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-11 2:21 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11 2:28 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11 2:34 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11 2:24 ` sashiko-bot [this message]
2026-10-11 2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-11 2:22 ` sashiko-bot
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