From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup
Date: Sun, 11 Oct 2026 02:25:43 +0000 [thread overview]
Message-ID: <sashiko-outbox-166979@kernel.org> (raw)
In-Reply-To: <20261011021422.3428136-3-smadhavan@nvidia.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] cleanup: Mixing goto-based error handling with scope-based cleanup in read_cdat_data()
- [Low] cxl: mixing goto and __free() in read_cdat_data()
--
commit 3f404cf13bcc3f018e17d22aaca79f82e169bf5d
Author: Srirangan Madhavan <smadhavan@nvidia.com>
cxl: Share CXL port upstream PCI device lookup
This commit factors out the lookup of a CXL port's upstream PCI device
into a new helper cxl_port_get_uport_pci_dev(). It also updates
read_cdat_data() to use this helper with a scope-based cleanup variable
to manage the PCI device reference.
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 9d807c1a002ca..c3c41efae5fde 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -564,26 +564,14 @@ static unsigned char cdat_checksum(void *buf, size_t size)
> */
> void read_cdat_data(struct cxl_port *port)
> {
> - struct device *uport = port->uport_dev;
> + struct pci_dev *pdev __free(pci_dev_put) =
> + cxl_port_get_uport_pci_dev(port);
> struct device *dev = &port->dev;
[Severity: Low]
Does this introduction of __free() conflict with the existing goto-based
error handling in this function?
Looking further down in read_cdat_data(), the function still relies on
legacy goto-based error handling for the buffer allocation:
buf = devm_kzalloc(dev, sizeof(*buf) + length, GFP_KERNEL);
if (!buf)
goto err;
table_length = length;
rc = cxl_cdat_read_table(dev, doe_mb, buf, &length);
if (rc)
goto err;
...
err:
/* Don't leave table data allocated on error */
devm_kfree(dev, buf);
dev_err(dev, "Failed to read/validate CDAT.\n");
The cleanup subsystem guidelines recommend that for a given routine, we
should convert all resources that need a goto cleanup to scope-based
cleanup, or convert none of them. Mixing goto-based cleanup labels with
__free() declarations can create confusing ownership semantics and
complicate future refactoring.
Should buf also be converted to use scope-based cleanup, or should pdev be
managed explicitly to keep the error handling style consistent?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261011021422.3428136-1-smadhavan@nvidia.com?part=2
next prev parent reply other threads:[~2026-10-11 2:25 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-11 2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-11 2:16 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot [this message]
2026-10-11 2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11 2:19 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-11 2:22 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-11 2:21 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-11 2:23 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-11 2:21 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11 2:28 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11 2:34 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11 2:24 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-11 2:22 ` sashiko-bot
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