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From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope
Date: Sun, 11 Oct 2026 02:28:00 +0000	[thread overview]
Message-ID: <sashiko-outbox-166981@kernel.org> (raw)
In-Reply-To: <20261011021422.3428136-13-smadhavan@nvidia.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] pci: CXL reset restriction fails to reject VFs, allowing device-wide resets
--

commit bc92caba866b3736b7ca2232519b796c40f058e5
Author: Srirangan Madhavan <smadhavan@nvidia.com>

PCI/CXL: Reject reset with unsafe function scope

The per-device PCI reset interface must not reset sibling functions.
Reject cxl_reset and cxl_bus for multifunction devices and PFs with
enabled VFs.

Link: https://lore.kernel.org/linux-cxl/20260626160846.426e71b6@nvidia.com/
Link: https://lore.kernel.org/linux-cxl/6a50441e2bb5e_3cabcb1003e@djbw-dev.notmuch/

> diff --git a/drivers/pci/cxl.c b/drivers/pci/cxl.c
> index 3da8b316857f1..eccdb57945feb 100644
> --- a/drivers/pci/cxl.c
> +++ b/drivers/pci/cxl.c
> @@ -496,6 +496,9 @@ int cxl_reset_function(struct pci_dev *pdev, bool probe)
>  	    !(ctrl & PCI_DVSEC_CXL_MEM_ENABLE))
>  		return -ENOTTY;
>  
> +	if (pdev->multifunction || pci_num_vf(pdev))
> +		return -ENOTTY;

[Severity: High]
Does this check fail to reject Virtual Functions (VFs)?

Since VFs are initialized as single-function (pdev->multifunction = 0) and
pci_num_vf(pdev) returns 0 for non-PF devices, this restriction appears to be
bypassed for VFs. 

If the CXL 3.0+ hardware exposes the CXL DVSEC on the VF, triggering a reset
on a VF would bypass this check and reset the entire CXL endpoint, disrupting
the PF and all sibling VFs. Should this check also include pdev->is_virtfn?

> +
>  	if (probe)
>  		return 0;
>  
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index b2879a6be5f80..fe611340f5ab1 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5026,6 +5026,9 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
>  	if (!dvsec)
>  		return -ENOTTY;
>  
> +	if (dev->multifunction || pci_num_vf(dev))
> +		return -ENOTTY;

[Severity: High]
Similarly, does this bus reset check allow VFs to bypass the restriction and
inadvertently trigger a bus reset affecting sibling functions?

> +
>  	if (probe)
>  		return 0;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261011021422.3428136-1-smadhavan@nvidia.com?part=12

  reply	other threads:[~2026-10-11  2:28 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-11  2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-11  2:16   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11  2:19   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-11  2:22   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-11  2:21   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-11  2:23   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-11  2:21   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11  2:28   ` sashiko-bot [this message]
2026-10-11  2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11  2:34   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11  2:24   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-11  2:22   ` sashiko-bot

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