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From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method
Date: Sun, 11 Oct 2026 02:34:39 +0000	[thread overview]
Message-ID: <sashiko-outbox-166982@kernel.org> (raw)
In-Reply-To: <20261011021422.3428136-15-smadhavan@nvidia.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] pci/cxl: incorrect capability probing in cxl_reset_function()
--

commit caffe4423e688e1f05bdb2a57599ac06d181265a
Author: Srirangan Madhavan <smadhavan@nvidia.com>

PCI/CXL: Expose CXL Reset as a PCI reset method

Register cxl_reset with the PCI reset-method interface and place it before
FLR, which does not reset CXL.cache or CXL.mem protocol state.

Return -ENOTTY when device capabilities, function scope, cached HDM state,
or required cache synchronization do not permit a safe reset.

> diff --git a/drivers/pci/cxl.c b/drivers/pci/cxl.c
> index 4c6b712ed4faf..7a225e215ca5c 100644
> --- a/drivers/pci/cxl.c
> +++ b/drivers/pci/cxl.c
[ ... ]
> @@ -651,9 +651,9 @@ int cxl_reset_function(struct pci_dev *pdev, bool probe)
>  
>  	rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CTRL, &ctrl);
>  	if (rc)
> -		return pcibios_err_to_errno(rc);
> +		return probe ? -ENOTTY : pcibios_err_to_errno(rc);
>  	if (PCI_POSSIBLE_ERROR(ctrl))
> -		return -ENODEV;
> +		return probe ? -ENOTTY : -ENODEV;
>  	if (!(ctrl & PCI_DVSEC_CXL_CACHE_ENABLE) ||
>  	    !(ctrl & PCI_DVSEC_CXL_MEM_ENABLE))
>  		return -ENOTTY;

[Severity: Medium]
Will this dynamic state check introduce a regression where the probe incorrectly
fails?

If the BIOS hasn't pre-enabled CXL memory, PCI_DVSEC_CXL_MEM_ENABLE will be 0.
Since this dynamic state is checked before the early return for probe further
down in the function, the method fails probing and isn't registered in sysfs,
even though the OS driver will enable CXL memory later.

Additionally, because the early return happens before static capability checks
like this:

    if (probe)
        return 0;

    /* ... */

    if (!cpu_cache_has_invalidate_memregion())
        return -ENOTTY;

Will this cause a regression that falsely advertises the capability in sysfs on
architectures lacking cache invalidation since the static check is skipped
during probe?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261011021422.3428136-1-smadhavan@nvidia.com?part=14

  reply	other threads:[~2026-10-11  2:34 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-11  2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-11  2:16   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11  2:19   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-11  2:22   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-11  2:21   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-11  2:23   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-11  2:21   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11  2:28   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-11  2:25   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11  2:34   ` sashiko-bot [this message]
2026-10-11  2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11  2:24   ` sashiko-bot
2026-10-11  2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-11  2:22   ` sashiko-bot

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