From: sashiko-bot@kernel.org
To: "Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v10 RESEND 5/9] riscv: mm: avoid enabling interrupts for nofault page faults
Date: Mon, 21 Sep 2026 11:28:05 +0000 [thread overview]
Message-ID: <20260921112806.2C96A1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <4bc18f96053a7859a3ff33747479b05a9e42a706.1789974241.git.zhangzhanpeng.jasper@bytedance.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] riscv: mm: fixup_exception bypasses vmalloc_fault for nofault accesses
--
commit b959120cb7ee095dc7b5e388ec2110c0a78dd4ac
Author: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
riscv: mm: avoid enabling interrupts for nofault page faults
This commit modifies the RISC-V page fault handler to resolve nofault accesses
via the exception table before enabling interrupts or entering the generic
fault path. It aims to prevent in-atomic nofault accesses from inadvertently
running tracepoints or opening an interrupt window.
> diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
> --- a/arch/riscv/mm/fault.c
> +++ b/arch/riscv/mm/fault.c
> @@ -294,6 +294,13 @@ void handle_page_fault(struct pt_regs *regs)
> if (kprobe_page_fault(regs, cause))
> return;
>
> + /*
> + * Nofault accesses must be resolved through the exception table before
> + * entering the generic fault path or enabling interrupts.
> + */
> + if (unlikely(faulthandler_disabled()) && fixup_exception(regs))
> + return;
[Severity: High]
Will this new check in handle_page_fault intercept faults on valid vmalloc
addresses before vmalloc_fault has a chance to execute?
When tools like BPF or perf perform a legitimate nofault read (such as via
copy_from_kernel_nofault) on a vmalloc address that has not yet been
synchronized to the current task PGD, it triggers a page fault. Since
faulthandler_disabled is true in a nofault context, it appears this new
early check will call fixup_exception and immediately return.
On 32-bit RISC-V and !MMU configurations, this bypasses the lazy PGD
synchronization performed a few lines further down:
if ((!IS_ENABLED(CONFIG_MMU) || !IS_ENABLED(CONFIG_64BIT)) &&
unlikely(addr >= VMALLOC_START && addr < VMALLOC_END)) {
vmalloc_fault(regs, code, addr);
return;
}
Could this cause valid kernel vmalloc reads via nofault accessors to
spuriously fail with -EFAULT?
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1789974241.git.zhangzhanpeng.jasper@bytedance.com?part=5
next prev parent reply other threads:[~2026-09-21 11:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 11:14 [PATCH v10 RESEND 0/9] riscv: add SBI Supervisor Software Events support Zhanpeng Zhang
2026-09-21 11:14 ` [PATCH v10 RESEND 1/9] riscv: add SBI SSE extension definitions Zhanpeng Zhang
2026-09-21 11:23 ` sashiko-bot
2026-09-21 11:14 ` [PATCH v10 RESEND 2/9] riscv: add support for SBI Supervisor Software Events extension Zhanpeng Zhang
2026-09-21 11:31 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 3/9] riscv: sse: mask events during shutdown and kexec Zhanpeng Zhang
2026-09-21 11:30 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 4/9] drivers: firmware: add riscv SSE support Zhanpeng Zhang
2026-09-21 11:34 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 5/9] riscv: mm: avoid enabling interrupts for nofault page faults Zhanpeng Zhang
2026-09-21 11:28 ` sashiko-bot [this message]
2026-09-21 11:15 ` [PATCH v10 RESEND 6/9] perf: RISC-V: support callchains with SSE delivery Zhanpeng Zhang
2026-09-21 11:36 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 7/9] perf: RISC-V: add support for SSE event Zhanpeng Zhang
2026-09-21 11:33 ` sashiko-bot
2026-10-02 12:31 ` Conor Dooley
2026-09-21 11:15 ` [PATCH v10 RESEND 8/9] selftests/riscv: add SSE test module Zhanpeng Zhang
2026-09-21 11:32 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 9/9] selftests/riscv: add perf user-stack SSE copy regression test Zhanpeng Zhang
2026-09-21 11:25 ` sashiko-bot
2026-09-23 4:17 ` [PATCH v10 RESEND 0/9] riscv: add SBI Supervisor Software Events support Himanshu Chauhan
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