From: sashiko-bot@kernel.org
To: "Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v10 RESEND 4/9] drivers: firmware: add riscv SSE support
Date: Mon, 21 Sep 2026 11:34:25 +0000 [thread overview]
Message-ID: <20260921113425.DDEBD1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <af6bf140f2bf97a85bed00f0cb6603bc220b5b0d.1789974241.git.zhangzhanpeng.jasper@bytedance.com>
> From: Clément Léger <cleger@rivosinc.com>
>
> Add a driver-level interface for RISC-V SSE. Linux clients can register
> handlers, select a target CPU for global events, and enable, disable or
> unregister events. The architecture entry wrapper completes an event after
> the registered handler returns. PMU and GHES drivers can use this
> interface.
>
> Represent global events with one firmware registration and local events
> with one registration per possible CPU. Keep registration and enable state
> stable across CPU hotplug, and validate firmware-provided hart IDs before
> converting them to Linux CPU IDs. Use phys_addr_t for attribute buffers to
> match the physical addresses passed to firmware. Require MMU support
> because the current event-stack implementation relies on vmapped memory and
> TLB synchronization.
> [ ... ]
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> Co-developed-by: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>
> Signed-off-by: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>
> Co-developed-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
> Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1789974241.git.zhangzhanpeng.jasper@bytedance.com?part=4
next prev parent reply other threads:[~2026-09-21 11:34 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 11:14 [PATCH v10 RESEND 0/9] riscv: add SBI Supervisor Software Events support Zhanpeng Zhang
2026-09-21 11:14 ` [PATCH v10 RESEND 1/9] riscv: add SBI SSE extension definitions Zhanpeng Zhang
2026-09-21 11:23 ` sashiko-bot
2026-09-21 11:14 ` [PATCH v10 RESEND 2/9] riscv: add support for SBI Supervisor Software Events extension Zhanpeng Zhang
2026-09-21 11:31 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 3/9] riscv: sse: mask events during shutdown and kexec Zhanpeng Zhang
2026-09-21 11:30 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 4/9] drivers: firmware: add riscv SSE support Zhanpeng Zhang
2026-09-21 11:34 ` sashiko-bot [this message]
2026-09-21 11:15 ` [PATCH v10 RESEND 5/9] riscv: mm: avoid enabling interrupts for nofault page faults Zhanpeng Zhang
2026-09-21 11:28 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 6/9] perf: RISC-V: support callchains with SSE delivery Zhanpeng Zhang
2026-09-21 11:36 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 7/9] perf: RISC-V: add support for SSE event Zhanpeng Zhang
2026-09-21 11:33 ` sashiko-bot
2026-10-02 12:31 ` Conor Dooley
2026-09-21 11:15 ` [PATCH v10 RESEND 8/9] selftests/riscv: add SSE test module Zhanpeng Zhang
2026-09-21 11:32 ` sashiko-bot
2026-09-21 11:15 ` [PATCH v10 RESEND 9/9] selftests/riscv: add perf user-stack SSE copy regression test Zhanpeng Zhang
2026-09-21 11:25 ` sashiko-bot
2026-09-23 4:17 ` [PATCH v10 RESEND 0/9] riscv: add SBI Supervisor Software Events support Himanshu Chauhan
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