Linux Perf Users
 help / color / mirror / Atom feed
From: Jonathan Cameron <jic23@kernel.org>
To: Dave Jiang <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org, linux-perf-users@vger.kernel.org,
	will@kernel.org, mark.rutland@arm.com, dave@stgolabs.net,
	robin.murphy@arm.com, icheng@nvidia.com,
	Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>,
	Robert Richter <rrichter@amd.com>
Subject: Re: [RESEND PATCH v4 00/11] perf/cxlpmu: Misc sashiko raised issues fixes
Date: Tue, 22 Sep 2026 02:02:16 +0100	[thread overview]
Message-ID: <20260922020216.2d1776ca@jic23-hlaptop> (raw)
In-Reply-To: <20260805155911.1304807-1-dave.jiang@intel.com>

On Wed,  5 Aug 2026 08:59:00 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> [resend, mangled linux-cxl mailing addr]
> 
> Teed off of Davidlohr's misc cxlpmu series [1]. I had Claude pick up all
> the sashiko raised issues and then continued multiple internal review
> iterations to pick up a number of fixes. I'm no CXL PMU or perf expert,
> but the fixes look reasonable to me AFAICT.

+CC Robert given Robert is talking about what needs adding to this driver at
LPC and so presumably has hardware (and will send lots of nice patches
for this driver shortly ;)

https://lpc.events/event/20/contributions/2521/


> 
> Since v3:
> - 4/11 and 5/11 swapped, so the one-line MSI vector 0 fix comes before the
>   info->msi_vec rename and backports on its own (Robin).
> - 6/11: new patch, add the PMUs after configuring events.
> - 7/11: no code change; the commit message no longer overstates what
>   dropping IRQF_SHARED costs a device that shares a vector.
> - 8/11: quote the spec sentence that makes the freeze sticky, and correct
>   the claim about what the migration window leaves enabled (Richard,
>   sashiko-bot).
> - 10/11: split the probe-time overflow clear out, so this is back to the
>   single hunk Jonathan acked.
> - 11/11: new patch. Clear a counter's stale overflow status when starting
>   an event, which is where the reuse case bites; the probe clear moved
>   here from 10/11 (Richard).
> 
> Since v2:
> - 1/11: check event_idx alongside counter_idx (Jonathan).
> - 2/11: use FIELD_MODIFY() rather than mask-then-OR (Jonathan).
> - 3/11: rewrite the rationale, no code change (Jonathan).
> - 5/11: new patch, split the MSI vector out of info->irq (Robin, Jonathan).
> - 7/11: drop IRQF_SHARED as well as adding IRQF_NOBALANCING, and retitle
>   (Jonathan, Robin).
> - 8/11: don't unfreeze if the PMU has been disabled meanwhile (Robin,
>   Jonathan).
> - 10/11: retitle, and drop the cxl_pmu_offline_cpu() hunk since that
>   dev_err() cannot be reached (Robin).
> - Dropped the old 9/9 that guarded cpumask_show() against cpumask_of(-1).
>   The init case was a false positive and neither reviewer liked the shape
>   of it (Jonathan, Robin).
> 
> Since v1:
> - Updated 3/9 to address sashiko issue.
> - No other changes as sashiko only raised issue with pre-existing.
> 
> Three follow-ups this series does not attempt:
> 
> cxl_pmu_read() relies on local64_t being same-CPU, which is the only reason
> the interrupt has to be pinned at all. Moving prev_count and event->count
> off local64_t would make the affinity question moot, and Robin may have a
> view on whether that is worth doing.
> 
> cxl_pmu_offline_cpu() still leaves on_cpu at -1 across a sleeping
> perf_pmu_migrate_context(), and still has an unreachable no-target branch.
> Both want removing, possibly on top of the generic PMU hotplug rework
> Jonathan pointed at [2].
> 
> Firmware can leave a counter enabled with Global Freeze on Overflow but not
> Interrupt on Overflow, which stalls the whole CPMU with no interrupt to say
> so. Quiescing the block at probe needs two writes per counter to stay
> within the spec's rule about changing an enabled counter, so it belongs in
> its own patch.
> 
> [1]: https://lore.kernel.org/linux-cxl/20260715191454.459673-1-dave@stgolabs.net/
> [2]: https://lore.kernel.org/linux-arm-kernel/cover.1784911757.git.robin.murphy@arm.com/
> 
> Dave Jiang (11):
>   perf/cxl: Program the requested event group on configurable counters
>   perf/cxl: Clear stale event fields before reprogramming a counter
>   perf/cxl: Fix the counter overflow delta fixup
>   perf/cxl: Accept an overflow interrupt on MSI message number 0
>   perf/cxl: Split the MSI vector out of info->irq
>   cxl/pci: Add the PMUs after configuring events
>   perf/cxl: Don't share the overflow interrupt, and keep it pinned
>   perf/cxl: Unfreeze counters after handling an overflow interrupt
>   perf/cxl: Validate the hardware-reported counter width
>   perf/cxl: Don't log through pmu.dev in the overflow interrupt handler
>   perf/cxl: Clear stale overflow status before using a counter
> 
>  drivers/cxl/pci.c      |  11 +++--
>  drivers/perf/cxl_pmu.c | 107 ++++++++++++++++++++++++++++++++---------
>  2 files changed, 90 insertions(+), 28 deletions(-)
> 
> 
> base-commit: f5098b6bae761e346ebcd9da7f95622c04733cff


  parent reply	other threads:[~2026-09-22  1:02 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-05 15:59 [RESEND PATCH v4 00/11] perf/cxlpmu: Misc sashiko raised issues fixes Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 01/11] perf/cxl: Program the requested event group on configurable counters Dave Jiang
2026-08-05 16:23   ` sashiko-bot
2026-08-05 15:59 ` [RESEND PATCH v4 02/11] perf/cxl: Clear stale event fields before reprogramming a counter Dave Jiang
2026-08-05 16:12   ` sashiko-bot
2026-09-22  0:58   ` Jonathan Cameron
2026-08-05 15:59 ` [RESEND PATCH v4 03/11] perf/cxl: Fix the counter overflow delta fixup Dave Jiang
2026-09-22  0:59   ` Jonathan Cameron
2026-08-05 15:59 ` [RESEND PATCH v4 04/11] perf/cxl: Accept an overflow interrupt on MSI message number 0 Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 05/11] perf/cxl: Split the MSI vector out of info->irq Dave Jiang
2026-09-22  1:03   ` Jonathan Cameron
2026-08-05 15:59 ` [RESEND PATCH v4 06/11] cxl/pci: Add the PMUs after configuring events Dave Jiang
2026-08-05 16:51   ` Alison Schofield
2026-09-22  1:05   ` Jonathan Cameron
2026-08-05 15:59 ` [RESEND PATCH v4 07/11] perf/cxl: Don't share the overflow interrupt, and keep it pinned Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 08/11] perf/cxl: Unfreeze counters after handling an overflow interrupt Dave Jiang
2026-08-05 16:15   ` sashiko-bot
2026-08-05 16:35     ` Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 09/11] perf/cxl: Validate the hardware-reported counter width Dave Jiang
2026-08-05 16:16   ` sashiko-bot
2026-08-05 15:59 ` [RESEND PATCH v4 10/11] perf/cxl: Don't log through pmu.dev in the overflow interrupt handler Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 11/11] perf/cxl: Clear stale overflow status before using a counter Dave Jiang
2026-08-05 16:21   ` sashiko-bot
2026-09-22  1:09   ` Jonathan Cameron
2026-09-15 22:43 ` [RESEND PATCH v4 00/11] perf/cxlpmu: Misc sashiko raised issues fixes Ian Rogers
2026-09-18 16:50   ` Dave Jiang
2026-09-22  1:02 ` Jonathan Cameron [this message]
2026-10-04 22:09 ` Will Deacon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260922020216.2d1776ca@jic23-hlaptop \
    --to=jic23@kernel.org \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=icheng@nvidia.com \
    --cc=jonathan.cameron@oss.qualcomm.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-perf-users@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=robin.murphy@arm.com \
    --cc=rrichter@amd.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox