Re: [PATCH 01/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for ICX

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

On 5/20/2026 6:19 AM, Chen, Zide wrote:
>
> On 5/15/2026 11:11 PM, Dapeng Mi wrote:
>> Update perf hard-coded event constraints and cache_extra_regs[] for
>> Icelake server according to the latest ICX perfmon events (v1.30).
> Nit: Ice Lake>

Sure. Thanks.


>> Since the value of cache extra registers differs with previous
>> generations, introduce new snc_hw_cache_extra_regs[] to represent the
>> value of extra registers on ICX.
>>
>> ICX perfmon events:
>> https://github.com/intel/perfmon/blob/main/ICX/events/icelakex_core.json
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> ---
> Reviewed-by: zide.chen@intel.com
>
>>  arch/x86/events/intel/core.c | 48 ++++++++++++++++++++++++++++++++----
>>  1 file changed, 43 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 793335c3ce78..1390d1da985b 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -310,10 +310,11 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
>>  static struct event_constraint intel_icl_event_constraints[] = {
>>  	FIXED_EVENT_CONSTRAINT(0x00c0, 0),	/* INST_RETIRED.ANY */
>>  	FIXED_EVENT_CONSTRAINT(0x01c0, 0),	/* old INST_RETIRED.PREC_DIST */
>> -	FIXED_EVENT_CONSTRAINT(0x0100, 0),	/* INST_RETIRED.PREC_DIST */
>> +	FIXED_EVENT_CONSTRAINT(0x0100, 0),	/* pseudo INST_RETIRED.ANY */
>>  	FIXED_EVENT_CONSTRAINT(0x003c, 1),	/* CPU_CLK_UNHALTED.CORE */
>> -	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* CPU_CLK_UNHALTED.REF */
>> -	FIXED_EVENT_CONSTRAINT(0x0400, 3),	/* SLOTS */
>> +	FIXED_EVENT_CONSTRAINT(0x0200, 1),	/* pseudo CPU_CLK_UNHALTED.THREAD */
>> +	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* pseudo CPU_CLK_UNHALTED.REF_TSC */
>> +	FIXED_EVENT_CONSTRAINT(0x0400, 3),	/* pseudo TOPDOWN.SLOTS */
>>  	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
>>  	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
>>  	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
>> @@ -1019,6 +1020,41 @@ static __initconst const u64 skl_hw_cache_extra_regs
>>   },
>>  };
>>  
>> +static __initconst const u64 snc_hw_cache_extra_regs
>> +				[PERF_COUNT_HW_CACHE_MAX]
>> +				[PERF_COUNT_HW_CACHE_OP_MAX]
>> +				[PERF_COUNT_HW_CACHE_RESULT_MAX] =
>> +{
>> + [ C(LL  ) ] = {
>> +	[ C(OP_READ) ] = {
>> +		[ C(RESULT_ACCESS) ] = 0x10001,		/* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
>> +		[ C(RESULT_MISS)   ] = 0x3FBFC00001,	/* OCR.DEMAND_DATA_RD.L3_MISS */
>> +	},
>> +	[ C(OP_WRITE) ] = {
>> +		[ C(RESULT_ACCESS) ] = 0x3F3FFC0002,	/* OCR.DEMAND_RFO.ANY_RESPONSE */
>> +		[ C(RESULT_MISS)   ] = 0x3F3FC00002,	/* OCR.DEMAND_RFO.L3_MISS */
>> +	},
>> +	[ C(OP_PREFETCH) ] = {
>> +		[ C(RESULT_ACCESS) ] = 0x0,
>> +		[ C(RESULT_MISS)   ] = 0x0,
>> +	},
>> + },
>> + [ C(NODE) ] = {
>> +	[ C(OP_READ) ] = {
>> +		[ C(RESULT_ACCESS) ] = 0x104000001,	/* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
>> +		[ C(RESULT_MISS)   ] = 0x730000001,	/* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
>> +	},
>> +	[ C(OP_WRITE) ] = {
>> +		[ C(RESULT_ACCESS) ] = 0x104000002,	/* OCR.DEMAND_RFO.LOCAL_DRAM */
>> +		[ C(RESULT_MISS)   ] = 0x730000002,	/* OCR.DEMAND_RFO.REMOTE_DRAM */
>> +	},
>> +	[ C(OP_PREFETCH) ] = {
>> +		[ C(RESULT_ACCESS) ] = 0x0,
>> +		[ C(RESULT_MISS)   ] = 0x0,
>> +	},
>> + },
>> +};
>> +
>>  #define SNB_DMND_DATA_RD	(1ULL << 0)
>>  #define SNB_DMND_RFO		(1ULL << 1)
>>  #define SNB_DMND_IFETCH		(1ULL << 2)
>> @@ -8119,17 +8155,19 @@ __init int intel_pmu_init(void)
>>  
>>  	case INTEL_ICELAKE_X:
>>  	case INTEL_ICELAKE_D:
>> +		memcpy(hw_cache_extra_regs, snc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
>>  		x86_pmu.pebs_ept = 1;
>>  		pmem = true;
>> -		fallthrough;
>> +		goto snc_common;
>>  	case INTEL_ICELAKE_L:
>>  	case INTEL_ICELAKE:
>>  	case INTEL_TIGERLAKE_L:
>>  	case INTEL_TIGERLAKE:
>>  	case INTEL_ROCKETLAKE:
>> +		memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
>> +	snc_common:
>>  		x86_pmu.late_ack = true;
>>  		memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
>> -		memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
>>  		hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
>>  		intel_pmu_lbr_init_skl();
>>