From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: sashiko-reviews@lists.linux.dev
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [Patch v8 02/23] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu()
Date: Mon, 1 Jun 2026 09:40:20 +0800 [thread overview]
Message-ID: <9f80cd55-9559-4fca-b56f-32e744d4fac4@linux.intel.com> (raw)
In-Reply-To: <20260529085116.A92351F0089D@smtp.kernel.org>
On 5/29/2026 4:51 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>
> Pre-existing issues:
> - [High] Use-after-free in `intel_pmu_cpu_dead()` triggered during error rollback if `perf_pmu_register()` fails.
> --
>
> commit a6b6c338247bf2e5f630f8fc0cce5709a4fbe801
> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
>
> perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu()
>
> This patch moves the default hybrid PMU structure initialization before
> calling x86_pmu_starting_cpu(). This change prevents key fields like
> capabilities from being inadvertently overwritten during initialization.
>
>> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
>> index 4b9e105309c6a..17e122e27e0b7 100644
>> --- a/arch/x86/events/core.c
>> +++ b/arch/x86/events/core.c
> [ ... ]
>> @@ -2195,8 +2195,20 @@ static int __init init_hw_perf_events(void)
>>
>> pmu.attr_update = x86_pmu.attr_update;
>>
>> - if (!is_hybrid())
>> + if (!is_hybrid()) {
>> x86_pmu_show_pmu_cap(NULL);
>> + } else {
>> + int i;
>> +
>> + /*
>> + * Init default ops.
>> + * Must be called before registering x86_pmu_starting_cpu(),
>> + * otherwise some key PMU fields, e.g., capabilities
>> + * initialized in x86_pmu_starting_cpu(), would be overwritten.
>> + */
>> + for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
>> + x86_pmu.hybrid_pmu[i].pmu = pmu;
> [Severity: High]
> This is a pre-existing issue, but I noticed a potential use-after-free
> during error rollback.
>
> During init_hw_perf_events(), the CPU hotplug states are set up and
> x86_pmu_starting_cpu() sets cpuc->pmu to point to elements within the
> dynamically allocated x86_pmu.hybrid_pmu array.
>
> If the subsequent perf_pmu_register() loop fails, the error path frees the
> x86_pmu.hybrid_pmu array via kfree() and jumps to out2 to unregister the
> CPU hotplug states:
>
> if (i < x86_pmu.num_hybrid_pmus) {
> ...
> kfree(x86_pmu.hybrid_pmu);
> ...
> goto out2;
> }
> ...
> out:
> cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
>
> Tearing down the CPUHP_PERF_X86_PREPARE state triggers x86_pmu_dead_cpu(),
> which eventually calls intel_pmu_cpu_dead().
>
> Could tearing down CPUHP_PERF_X86_PREPARE evaluate the dangling cpuc->pmu
> pointer in intel_pmu_cpu_dead(), causing cpumask_clear_cpu() to write to
> the array that was just freed?
Yes, it's a bug. Need to check if x86_pmu.num_hybrid_pmus is 0 before
accessing the cpuc->pmu, like this,
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 5013c424a0a2..7aecc86b5788 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6378,7 +6378,7 @@ static void intel_pmu_cpu_dead(int cpu)
release_arch_pebs_buf_on_cpu(cpu);
intel_cpuc_finish(cpuc);
- if (is_hybrid() && cpuc->pmu)
+ if (is_hybrid() && x86_pmu.num_hybrid_pmus && cpuc->pmu)
cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
}
BTW, I would extract these bug fixing and clean-up patches to a separate
patchset and avoid this patchset inflating too much.
Thanks.
>
>> + }
>>
>> if (!x86_pmu.read)
>> x86_pmu.read = _x86_pmu_read;
next prev parent reply other threads:[~2026-06-01 1:40 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 7:56 [Patch v8 00/23] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-05-29 7:56 ` [Patch v8 01/23] perf/x86/intel: Validate return value of intel_pmu_init_hybrid() Dapeng Mi
2026-05-29 8:53 ` sashiko-bot
2026-05-29 11:11 ` Peter Zijlstra
2026-06-01 1:02 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 02/23] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu() Dapeng Mi
2026-05-29 8:51 ` sashiko-bot
2026-06-01 1:40 ` Mi, Dapeng [this message]
2026-05-29 7:56 ` [Patch v8 03/23] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-05-29 7:56 ` [Patch v8 04/23] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-05-29 7:56 ` [Patch v8 05/23] perf: Eliminate duplicate arch-specific functions definations Dapeng Mi
2026-05-29 7:56 ` [Patch v8 06/23] perf/x86: Use x86_perf_regs in the x86 nmi handlers Dapeng Mi
2026-05-29 7:56 ` [Patch v8 07/23] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-05-29 8:56 ` sashiko-bot
2026-05-29 11:32 ` Peter Zijlstra
2026-06-01 2:31 ` Mi, Dapeng
2026-06-01 8:28 ` Peter Zijlstra
2026-05-29 7:56 ` [Patch v8 08/23] x86/fpu: Ensure TIF_NEED_FPU_LOAD is set after saving FPU state Dapeng Mi
2026-05-29 7:56 ` [Patch v8 09/23] perf: Move and enhance has_extended_regs() for arch-specific use Dapeng Mi
2026-05-29 7:56 ` [Patch v8 10/23] perf/x86: Enable XMM Register Sampling for Non-PEBS Events Dapeng Mi
2026-05-29 9:02 ` sashiko-bot
2026-06-01 3:11 ` Mi, Dapeng
2026-05-29 11:38 ` Peter Zijlstra
2026-06-01 3:04 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 11/23] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-05-29 9:24 ` sashiko-bot
2026-06-01 5:57 ` Mi, Dapeng
2026-05-29 11:42 ` Peter Zijlstra
2026-06-01 5:53 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 12/23] perf: Add sampling support for SIMD registers Dapeng Mi
2026-05-29 8:36 ` sashiko-bot
2026-06-01 6:44 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 13/23] perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-05-29 8:49 ` sashiko-bot
2026-06-01 6:57 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 14/23] perf/x86: Support YMM " Dapeng Mi
2026-05-29 8:47 ` sashiko-bot
2026-06-01 7:14 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 15/23] perf/x86: Support ZMM " Dapeng Mi
2026-05-29 7:56 ` [Patch v8 16/23] perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-05-29 9:21 ` sashiko-bot
2026-06-01 7:21 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 17/23] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-05-29 7:56 ` [Patch v8 18/23] perf/x86: Support eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-05-29 9:31 ` sashiko-bot
2026-06-01 8:20 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 19/23] perf/x86: Support SSP " Dapeng Mi
2026-05-29 10:03 ` sashiko-bot
2026-06-01 8:54 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 20/23] perf/x86/intel: Support arch-PEBS based SIMD/eGPRs/SSP sampling Dapeng Mi
2026-05-29 9:45 ` sashiko-bot
2026-06-01 9:08 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 21/23] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-05-29 10:43 ` sashiko-bot
2026-06-01 9:19 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 22/23] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-05-29 9:34 ` sashiko-bot
2026-06-01 9:23 ` Mi, Dapeng
2026-05-29 7:56 ` [Patch v8 23/23] perf/x86/intel: Add sanity check for PEBS fragment size Dapeng Mi
2026-05-29 9:54 ` sashiko-bot
2026-06-01 9:42 ` Mi, Dapeng
2026-05-29 8:32 ` [Patch v8 00/23] Support SIMD/eGPRs/SSP registers sampling for perf Mi, Dapeng
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