Linux Perf Users
 help / color / mirror / Atom feed
From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: sashiko-reviews@lists.linux.dev
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [Patch v9 02/24] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu()
Date: Mon, 6 Jul 2026 16:33:41 +0800	[thread overview]
Message-ID: <afa403c1-2594-49ec-ad12-f1dd1409e29e@linux.intel.com> (raw)
In-Reply-To: <20260706021852.DE2ED1F000E9@smtp.kernel.org>


On 7/6/2026 10:18 AM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>
> Pre-existing issues:
> - [High] Preexisting out-of-bounds read in `check_hw_exists()` on hybrid platforms due to an invalid `container_of()` cast on the global static `pmu` struct via the `hybrid()` macro.
> --
>
> commit 8216e613cee4854e16daaa11279146d17bc7f313
> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
>
> perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu()
>
> The current approach initializes hybrid PMU structures immediately before
> registering them. This is risky as it can lead to key fields being
> inadvertently overwritten. This patch mitigates this by moving the
> default hybrid structure initialization before calling
> x86_pmu_starting_cpu().
>
>> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
>> index 872d07a5fa80d..0888d3b0923e1 100644
>> --- a/arch/x86/events/core.c
>> +++ b/arch/x86/events/core.c
>> @@ -2195,8 +2195,20 @@ static int __init init_hw_perf_events(void)
>>  
>>  	pmu.attr_update = x86_pmu.attr_update;
>>  
>> -	if (!is_hybrid())
>> +	if (!is_hybrid()) {
>>  		x86_pmu_show_pmu_cap(NULL);
>> +	} else {
>> +		int i;
>> +
>> +		/*
>> +		 * Init default ops.
>> +		 * Must be called before registering x86_pmu_starting_cpu(),
>> +		 * otherwise some key PMU fields, e.g., capabilities
>> +		 * initialized in x86_pmu_starting_cpu(), would be overwritten.
>> +		 */
>> +		for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
>> +			x86_pmu.hybrid_pmu[i].pmu = pmu;
>> +	}
> [Severity: High]
> This is a pre-existing issue, but does passing the global pmu struct to
> check_hw_exists() earlier in this function cause an out-of-bounds read on
> hybrid platforms?
>
> In init_hw_perf_events(), check_hw_exists(&pmu, ...) is called after
> perf_is_hybrid is enabled. Inside check_hw_exists(), it iterates over
> fixed counters and calls fixed_counter_disabled():
>
> arch/x86/events/perf_event.h:fixed_counter_disabled() {
>     ...
>     u64 intel_ctrl = hybrid(pmu, intel_ctrl);
>     ...
> }
>
> The hybrid() macro expands to a container_of() cast:
>
>     container_of(_pmu, struct x86_hybrid_pmu, pmu)->_field
>
> Because the pmu passed in is the standalone global struct pmu (not embedded
> within a struct x86_hybrid_pmu), this cast yields an invalid pointer.
>
> Could this read garbage data past the end of the global pmu struct when
> accessing intel_ctrl, potentially causing the BIOS hardware check to act on
> garbage data or trigger a kernel panic if it crosses an unmapped page
> boundary?

Yes, a real issue. It looks unnecessary to run fixed_counter_disabled()
check since intel_ctrl always comes from the the bitwised-or between
cntr_mask64 and fixed_cntr_mask64. Would drop fixed_counter_disabled() and
all calling in a separate patch.

Thanks.


>

  reply	other threads:[~2026-07-06  8:33 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-06  1:54 [Patch v9 00/24] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-07-06  1:54 ` [Patch v9 01/24] perf/x86: Fix two error-path and hybrid PMU guard issues Dapeng Mi
2026-07-06  2:21   ` sashiko-bot
2026-07-06  8:05     ` Mi, Dapeng
2026-07-06  1:54 ` [Patch v9 02/24] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu() Dapeng Mi
2026-07-06  2:18   ` sashiko-bot
2026-07-06  8:33     ` Mi, Dapeng [this message]
2026-07-06  1:54 ` [Patch v9 03/24] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-07-06  1:54 ` [Patch v9 04/24] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-07-06  1:54 ` [Patch v9 05/24] perf: Eliminate duplicate arch-specific function definitions Dapeng Mi
2026-07-06  1:54 ` [Patch v9 06/24] perf/x86: Use x86_perf_regs in NMI handlers Dapeng Mi
2026-07-06  2:31   ` sashiko-bot
2026-07-06  8:43     ` Mi, Dapeng
2026-07-06  1:54 ` [Patch v9 07/24] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-07-06  2:18   ` sashiko-bot
2026-07-06  9:09     ` Mi, Dapeng
2026-07-06  1:54 ` [Patch v9 08/24] x86/fpu: Add update_fpu_state_and_flag() helper Dapeng Mi
2026-07-06  2:22   ` sashiko-bot
2026-07-06  9:15     ` Mi, Dapeng
2026-07-06  1:54 ` [Patch v9 09/24] perf: Move and enhance has_extended_regs() for arch-specific use Dapeng Mi
2026-07-06  1:54 ` [Patch v9 10/24] perf/x86/intel: Consolidate PMU capability updates Dapeng Mi
2026-07-06  1:54 ` [Patch v9 11/24] perf/x86: Enable XMM register sampling for non-PEBS events Dapeng Mi
2026-07-06  2:34   ` sashiko-bot
2026-07-06  9:47     ` Mi, Dapeng
2026-07-06  1:54 ` [Patch v9 12/24] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-07-06  2:35   ` sashiko-bot
2026-07-06  1:54 ` [Patch v9 13/24] perf: Add sampling support for SIMD registers Dapeng Mi
2026-07-06  2:34   ` sashiko-bot
2026-07-06  1:54 ` [Patch v9 14/24] perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-07-06  6:45   ` sashiko-bot
2026-07-06  1:54 ` [Patch v9 15/24] perf/x86: Support YMM " Dapeng Mi
2026-07-06  1:54 ` [Patch v9 16/24] perf/x86: Support ZMM " Dapeng Mi
2026-07-06  1:54 ` [Patch v9 17/24] perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-07-06  1:54 ` [Patch v9 18/24] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-07-06  1:54 ` [Patch v9 19/24] perf/x86: Support eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-07-06  1:54 ` [Patch v9 20/24] perf/x86: Support SSP " Dapeng Mi
2026-07-06  1:54 ` [Patch v9 21/24] perf/x86/intel: Support arch-PEBS based SIMD/eGPRs/SSP sampling Dapeng Mi
2026-07-06  1:54 ` [Patch v9 22/24] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-07-06  2:57   ` sashiko-bot
2026-07-06  1:54 ` [Patch v9 23/24] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-07-06  1:54 ` [Patch v9 24/24] perf/x86/intel: Add sanity check for PEBS fragment size Dapeng Mi
2026-07-06  5:04   ` sashiko-bot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=afa403c1-2594-49ec-ad12-f1dd1409e29e@linux.intel.com \
    --to=dapeng1.mi@linux.intel.com \
    --cc=linux-perf-users@vger.kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox