Linux-PHY Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Konrad Dybcio <konrad.dybcio@somainline.org>,
	Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org
Subject: [PATCH v1 19/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers
Date: Tue,  5 Jul 2022 12:43:11 +0300	[thread overview]
Message-ID: <20220705094320.1313312-20-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220705094320.1313312-1-dmitry.baryshkov@linaro.org>

Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h    | 17 ++++++++++++
 .../qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h    | 17 ++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h | 15 +++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h           | 27 ++++---------------
 4 files changed, 54 insertions(+), 22 deletions(-)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
 create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
 create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
new file mode 100644
index 000000000000..af273602998e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+
+#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1			0x0a0
+#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME		0x0f0
+#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME		0x0f4
+#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2		0x0fc
+#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5		0x108
+#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2		0x824
+#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2		0x828
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
new file mode 100644
index 000000000000..1eedf50cf9cb
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
+
+/* Only for QMP V5_20 PHY - PCIe PCS registers */
+#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x01c
+#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS		0x090
+#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1			0x0a0
+#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5		0x108
+#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN			0x15c
+#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3	0x184
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
new file mode 100644
index 000000000000..08c3dd115488
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V4_20_H_
+#define QCOM_PHY_QMP_PCS_V4_20_H_
+
+/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
+#define QPHY_V4_20_PCS_RX_SIGDET_LVL			0x188
+#define QPHY_V4_20_PCS_EQ_CONFIG2			0x1d8
+#define QPHY_V4_20_PCS_EQ_CONFIG4			0x1e0
+#define QPHY_V4_20_PCS_EQ_CONFIG5			0x1e4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1f8684c87c06..cdbbcf6b5686 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -32,11 +32,16 @@
 #include "phy-qcom-qmp-pcs-usb-v4.h"
 #include "phy-qcom-qmp-pcs-ufs-v4.h"
 
+#include "phy-qcom-qmp-pcs-v4_20.h"
+#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
+
 #include "phy-qcom-qmp-pcs-v5.h"
 #include "phy-qcom-qmp-pcs-pcie-v5.h"
 #include "phy-qcom-qmp-pcs-usb-v5.h"
 #include "phy-qcom-qmp-pcs-ufs-v5.h"
 
+#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
+
 #include "phy-qcom-qmp-pcie-qhp.h"
 
 /* Only for QMP V3 & V4 PHY - DP COM registers */
@@ -121,12 +126,6 @@
 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS		0x0d8
 #define QSERDES_V4_DP_PHY_STATUS			0x0dc
 
-/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
-#define QPHY_V4_20_PCS_RX_SIGDET_LVL			0x188
-#define QPHY_V4_20_PCS_EQ_CONFIG2			0x1d8
-#define QPHY_V4_20_PCS_EQ_CONFIG4			0x1e0
-#define QPHY_V4_20_PCS_EQ_CONFIG5			0x1e4
-
 /* Only for QMP V4 PHY - PCS_MISC registers */
 #define QPHY_V4_PCS_MISC_TYPEC_CTRL			0x00
 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL		0x04
@@ -135,20 +134,4 @@
 #define QPHY_V4_PCS_MISC_TYPEC_STATUS			0x10
 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS		0x14
 
-#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1			0x0a0
-#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME		0x0f0
-#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME		0x0f4
-#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2		0x0fc
-#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5		0x108
-#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2		0x824
-#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2		0x828
-
-/* Only for QMP V5_20 PHY - PCIe PCS registers */
-#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x01c
-#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS		0x090
-#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1			0x0a0
-#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5		0x108
-#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN			0x15c
-#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3	0x184
-
 #endif
-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  parent reply	other threads:[~2022-07-05 10:45 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-05  9:42 [PATCH v1 00/28] phy: qcom-qmp: split register tables Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 01/28] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 02/28] phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 03/28] phy: qcom-qmp-combo,usb: add support for separate PCS_USB region Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 04/28] phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3 Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 05/28] phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 06/28] phy: qcom-qmp: rename QMP V2 PCS registers Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 07/28] phy: qcom-qmp: use QPHY_V4_PCS for ipq6018/ipq8074 PCIe gen3 Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 08/28] phy: qcom-qmp: move QSERDES registers to separate header Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 09/28] phy: qcom-qmp: move QSERDES V3 registers to separate headers Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 10/28] phy: qcom-qmp: move QSERDES V4 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 11/28] phy: qcom-qmp: move QSERDES V5 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 12/28] phy: qcom-qmp: move QSERDES PLL registers to separate header Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 13/28] phy: qcom-qmp: move PCS V2 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 14/28] phy: qcom-qmp: move PCS V3 registers to separate headers Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 15/28] phy: qcom-qmp: move PCS V4 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 16/28] phy: qcom-qmp: move PCS V5 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 17/28] phy: qcom-qmp: move PCIE QHP registers to separate header Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 18/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers Dmitry Baryshkov
2022-07-05  9:43 ` Dmitry Baryshkov [this message]
2022-07-05  9:43 ` [PATCH v1 20/28] phy: qcom-qmp: split PCS_UFS V3 symbols to separate header Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 21/28] phy: qcom-qmp: qserdes-com: add missing registers Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 22/28] phy: qcom-qmp: qserdes-com-v3: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 23/28] phy: qcom-qmp: qserdes-com-v4: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 24/28] phy: qcom-qmp: qserdes-com-v5: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 25/28] phy: qcom-qmp: pcs-v3: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 26/28] phy: qcom-qmp: pcs-pcie-v4: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 27/28] phy: qcom-qmp-usb: replace FLL layout writes for msm8996 Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register Dmitry Baryshkov
2022-07-07  5:02 ` [PATCH v1 00/28] phy: qcom-qmp: split register tables Vinod Koul

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220705094320.1313312-20-dmitry.baryshkov@linaro.org \
    --to=dmitry.baryshkov@linaro.org \
    --cc=agross@kernel.org \
    --cc=bjorn.andersson@linaro.org \
    --cc=kishon@ti.com \
    --cc=konrad.dybcio@somainline.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-phy@lists.infradead.org \
    --cc=p.zabel@pengutronix.de \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox