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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Konrad Dybcio <konrad.dybcio@somainline.org>,
	Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org
Subject: [PATCH v1 04/28] phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3
Date: Tue,  5 Jul 2022 12:42:56 +0300	[thread overview]
Message-ID: <20220705094320.1313312-5-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220705094320.1313312-1-dmitry.baryshkov@linaro.org>

Follow the example of other PCIe PHYs and use separate pcs_misc region
to access PCS_PCIE_* resources.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c |  9 +++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h      | 32 ++++++++++++------------
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 616be76f4ab0..d56357e2df4f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -361,6 +361,9 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
 	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 	QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
 	QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
+};
+
+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
 	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
 	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 	QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
@@ -1593,6 +1596,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
 	.rx_tbl_num		= ARRAY_SIZE(ipq6018_pcie_rx_tbl),
 	.pcs_tbl		= ipq6018_pcie_pcs_tbl,
 	.pcs_tbl_num		= ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
+	.pcs_misc_tbl		= ipq6018_pcie_pcs_misc_tbl,
+	.pcs_misc_tbl_num	= ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
 	.clk_list		= ipq8074_pciephy_clk_l,
 	.num_clks		= ARRAY_SIZE(ipq8074_pciephy_clk_l),
 	.reset_list		= ipq8074_pciephy_reset_l,
@@ -2374,6 +2379,10 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
 		qphy->pcs_misc = of_iomap(np, 3);
 	}
 
+	if (!qphy->pcs_misc &&
+	    of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
+		qphy->pcs_misc = qphy->pcs + 0x400;
+
 	if (!qphy->pcs_misc)
 		dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
 
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index c07227f352b3..adb155a45923 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -121,22 +121,22 @@
 
 /* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
 
-#define PCS_PCIE_POWER_STATE_CONFIG2			0x40c
-#define PCS_PCIE_POWER_STATE_CONFIG4			0x414
-#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE			0x41c
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L		0x440
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H		0x444
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L		0x448
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H		0x44c
-#define PCS_PCIE_OSC_DTCT_CONFIG2			0x45c
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2			0x478
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4			0x480
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5			0x484
-#define PCS_PCIE_OSC_DTCT_ACTIONS			0x490
-#define PCS_PCIE_EQ_CONFIG1				0x4a0
-#define PCS_PCIE_EQ_CONFIG2				0x4a4
-#define PCS_PCIE_PRESET_P10_PRE				0x4bc
-#define PCS_PCIE_PRESET_P10_POST			0x4e0
+#define PCS_PCIE_POWER_STATE_CONFIG2			0x00c
+#define PCS_PCIE_POWER_STATE_CONFIG4			0x014
+#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE			0x01c
+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L		0x040
+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H		0x044
+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L		0x048
+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H		0x04c
+#define PCS_PCIE_OSC_DTCT_CONFIG2			0x05c
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2			0x078
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4			0x080
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5			0x084
+#define PCS_PCIE_OSC_DTCT_ACTIONS			0x090
+#define PCS_PCIE_EQ_CONFIG1				0x0a0
+#define PCS_PCIE_EQ_CONFIG2				0x0a4
+#define PCS_PCIE_PRESET_P10_PRE				0x0bc
+#define PCS_PCIE_PRESET_P10_POST			0x0e0
 
 /* Only for QMP V2 PHY - QSERDES COM registers */
 #define QSERDES_COM_BG_TIMER				0x00c
-- 
2.35.1


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  parent reply	other threads:[~2022-07-05 10:45 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-05  9:42 [PATCH v1 00/28] phy: qcom-qmp: split register tables Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 01/28] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 02/28] phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 03/28] phy: qcom-qmp-combo,usb: add support for separate PCS_USB region Dmitry Baryshkov
2022-07-05  9:42 ` Dmitry Baryshkov [this message]
2022-07-05  9:42 ` [PATCH v1 05/28] phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 06/28] phy: qcom-qmp: rename QMP V2 PCS registers Dmitry Baryshkov
2022-07-05  9:42 ` [PATCH v1 07/28] phy: qcom-qmp: use QPHY_V4_PCS for ipq6018/ipq8074 PCIe gen3 Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 08/28] phy: qcom-qmp: move QSERDES registers to separate header Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 09/28] phy: qcom-qmp: move QSERDES V3 registers to separate headers Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 10/28] phy: qcom-qmp: move QSERDES V4 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 11/28] phy: qcom-qmp: move QSERDES V5 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 12/28] phy: qcom-qmp: move QSERDES PLL registers to separate header Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 13/28] phy: qcom-qmp: move PCS V2 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 14/28] phy: qcom-qmp: move PCS V3 registers to separate headers Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 15/28] phy: qcom-qmp: move PCS V4 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 16/28] phy: qcom-qmp: move PCS V5 " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 17/28] phy: qcom-qmp: move PCIE QHP registers to separate header Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 18/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 19/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 20/28] phy: qcom-qmp: split PCS_UFS V3 symbols to separate header Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 21/28] phy: qcom-qmp: qserdes-com: add missing registers Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 22/28] phy: qcom-qmp: qserdes-com-v3: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 23/28] phy: qcom-qmp: qserdes-com-v4: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 24/28] phy: qcom-qmp: qserdes-com-v5: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 25/28] phy: qcom-qmp: pcs-v3: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 26/28] phy: qcom-qmp: pcs-pcie-v4: " Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 27/28] phy: qcom-qmp-usb: replace FLL layout writes for msm8996 Dmitry Baryshkov
2022-07-05  9:43 ` [PATCH v1 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register Dmitry Baryshkov
2022-07-07  5:02 ` [PATCH v1 00/28] phy: qcom-qmp: split register tables Vinod Koul

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