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From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <robh+dt@kernel.org>, <lee.jones@linaro.org>,
	<krzysztof.kozlowski@linaro.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <kishon@ti.com>,
	<vkoul@kernel.org>, <dan.carpenter@oracle.com>,
	<grygorii.strashko@ti.com>, <rogerq@kernel.org>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-phy@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>, <sjakhade@cadence.com>,
	<s-vadapalli@ti.com>
Subject: [PATCH 2/6] phy: ti: gmii-sel: Add support for configuring CPSW5G ports in SGMII mode
Date: Wed, 14 Sep 2022 15:09:07 +0530	[thread overview]
Message-ID: <20220914093911.187764-3-s-vadapalli@ti.com> (raw)
In-Reply-To: <20220914093911.187764-1-s-vadapalli@ti.com>

CPSW5G ports on J7200 support SGMII mode. Add support to the phy-gmii-sel
driver to configure the CPSW5G ports in SGMII mode.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 drivers/phy/ti/phy-gmii-sel.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 0bcfd6d96b4d..f0b2ba7a9c96 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -23,6 +23,7 @@
 #define AM33XX_GMII_SEL_MODE_RGMII	2
 
 /* J72xx SoC specific definitions for the CONTROL port */
+#define J72XX_GMII_SEL_MODE_SGMII	3
 #define J72XX_GMII_SEL_MODE_QSGMII	4
 #define J72XX_GMII_SEL_MODE_QSGMII_SUB	6
 
@@ -105,6 +106,13 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
 			gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB;
 		break;
 
+	case PHY_INTERFACE_MODE_SGMII:
+		if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII)))
+			goto unsupported;
+		else
+			gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII;
+		break;
+
 	default:
 		goto unsupported;
 	}
@@ -212,7 +220,7 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
-	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
 };
 
 static const struct of_device_id phy_gmii_sel_id_table[] = {
-- 
2.25.1


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  parent reply	other threads:[~2022-09-14  9:45 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-14  9:39 [PATCH 0/6] Add support for J721e CPSW9G and SGMII mode Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e Siddharth Vadapalli
2022-09-14 16:15   ` Rob Herring
2022-09-15  5:28     ` Siddharth Vadapalli
2022-09-19 10:17       ` Krzysztof Kozlowski
2022-09-20  4:56         ` Siddharth Vadapalli
2022-09-21  6:36           ` Krzysztof Kozlowski
2022-09-19 10:15   ` Krzysztof Kozlowski
2022-09-20  4:27     ` Siddharth Vadapalli
2022-09-21  6:39       ` Krzysztof Kozlowski
2022-09-21  7:23         ` Siddharth Vadapalli
2022-09-14  9:39 ` Siddharth Vadapalli [this message]
2022-09-14  9:39 ` [PATCH 3/6] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e Siddharth Vadapalli
2022-09-14 11:34   ` Roger Quadros
2022-09-15  6:19     ` Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 4/6] phy: ti: gmii-sel: Enable SGMII mode configuration for J721E Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 5/6] phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver " Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 6/6] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration Siddharth Vadapalli

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