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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>,
	krzysztof.kozlowski+dt@linaro.org, Rob Herring <robh@kernel.org>
Cc: lee.jones@linaro.org, kishon@ti.com, vkoul@kernel.org,
	dan.carpenter@oracle.com, rogerq@kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-phy@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, sjakhade@cadence.com
Subject: Re: [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e
Date: Wed, 21 Sep 2022 08:36:43 +0200	[thread overview]
Message-ID: <da0d5f12-78fd-b09f-d1c5-2df46cb98901@linaro.org> (raw)
In-Reply-To: <2f830a26-c9f0-2902-302c-371c59994a6f@ti.com>

On 20/09/2022 06:56, Siddharth Vadapalli wrote:
>>> Thank you for reviewing the patch. Based on the discussion for the
>>> previous series at [1], I had planned to reuse the same property
>>> "ti,qsgmii-main-ports" for TI's J721e device too. The reason for this is
>>> that the property represents the same feature on both devices which is
>>> that of the QSGMII main port. The only difference between the two of
>>> them is that J7200's CPSW5G has 4 external ports while J721e's CPSW9G
>>> has 8 external ports. Thus, J7200 can have at most one QSGMII main port
>>> while J721e can have up to two. Adding a new property which describes
>>> the same feature appears to be redundant to me. Please let me know.
>>>
>>
>> The trouble is that you wrote the description like it were two different
>> properties (for xx this is one element, for yy this is something else).
>> You need to describe the property in unified way.
> 
> Thank you for reviewing the patch. I plan to update the description to
> the following:
> "Required only for QSGMII mode. Array to select the port/s for QSGMII
> main mode. The size of the array corresponds to the number of QSGMII
> interfaces and thus, the number of distinct QSGMII main ports, supported
> by the device. If the device supports two QSGMII interfaces but only one
> QSGMII interface is desired, repeat the QSGMII main port value
> corresponding to the QSGMII interface in the array."
> 
> I intend to describe the property in detail to help users understand the
> property and its usage better. In the process, I might have
> unintentionally made it appear as two different properties in the
> previous description. I hope the new description shows that the property
> describes the same feature across devices while making its usage clear
> to the users at the same time. Please let me know if this is fine.

Sounds good to me.

Best regards,
Krzysztof

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  reply	other threads:[~2022-09-21  6:36 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-14  9:39 [PATCH 0/6] Add support for J721e CPSW9G and SGMII mode Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e Siddharth Vadapalli
2022-09-14 16:15   ` Rob Herring
2022-09-15  5:28     ` Siddharth Vadapalli
2022-09-19 10:17       ` Krzysztof Kozlowski
2022-09-20  4:56         ` Siddharth Vadapalli
2022-09-21  6:36           ` Krzysztof Kozlowski [this message]
2022-09-19 10:15   ` Krzysztof Kozlowski
2022-09-20  4:27     ` Siddharth Vadapalli
2022-09-21  6:39       ` Krzysztof Kozlowski
2022-09-21  7:23         ` Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 2/6] phy: ti: gmii-sel: Add support for configuring CPSW5G ports in SGMII mode Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 3/6] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e Siddharth Vadapalli
2022-09-14 11:34   ` Roger Quadros
2022-09-15  6:19     ` Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 4/6] phy: ti: gmii-sel: Enable SGMII mode configuration for J721E Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 5/6] phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver " Siddharth Vadapalli
2022-09-14  9:39 ` [PATCH 6/6] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration Siddharth Vadapalli

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