Re: [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e

From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>, Rob Herring <robh@kernel.org>
Cc: lee.jones@linaro.org, krzysztof.kozlowski+dt@linaro.org,
	kishon@ti.com, vkoul@kernel.org, dan.carpenter@oracle.com,
	grygorii.strashko@ti.com, rogerq@kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-phy@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, sjakhade@cadence.com
Subject: Re: [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e
Date: Mon, 19 Sep 2022 12:17:14 +0200	[thread overview]
Message-ID: <31028736-ba81-122e-b630-b66e9d9d491a@linaro.org> (raw)
In-Reply-To: <d48e5ef4-6d5b-0977-ed45-de810e42356c@ti.com>

On 15/09/2022 07:28, Siddharth Vadapalli wrote:
>>> @@ -65,12 +66,19 @@ properties:
>>>      description: |
>>>        Required only for QSGMII mode. Array to select the port for
>>>        QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
>>> -      ports automatically. Any one of the 4 CPSW5G ports can act as the
>>> -      main port with the rest of them being the QSGMII_SUB ports.
>>> -    maxItems: 1
>>> -    items:
>>> -      minimum: 1
>>> -      maximum: 4
>>> +      ports automatically. For J7200 CPSW5G with the compatible:
>>> +      ti,j7200-cpsw5g-phy-gmii-sel, ti,qsgmii-main-ports is an
>>> +      array of only one element, which is the port number ranging from
>>> +      1 to 4. For J721e CPSW9G with the compatible:
>>> +      ti,j721e-cpsw9g-phy-gmii-sel, ti,qsgmii-main-ports is an array
>>> +      of two elements, which corresponds to two potential QSGMII main
>>> +      ports. The first element and second element of the array can both
>>> +      range from 1 to 8 each, corresponding to two QSGMII main ports.
>>> +      For J721e CPSW9G, to configure port 2 as the first QSGMII main
>>> +      port and port 7 as the second QSGMII main port, we specify:
>>> +      ti,qsgmii-main-ports = <2>, <7>;
>>> +      If only one QSGMII main port is desired, mention the same main
>>> +      port twice.
>>
>> Two different forms for the same property name is not great. Just make a 
>> new property if you need something different.
> 
> Thank you for reviewing the patch. Based on the discussion for the
> previous series at [1], I had planned to reuse the same property
> "ti,qsgmii-main-ports" for TI's J721e device too. The reason for this is
> that the property represents the same feature on both devices which is
> that of the QSGMII main port. The only difference between the two of
> them is that J7200's CPSW5G has 4 external ports while J721e's CPSW9G
> has 8 external ports. Thus, J7200 can have at most one QSGMII main port
> while J721e can have up to two. Adding a new property which describes
> the same feature appears to be redundant to me. Please let me know.
> 

The trouble is that you wrote the description like it were two different
properties (for xx this is one element, for yy this is something else).
You need to describe the property in unified way.

Best regards,
Krzysztof

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