From: Konrad Dybcio <konradybcio@kernel.org>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH 0/6] X1P42100 DT and PCIe PHY bits
Date: Sat, 25 Jan 2025 04:31:16 +0100 [thread overview]
Message-ID: <20250125-topic-x1p4_dts-v1-0-02659a08b044@oss.qualcomm.com> (raw)
X1P42100 is a(n indirect) derivative of X1E80100 - the silicon is
actually different and it's not a fused down part.
Introduce the DTS bits required to support it by mostly reusing the
X1E SoC and CRD DTSIs. The most notable differences from our software
PoV are a different GPU (support for which will be added later), 4
less CPUs and some nuances in the PCIe hardware.
This series very strictly depends on the NOCSR PCIe PHY reset patches.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Konrad Dybcio (6):
dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY
dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints
phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY
arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets
arm64: dts: qcom: Commonize X1 CRD DTSI
arm64: dts: qcom: Add X1P42100 SoC and CRD
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 26 +-
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../dts/qcom/{x1e80100-crd.dts => x1-crd.dtsi} | 7 -
arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 1270 +-------------------
arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 2 +-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 44 +-
arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 17 +
arch/arm64/boot/dts/qcom/x1p42100.dtsi | 81 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 +
9 files changed, 148 insertions(+), 1318 deletions(-)
---
base-commit: d7dfdec72fb32629d1affc32ff37a66a7fd1fb53
change-id: 20250125-topic-x1p4_dts-3b9509bce3a3
prerequisite-message-id: 20250121094140.4006801-1-quic_wenbyao@quicinc.com
prerequisite-patch-id: 719a1c1319a8f25be57f1e9bc68887684ff0d7cd
prerequisite-patch-id: 44ff71b8033fc91867a83a2f8f063fd0d9951d5e
Best regards,
--
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next reply other threads:[~2025-01-25 3:31 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-25 3:31 Konrad Dybcio [this message]
2025-01-25 3:31 ` [PATCH 1/6] dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY Konrad Dybcio
2025-01-27 8:24 ` Krzysztof Kozlowski
2025-01-25 3:31 ` [PATCH 2/6] dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints Konrad Dybcio
2025-01-27 8:26 ` Krzysztof Kozlowski
2025-02-01 15:56 ` Konrad Dybcio
2025-02-02 14:35 ` Krzysztof Kozlowski
2025-02-03 13:03 ` Konrad Dybcio
2025-02-03 14:17 ` Krzysztof Kozlowski
2025-01-25 3:31 ` [PATCH 3/6] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY Konrad Dybcio
2025-01-25 17:30 ` Dmitry Baryshkov
2025-01-26 7:29 ` Manivannan Sadhasivam
2025-01-26 11:39 ` Dmitry Baryshkov
2025-01-26 16:32 ` Manivannan Sadhasivam
2025-01-26 21:43 ` Dmitry Baryshkov
2025-01-27 5:34 ` Manivannan Sadhasivam
2025-01-27 14:24 ` Dmitry Baryshkov
2025-01-25 3:31 ` [PATCH 4/6] arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets Konrad Dybcio
2025-01-25 17:32 ` Dmitry Baryshkov
2025-01-25 3:31 ` [PATCH 5/6] arm64: dts: qcom: Commonize X1 CRD DTSI Konrad Dybcio
2025-01-25 3:31 ` [PATCH 6/6] arm64: dts: qcom: Add X1P42100 SoC and CRD Konrad Dybcio
2025-01-29 18:10 ` [PATCH 0/6] X1P42100 DT and PCIe PHY bits Jens Glathe
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