Re: [PATCH 3/6] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
	Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: Re: [PATCH 3/6] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY
Date: Mon, 27 Jan 2025 11:04:12 +0530	[thread overview]
Message-ID: <20250127053412.anbdj6hgwcmkildf@thinkpad> (raw)
In-Reply-To: <CAA8EJpq-aNVhSc0fTf4zD63VgrzDokR5uvdGiPvecaBHXYtd+Q@mail.gmail.com>

On Sun, Jan 26, 2025 at 11:43:38PM +0200, Dmitry Baryshkov wrote:
> On Sun, 26 Jan 2025 at 18:32, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > On Sun, Jan 26, 2025 at 01:39:05PM +0200, Dmitry Baryshkov wrote:
> > > On Sun, Jan 26, 2025 at 12:59:52PM +0530, Manivannan Sadhasivam wrote:
> > > >
> > > >
> > > > On January 25, 2025 11:00:23 PM GMT+05:30, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > > > >On Sat, Jan 25, 2025 at 04:31:19AM +0100, Konrad Dybcio wrote:
> > > > >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > > > >>
> > > > >> Add a new, common configuration for Gen4x4 V6 PHYs without an init
> > > > >> sequence.
> > > > >>
> > > > >> The bootloader configures the hardware once and the OS retains that
> > > > >> configuration by using the NOCSR reset line (which doesn't drop
> > > > >> register state on assert) in place of the "full reset" one.
> > > > >
> > > > >I know your opinion, but my 2c would still be for not depending on the
> > > > >bootloader. I think that was the rule for ages for many possible
> > > > >reasons.
> > > > >
> > > >
> > > > But if Linux or other OS can trust the bootloader, then it makes perfect sense to rely on them. Obviously, the question here is that on which platforms this level of trust should be established. And the answer I got was starting from the compute platforms (atleast X1E).
> > >
> > > Is there any way how those values can be lost that we still might want
> > > to support ? The GDSC going to the OFF state? Some deep sleep state or a
> > > power collapse? Actual suspend to RAM (instead of current S2Idle)?
> > >
> >
> > As per Konrad's reply to my identical question, PHY register state is supposed
> > to be maintained by MX domain even during CX PC. This seem to be case on X1E
> > based platforms (compute).
> 
> Is MX on during S2RAM?
> 

Qcom says that their current s2idle implementation is equal to S2RAM (when CX PC
is achieved). In that sense, yes, MX is ON during S2RAM. Do note that, on
majority of the platforms, MX is the AON (Always ON) domain.

- Mani

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