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From: Konrad Dybcio <konradybcio@kernel.org>
To: Vinod Koul <vkoul@kernel.org>,
	 Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	 Konrad Dybcio <konradybcio@kernel.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
	 linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH 4/6] arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets
Date: Sat, 25 Jan 2025 04:31:20 +0100	[thread overview]
Message-ID: <20250125-topic-x1p4_dts-v1-4-02659a08b044@oss.qualcomm.com> (raw)
In-Reply-To: <20250125-topic-x1p4_dts-v1-0-02659a08b044@oss.qualcomm.com>

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Asserting the NOCSR reset line keeps the PHY registers in tact.
This allows us to avoid programming long tables of magic values in the
operating system.

Wire up these resets to PCIe PHY4 and 5 (it's there on the others).

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 9d38436763432892ceef95daf0335d4cf446357c..a244cbb84aecc23ce11414c41f2e5d0905f455ee 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3558,8 +3558,10 @@ pcie5_phy: phy@1c06000 {
 				      "pipe",
 				      "pipediv2";
 
-			resets = <&gcc GCC_PCIE_5_PHY_BCR>;
-			reset-names = "phy";
+			resets = <&gcc GCC_PCIE_5_PHY_BCR>,
+				 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
+			reset-names = "phy",
+				      "phy_nocsr";
 
 			assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
 			assigned-clock-rates = <100000000>;
@@ -3692,8 +3694,10 @@ pcie4_phy: phy@1c0e000 {
 				      "pipe",
 				      "pipediv2";
 
-			resets = <&gcc GCC_PCIE_4_PHY_BCR>;
-			reset-names = "phy";
+			resets = <&gcc GCC_PCIE_4_PHY_BCR>,
+				 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
+			reset-names = "phy",
+				      "phy_nocsr";
 
 			assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
 			assigned-clock-rates = <100000000>;

-- 
2.48.1


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  parent reply	other threads:[~2025-01-25  3:31 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-25  3:31 [PATCH 0/6] X1P42100 DT and PCIe PHY bits Konrad Dybcio
2025-01-25  3:31 ` [PATCH 1/6] dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY Konrad Dybcio
2025-01-27  8:24   ` Krzysztof Kozlowski
2025-01-25  3:31 ` [PATCH 2/6] dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints Konrad Dybcio
2025-01-27  8:26   ` Krzysztof Kozlowski
2025-02-01 15:56     ` Konrad Dybcio
2025-02-02 14:35       ` Krzysztof Kozlowski
2025-02-03 13:03         ` Konrad Dybcio
2025-02-03 14:17           ` Krzysztof Kozlowski
2025-01-25  3:31 ` [PATCH 3/6] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY Konrad Dybcio
2025-01-25 17:30   ` Dmitry Baryshkov
2025-01-26  7:29     ` Manivannan Sadhasivam
2025-01-26 11:39       ` Dmitry Baryshkov
2025-01-26 16:32         ` Manivannan Sadhasivam
2025-01-26 21:43           ` Dmitry Baryshkov
2025-01-27  5:34             ` Manivannan Sadhasivam
2025-01-27 14:24               ` Dmitry Baryshkov
2025-01-25  3:31 ` Konrad Dybcio [this message]
2025-01-25 17:32   ` [PATCH 4/6] arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets Dmitry Baryshkov
2025-01-25  3:31 ` [PATCH 5/6] arm64: dts: qcom: Commonize X1 CRD DTSI Konrad Dybcio
2025-01-25  3:31 ` [PATCH 6/6] arm64: dts: qcom: Add X1P42100 SoC and CRD Konrad Dybcio
2025-01-29 18:10 ` [PATCH 0/6] X1P42100 DT and PCIe PHY bits Jens Glathe

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