* Re: [RESEND 1/1] phy: freescale: imx8qm-hsio: provide regmap names
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
To: Neil Armstrong, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Alexander Stein
Cc: linux-phy, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20260211144949.1128122-1-alexander.stein@ew.tq-group.com>
On Wed, 11 Feb 2026 15:49:48 +0100, Alexander Stein wrote:
> This driver uses multiple regmaps, which will causes name conflicts
> in debugfs like:
> debugfs: '5f1a0000.phy' already exists in 'regmap'
> Fix this by using a dedicated regmap config for each resource, each
> having a dedicated regmap name.
>
>
> [...]
Applied, thanks!
[1/1] phy: freescale: imx8qm-hsio: provide regmap names
commit: 057c81a17fffb17f66e5b4524d49b7caad3fe627
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* Re: [PATCHv2 0/2] phy: miphy28lp: build and simplify allocation
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
To: linux-phy, Rosen Penev
Cc: Neil Armstrong, Patrice Chotard, Kees Cook, Gustavo A. R. Silva,
linux-kernel, linux-arm-kernel, linux-hardening
In-Reply-To: <20260306222457.8400-1-rosenp@gmail.com>
On Fri, 06 Mar 2026 14:24:55 -0800, Rosen Penev wrote:
> First patch allows compilation on at least x86.
>
> Second uses a flexible array member to simplify allocation.
>
> v2: add first patch and fix second.
>
> Rosen Penev (2):
> phy: miphy28lp: add COMPILE_TEST
> phy: miphy28lp: kzalloc + kcalloc to single kzalloc
>
> [...]
Applied, thanks!
[1/2] phy: miphy28lp: add COMPILE_TEST
commit: cc68a1728abfcbde12d36015f244046ae74ddd44
[2/2] phy: miphy28lp: kzalloc + kcalloc to single kzalloc
commit: f3508a61c892c592e4e893a3681e568a5c671027
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* Re: [PATCH v9] phy: Add generic PHY driver used by MACB/GEM on EyeQ5
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
To: Neil Armstrong, Théo Lebrun
Cc: linux-phy, linux-kernel, linux-mips, Vladimir Kondratiev,
Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
Thomas Petazzoni, Luca Ceresoli
In-Reply-To: <20260309-macb-phy-v9-0-5afd87d9db43@bootlin.com>
On Mon, 09 Mar 2026 15:37:33 +0100, Théo Lebrun wrote:
> EyeQ5 SoCs integrate two GEM instances. A system-controller register
> region named "OLB" has some control over the Ethernet PHY integration.
>
> Extend the current OLB ecosystem with a new generic PHY driver.
> - OLB is carried by one main platform driver: clk-eyeq.
> - It instantiates auxiliary devices: reset-eyeq & pinctrl-eyeq5.
> - We add a new one: phy-eyeq5-eth.
>
> [...]
Applied, thanks!
[1/1] phy: Add driver for EyeQ5 Ethernet PHY wrapper
commit: b6e33443876d0ca7e93cf949455e3c1a1a0aae24
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* Re: [PATCH v2] phy: renesas: phy-rzg3e-usb3: Fix malformed MODULE_AUTHOR string
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
To: Biju
Cc: Biju Das, Neil Armstrong, Geert Uytterhoeven, linux-phy,
linux-kernel, Prabhakar Mahadev Lad, linux-renesas-soc,
Pavel Machek
In-Reply-To: <20260319063211.5056-1-biju.das.jz@bp.renesas.com>
On Thu, 19 Mar 2026 06:32:07 +0000, Biju wrote:
> Fix a malformed MODULE_AUTHOR macro in the RZ/G3E USB3.0 PHY driver where
> the author's name and opening angle bracket were missing, leaving only the
> email address with a stray closing >. Correct it to the standard Name
> <email> format.
>
>
Applied, thanks!
[1/1] phy: renesas: phy-rzg3e-usb3: Fix malformed MODULE_AUTHOR string
commit: 53f60930e3d20883364fc01fd46b6099acb8127a
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* Re: [PATCH] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Abel Vesa
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260318-eliza-bindings-qmp-phy-v1-1-96a0d529ad2d@oss.qualcomm.com>
On Wed, 18 Mar 2026 11:54:36 +0200, Abel Vesa wrote:
> Document the compatible for the USB QMP PHY found on the Qualcomm Eliza
> SoC.
>
> It is fully compatible with the one found on Qualcomm SM8650, so add it
> with the SM8650 as fallback.
>
>
> [...]
Applied, thanks!
[1/1] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
commit: d67a337d28a2d852ff539e983ad6790caf9c95f5
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* Re: [PATCH phy-next 0/3] Lynx 28G: better init(), exit(), power_on(), power_off()
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
To: linux-phy, Vladimir Oltean
Cc: netdev, Ioana Ciornei, Neil Armstrong, Josua Mayer, linux-kernel
In-Reply-To: <20260321011451.1557091-1-vladimir.oltean@nxp.com>
On Sat, 21 Mar 2026 03:14:48 +0200, Vladimir Oltean wrote:
> This is a set of 3 improvements to the 28G Lynx SerDes driver as found
> on NXP Layerscape:
> - avoid kernel hangs if lane resets/halts fail due to other bugs
> - actually have phy_power_down() cut power from lanes, not just halt them
> - allow consumers to call phy_exit(), to balance the phy->init_count
>
> Especially change 3 will allow further development of the dpaa2-eth
> consumer. To permit phy_exit() and other patches in net-next to be
> submitted in this development cycle without functionally breaking
> networking, please apply this change on top of v7.0-rc1 and provide
> it as a stable tag to be pulled in netdev.
>
> [...]
Applied, thanks!
[1/3] phy: lynx-28g: use timeouts when waiting for lane halt and reset
commit: 905780855a320ab3dcf0e4eaebf544cb3e7b55f8
[2/3] phy: lynx-28g: truly power the lanes up or down
commit: 5d38f693f16a0e9470fda530e01994f35fed8644
[3/3] phy: lynx-28g: implement phy_exit() operation
commit: 0ee5cc59c0ee679e1a3a749cfc47834041763494
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* Re: [PATCH v2] phy: qcom: m31-eusb2: Make USB repeater optional
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
To: Neil Armstrong, Abel Vesa
Cc: linux-arm-msm, linux-phy, linux-kernel, Wesley Cheng,
Dmitry Baryshkov, Bjorn Andersson
In-Reply-To: <20260302-phy-qcom-m31-eusb2-make-repeater-optional-v2-1-dbf714c72056@oss.qualcomm.com>
On Mon, 02 Mar 2026 10:34:46 +0200, Abel Vesa wrote:
> A repeater is not required for the PHY to function. On systems with
> multiple PHY instances connected to a multi-port controller, some PHYs
> may be unconnected. All PHYs must still probe successfully even without
> attached repeaters, otherwise the controller probe fails.
>
> So make it optional.
>
> [...]
Applied, thanks!
[1/1] phy: qcom: m31-eusb2: Make USB repeater optional
commit: a62bfbcf2db4ae6eb7a544a40b1075a81784ea41
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* Re: (subset) [PATCH v4 0/2] Add edp reference clock for lemans
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: robin.clark, lumag, abhinav.kumar, sean, marijn.suijten,
maarten.lankhorst, mripard, tzimmermann, airlied, simona, robh,
krzk+dt, conor+dt, quic_mahap, andersson, konradybcio, mani,
James.Bottomley, martin.petersen, kishon, cros-qcom-dts-watchers,
Ritesh Kumar
Cc: linux-phy, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-scsi, quic_vproddut
In-Reply-To: <20260128114853.2543416-1-quic_riteshk@quicinc.com>
On Wed, 28 Jan 2026 17:18:48 +0530, Ritesh Kumar wrote:
> On lemans chipset, edp reference clock is being voted by ufs mem phy
> (ufs_mem_phy: phy@1d87000). But after commit 77d2fa54a945
> ("scsi: ufs: qcom : Refactor phy_power_on/off calls") edp reference
> clock is getting turned off, leading to below phy poweron failure on
> lemans edp phy.
>
> [ 19.830220] phy phy-aec2a00.phy.10: phy poweron failed --> -110
> [ 19.842112] mdss_0_disp_cc_mdss_dptx0_link_clk status stuck at 'off'
> [ 19.842131] WARNING: CPU: 2 PID: 371 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x174/0x18c
> [ 19.984356] Hardware name: Qualcomm QCS9100 Ride (DT)
> [ 19.989548] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 19.996697] pc : clk_branch_toggle+0x174/0x18c
> [ 20.001267] lr : clk_branch_toggle+0x174/0x18c
> [ 20.005833] sp : ffff8000863ebbc0
> [ 20.009251] x29: ffff8000863ebbd0 x28: 0000000000000000 x27: 0000000000000000
> [ 20.016579] x26: 0000000000000000 x25: 0000000000000000 x24: 0000000000000001
> [ 20.023915] x23: ffff0000c53de980 x22: 0000000000000001 x21: ffffb4b57fd8d710
> [ 20.031245] x20: ffffb4b5bb238b88 x19: 0000000000000000 x18: ffffffffffff7198
> [ 20.038584] x17: 0000000000000014 x16: ffffb4b5bb1e2330 x15: 0000000000000048
> [ 20.045926] x14: 0000000000000000 x13: ffffb4b5bd386a48 x12: 0000000000000dfb
> [ 20.053263] x11: 00000000000004a9 x10: ffffb4b5bd3e5a20 x9 : ffffb4b5bd386a48
> [ 20.060600] x8 : 00000000ffffefff x7 : ffffb4b5bd3dea48 x6 : 00000000000004a9
> [ 20.067934] x5 : ffff000eb7d38408 x4 : 40000000fffff4a9 x3 : ffff4b58fb2b7000
> [ 20.075269] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000ec4fc3480
> [ 20.082601] Call trace:
> [ 20.085127] clk_branch_toggle+0x174/0x18c (P)
> [ 20.089705] clk_branch2_enable+0x1c/0x28
> [ 20.093829] clk_core_enable+0x6c/0xac
> [ 20.097687] clk_enable+0x2c/0x4c
> [ 20.101104] clk_bulk_enable+0x4c/0xd8
> [ 20.104964] msm_dp_ctrl_enable_mainlink_clocks+0x184/0x24c [msm]
> [ 20.111294] msm_dp_ctrl_on_link+0xb0/0x400 [msm]
> [ 20.116178] msm_dp_display_process_hpd_high+0x110/0x190 [msm]
> [ 20.122209] msm_dp_hpd_plug_handle.isra.0+0xac/0x1c4 [msm]
> [ 20.127983] hpd_event_thread+0x320/0x5cc [msm]
> [ 20.132680] kthread+0x12c/0x204
> [ 20.136011] ret_from_fork+0x10/0x20
> [ 20.139699] ---[ end trace 0000000000000000 ]---
> [ 20.144489] Failed to enable clk 'ctrl_link': -16
> [ 20.149340] [drm:msm_dp_ctrl_enable_mainlink_clocks [msm]] *ERROR* Unable to start link clocks. ret=-16
>
> [...]
Applied, thanks!
[1/2] dt-bindings: phy: qcom-edp: Add reference clock for sa8775p eDP PHY
commit: 0cc64561b03d755bba54cbd0cf05e9210ab40a13
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* Re: [PATCH 0/6] phy: qcom-qmp: Clean up QSERDES COM and TXRX register headers
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Neil Armstrong, Dmitry Baryshkov, Abel Vesa, Konrad Dybcio,
Xiangxu Yin, Manivannan Sadhasivam, Luca Weiss, linux-kernel,
linux-arm-msm, linux-phy
In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com>
On Sat, 14 Mar 2026 13:13:19 +0800, Shawn Guo wrote:
> There are some duplications around QSERDES COM and TXRX v2/v3 register
> definitions. The series tries to clean them up, and also rename
> v2 registers/headers to make the version explicit, just like all other
> versions of the QSERDES registers.
>
> No functional changes is expected.
>
> [...]
Applied, thanks!
[1/6] phy: qcom-qmp: Add missing QSERDES COM v2 registers
commit: 52595824b0027d075470f7f08afe805844c1b079
[2/6] phy: qcom-qmp: Use explicit QSERDES COM v2 register definitions
commit: 764f409b840ab400253215e765a72b903feb6afd
[3/6] phy: qcom-qmp-usbc: Use register definitions in qserdes-txrx-v3
commit: 9dfdd6e7bebd63eeef0ba57493adee91c34ae338
[4/6] phy: qcom-qmp-usbc: Rename QCS615 DP PHY variables and functions
commit: c834f0a69051e5db52172262dadf8f7b5ff58bd0
[5/6] phy: qcom-qmp: Drop unused register headers
commit: 9b1270d2b85bb7ce6bbc71232375b21d8be0b799
[6/6] phy: qcom-qmp: Make QSERDES TXRX v2 registers explicit
commit: c7cd4798fafa84581502094d0be282072851c9b7
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* Re: [PATCH] phy: tegra: xusb: Make USB_CONN_GPIO select conditional on GPIOLIB
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: Sasha Levin
Cc: Neil Armstrong, Thierry Reding, Jonathan Hunter, Niklas Cassel,
Vidya Sagar, linux-phy, linux-tegra, linux-kernel
In-Reply-To: <20260426000309.54959-1-sashal@kernel.org>
On Sat, 25 Apr 2026 20:03:09 -0400, Sasha Levin wrote:
> kconfiglint reports:
>
> K006: config PHY_TEGRA_XUSB selects USB_CONN_GPIO which depends on
> GPIOLIB, but PHY_TEGRA_XUSB does not depend on GPIOLIB
> K002: config PHY_TEGRA_XUSB selects visible symbol USB_CONN_GPIO
> which has dependencies
>
> [...]
Applied, thanks!
[1/1] phy: tegra: xusb: Make USB_CONN_GPIO select conditional on GPIOLIB
commit: 18af47764d75bf2cd6297289255fd7f83967e7cf
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* Re: (subset) [PATCH RESEND v3 0/4] Add eMMC PHY support for Axiado AX3000 SoC
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: SriNavmani A, Prasad Bolisetty, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tzu-Hao Wei
Cc: linux-phy, devicetree, linux-arm-kernel, linux-kernel, openbmc
In-Reply-To: <20260504-axiado-ax3000-add-emmc-phy-driver-support-v3-0-3ab7eb45b0c5@axiado.com>
On Mon, 04 May 2026 09:38:31 +0800, Tzu-Hao Wei wrote:
> Axiado AX3000 SoC contains Arasan PHY which provides the interface to the
> HS200 eMMC controller.
>
> This series includes:
> 1. Add bindings for Axiado AX3000 eMMC PHY
> 2. Add Axiado AX3000 eMMC phy driver
> 3. Update MAINTAINERS for the new driver
> 4. Update Axiado AX3000 device tree
>
> [...]
Applied, thanks!
[1/4] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY
commit: 1a75ecefa4fbedefc1600e43445de4e1e7f03b55
[2/4] phy: axiado: add Axiado eMMC PHY driver
commit: 9e7dfa4bcd4e2c3541c4ee954ea5e66edab94d3f
[3/4] MAINTAINERS: Add Axiado AX3000 eMMC PHY driver
commit: 13ee293a904b7b7b0507aaa8c71f7be7e683800e
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* Re: [PATCH v2] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Abel Vesa
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Krzysztof Kozlowski
In-Reply-To: <20260504-eliza-bindings-qmp-phy-v2-1-849c4de8d75f@oss.qualcomm.com>
On Mon, 04 May 2026 19:03:41 +0300, Abel Vesa wrote:
> Document the compatible for the USB QMP PHY found on the Qualcomm Eliza
> SoC.
>
> It is fully compatible with the one found on Qualcomm SM8650, so add it
> with the SM8650 as fallback.
>
>
> [...]
Applied, thanks!
[1/1] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
commit: d67a337d28a2d852ff539e983ad6790caf9c95f5
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* Re: [PATCH v2] dt-bindings: phy: qcom,snps-eusb2: Document the Eliza Synopsys eUSB2 PHY
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Abel Vesa, Abel Vesa
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, Konrad Dybcio
In-Reply-To: <20260504-eliza-bindings-phy-eusb2-v2-1-fa3a1fd65ab1@oss.qualcomm.com>
On Mon, 04 May 2026 19:06:46 +0300, Abel Vesa wrote:
> The Synopsys eUSB2 PHY found on the Eliza SoC is fully compatible with the
> one found the SM8550.
>
> So document it by adding the compatible to the list that has the SM8550
> one as fallback.
>
>
> [...]
Applied, thanks!
[1/1] dt-bindings: phy: qcom,snps-eusb2: Document the Eliza Synopsys eUSB2 PHY
commit: 78a6a90a5c4ac29d06fc8119885b80f919950d00
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* Re: [PATCH v3] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Nord QMP UFS PHY
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Dmitry Baryshkov, Bartosz Golaszewski, Deepti Jaggi, linux-phy,
devicetree, linux-arm-msm, linux-kernel
In-Reply-To: <20260504081442.825908-1-shengchao.guo@oss.qualcomm.com>
On Mon, 04 May 2026 16:14:42 +0800, Shawn Guo wrote:
> Document QMP UFS PHY on Qualcomm Nord SoC.
>
>
Applied, thanks!
[1/1] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Nord QMP UFS PHY
commit: 6d6ff64e01ddeb579bf0078e5b6d50c04035541e
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* Re: [PATCH v4 0/2] phy: spacemit: Add USB2 PHY support for K3 SoC
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ze Huang, Yixun Lan
Cc: Junzhong Pan, linux-phy, devicetree, linux-riscv, spacemit,
linux-kernel, Krzysztof Kozlowski, Yao Zi
In-Reply-To: <20260305-11-k3-usb2-phy-v4-0-15554fb933bc@kernel.org>
On Thu, 05 Mar 2026 01:00:50 +0000, Yixun Lan wrote:
> The series trys to add USB2 PHY support for SpacemiT K3 SoC, while
> patch [1/2] implement a disconnect function which is needed during
> next connection.
>
> No DTS part has been inclueded in this series, instead I plan to
> submit them later while adding USB host support.
>
> [...]
Applied, thanks!
[1/2] dt-bindings: phy: spacemit: k3: add USB2 PHY support
commit: ad8fdebd40fd25e86331886f4fc6951531691319
[2/2] phy: k1-usb: k3: add USB2 PHY support
commit: 056ee8b37bc91e3230afa11ec1018fa898b983b8
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* Re: (subset) [PATCH v4 0/5] J722S SGMII support
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Neil Armstrong,
Nora Schiffer
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Siddharth Vadapalli, Roger Quadros, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux
In-Reply-To: <cover.1775559102.git.nora.schiffer@ew.tq-group.com>
On Tue, 07 Apr 2026 13:42:32 +0200, Nora Schiffer wrote:
> The J722S CPSW and SERDES are very similar to the variants found on the
> AM64, but they additionally support SGMII. Introduce new compatible
> strings for the J722S to add this support to the drivers.
>
> This is a prerequisite for the Single-Pair Ethernet interface of the
> TQ-Systems MBa67xx baseboard for the TQMa67xx SoM, which will be
> submitted separately.
>
> [...]
Applied, thanks!
[1/5] dt-bindings: phy: ti: phy-j721e-wiz: Add ti,j722s-wiz-10g compatible
commit: 059f1a4c9e3aa44d888c0e7cf4559403eece0438
[2/5] dt-bindings: phy: ti: phy-gmii-sel: Add ti,j722s-phy-gmii-sel compatible
commit: 567b3c62a7eb51db4cb562b416ec220132d524c9
[3/5] phy: ti: phy-j721e-wiz: add support for J722S SoC family
commit: 61849b7afb579630fc45dbeaf5449b42b33cc70e
[4/5] phy: ti: gmii-sel: add support for J722S SoC family
commit: d39cf00e7daea64889dda9abb0b7e6da04a69d04
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* Re: [PATCH] phy: renesas: rzg3e-usb3: Convert to FIELD_MODIFY()
From: Vinod Koul @ 2026-05-10 12:24 UTC (permalink / raw)
To: Neil Armstrong, Biju Das, Geert Uytterhoeven; +Cc: linux-phy, linux-renesas-soc
In-Reply-To: <a52020ba597e2e213b161eee21239f10e6057d9d.1772705690.git.geert+renesas@glider.be>
On Thu, 05 Mar 2026 11:15:28 +0100, Geert Uytterhoeven wrote:
> Use the FIELD_MODIFY() helper instead of open-coding the same operation.
>
>
Applied, thanks!
[1/1] phy: renesas: rzg3e-usb3: Convert to FIELD_MODIFY()
commit: 5e2871746039e69657623b222b30c1c6f52159f0
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* Re: [PATCH] phy: spacemit: Remove incorrect clk_disable() in spacemit_usb2phy_init()
From: Vinod Koul @ 2026-05-10 12:24 UTC (permalink / raw)
To: Neil Armstrong, Yixun Lan, Ze Huang, Felix Gu
Cc: linux-phy, linux-riscv, spacemit, linux-kernel
In-Reply-To: <20260326-k1-usb3-v1-1-0c2b6adf5185@gmail.com>
On Thu, 26 Mar 2026 00:23:58 +0800, Felix Gu wrote:
> When clk_enable() fails, the clock was never enabled. Calling
> clk_disable() in this error path is incorrect.
>
> Remove the spurious clk_disable() call from the error handling
> in spacemit_usb2phy_init().
>
>
> [...]
Applied, thanks!
[1/1] phy: spacemit: Remove incorrect clk_disable() in spacemit_usb2phy_init()
commit: a4058c09dd6e28ec33316fd6eb45ddae4cab1f31
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* Re: [PATCH v1] phy: eswin: Fix incorrect error check in probe()
From: Vinod Koul @ 2026-05-10 12:23 UTC (permalink / raw)
To: neil.armstrong, linux-phy, linux-kernel, Yulin Lu
Cc: linmin, ningyu, Dan Carpenter
In-Reply-To: <20260413070033.128-1-luyulin@eswincomputing.com>
On Mon, 13 Apr 2026 15:00:33 +0800, Yulin Lu wrote:
> devm_ioremap() returns NULL on failure, not an ERR_PTR.
> Using IS_ERR() to check the return value is incorrect.
>
> Fix this by checking for NULL and returning -ENOMEM.
>
>
Applied, thanks!
[1/1] phy: eswin: Fix incorrect error check in probe()
commit: c2cd08e8f150738515c8df415ad7ecfa3d38124a
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* Re: [PATCH] phy: qcom-qmp-ufs: Fix kaanapali PHY PLL lock failure after SM8650 G4 fix
From: Vinod Koul @ 2026-05-10 12:23 UTC (permalink / raw)
To: neil.armstrong, konrad.dybcio, dmitry.baryshkov, mani, abel.vesa,
Nitin Rawat
Cc: linux-arm-msm, linux-phy, linux-kernel, stable
In-Reply-To: <20260415104851.2763238-1-nitin.rawat@oss.qualcomm.com>
On Wed, 15 Apr 2026 16:18:51 +0530, Nitin Rawat wrote:
> Commit 81af9e40e2e4 ("phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4")
> moved QPHY_V6_PCS_UFS_PLL_CNTL register configuration from the shared
> sm8650_ufsphy_g5_pcs table to the SM8650-specific sm8650_ufsphy_pcs base
> table to fix Gear 4 operation on SM8650.
>
> However, this change inadvertently broke kaanapali and SM8750 SoCs
> which also rely on the shared sm8650_ufsphy_g5_pcs table for Gear 5
> configuration but use their own sm8750_ufsphy_pcs base table. After the
> change, kaanapali PHYs are left without the required PLL_CNTL = 0x33
> setting, causing the PHY PLL to remain at its hardware reset default
> value, preventing PLL lock and resulting in DME_LINKSTARTUP timeouts.
>
> [...]
Applied, thanks!
[1/1] phy: qcom-qmp-ufs: Fix kaanapali PHY PLL lock failure after SM8650 G4 fix
commit: 80305760d7a55b884fb9023c490b75568d1ea0b1
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* Re: [PATCH v2] phy: exynos5-usbdrd: fix USB 2.0 HS PHY tuning values for Exynos7870
From: Vinod Koul @ 2026-05-10 12:23 UTC (permalink / raw)
To: Łukasz Lebiedziński
Cc: neil.armstrong, krzk, alim.akhtar, andre.draszik, pritam.sutar,
kauschluss, johan, ivo.ivanov.ivanov1, linux-phy,
linux-arm-kernel, linux-samsung-soc, linux-kernel, stable,
Krzysztof Kozlowski
In-Reply-To: <20260406135627.234835-1-kernel@lvkasz.us>
On Mon, 06 Apr 2026 15:56:27 +0200, Łukasz Lebiedziński wrote:
> The existing PHYPARAM0 tuning values for Exynos7870 are incorrect,
> causing the USB 2.0 PHY to fail high-speed negotiation and fall back
> to full-speed (12Mbps) operation.
>
> Fix TXVREFTUNE (transmitter voltage reference) from 14 to 3,
> TXRESTUNE (transmitter impedance) from 3 to 2, and SQRXTUNE
> (squelch threshold) from 6 to 5. Also explicitly set
> TXPREEMPPULSETUNE to 0, which was previously missing from the
> tuning table despite being included in the register mask.
>
> [...]
Applied, thanks!
[1/1] phy: exynos5-usbdrd: fix USB 2.0 HS PHY tuning values for Exynos7870
commit: 5a759b120e31aa3ed914d98b51eb1755235250f2
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* Re: [PATCH v2] phy: tegra: xusb: Fix per-pad high-speed termination calibration
From: Vinod Koul @ 2026-05-10 12:23 UTC (permalink / raw)
To: Jonathan Hunter, JC Kuo, Neil Armstrong, Thierry Reding,
Wei-Cheng Chen
Cc: Wayne Chang, WK Tsai, linux-phy, linux-tegra, linux-kernel
In-Reply-To: <20260504033305.2283145-1-weichengc@nvidia.com>
On Mon, 04 May 2026 11:33:05 +0800, Wei-Cheng Chen wrote:
> The existing code reads a single hs_term_range_adj value from bit field
> [10:7] of FUSE_SKU_CALIB_0 and applies it to all USB2 pads uniformly.
> However, on SoCs that support per-pad termination, each pad has its own
> hs_term_range_adj field: pad 0 in FUSE_SKU_CALIB_0[10:7], and pads 1-3
> in FUSE_USB_CALIB_EXT_0 at bit offsets [8:5], [12:9], and [16:13]
> respectively.
>
> [...]
Applied, thanks!
[1/1] phy: tegra: xusb: Fix per-pad high-speed termination calibration
commit: da110228b54f2e2143d97ea7151e0dc22e539d67
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* Re: [PATCH phy-fixes] phy: marvell: mvebu-a3700-utmi: fix incorrect USB2_PHY_CTRL register access
From: Vinod Koul @ 2026-05-10 12:23 UTC (permalink / raw)
To: Miquel Raynal, Neil Armstrong, Igal Liberman,
Kishon Vijay Abraham I, Gabor Juhos
Cc: linux-phy, linux-kernel
In-Reply-To: <20260321-a3700-utmi-fix-usb2_phy_ctrl-access-v1-1-6005ff4b5058@gmail.com>
On Sat, 21 Mar 2026 15:42:32 +0100, Gabor Juhos wrote:
> The mvebu_a3700_utmi_phy_power_off() function tries to modify the
> USB2_PHY_CTRL register by using the IO address of the PHY IP block along
> with the readl/writel IO accessors. However, the register exist in the
> USB miscellaneous register space, and as such it must be accessed via
> regmap like it is done in the mvebu_a3700_utmi_phy_power_on() function.
>
> Change the code to use regmap_update_bits() for modífying the register
> to fix this.
>
> [...]
Applied, thanks!
[1/1] phy: marvell: mvebu-a3700-utmi: fix incorrect USB2_PHY_CTRL register access
commit: 91ddf6f722084383fb05be731c0107814b055c0c
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* Re: [PATCH] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
From: Vinod Koul @ 2026-05-10 12:06 UTC (permalink / raw)
To: Abel Vesa
Cc: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260318-eliza-bindings-qmp-phy-v1-1-96a0d529ad2d@oss.qualcomm.com>
On 18-03-26, 11:54, Abel Vesa wrote:
> Document the compatible for the USB QMP PHY found on the Qualcomm Eliza
> SoC.
>
> It is fully compatible with the one found on Qualcomm SM8650, so add it
> with the SM8650 as fallback.
Can you please rebase this on phy/next
>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> index 3d537b7f9985..4eff92343ce4 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> @@ -16,6 +16,10 @@ description:
> properties:
> compatible:
> oneOf:
> + - items:
> + - enum:
> + - qcom,eliza-qmp-usb3-dp-phy
> + - const: qcom,sm8650-qmp-usb3-dp-phy
> - items:
> - enum:
> - qcom,kaanapali-qmp-usb3-dp-phy
>
> ---
> base-commit: 8e5a478b6d6a5bb0a3d52147862b15e4d826af19
> change-id: 20260318-eliza-bindings-qmp-phy-c53be4b0b131
>
> Best regards,
> --
> Abel Vesa <abel.vesa@oss.qualcomm.com>
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* Re: [PATCH V2 RESEND 2/2] phy: mediatek: xsphy: add support to set disconnect threshold
From: Vinod Koul @ 2026-05-10 11:50 UTC (permalink / raw)
To: Chunfeng Yun
Cc: AngeloGioacchino Del Regno, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
linux-arm-kernel, linux-mediatek, linux-phy, devicetree,
linux-kernel
In-Reply-To: <20260413122836.4848-2-chunfeng.yun@mediatek.com>
On 13-04-26, 20:28, Chunfeng Yun wrote:
> Add a property to tune usb2 phy's disconnect threshold.
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: change property name
> ---
> drivers/phy/mediatek/phy-mtk-xsphy.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-xsphy.c b/drivers/phy/mediatek/phy-mtk-xsphy.c
> index c0ddb9273cc3..46345e4f4189 100644
> --- a/drivers/phy/mediatek/phy-mtk-xsphy.c
> +++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
> @@ -61,6 +61,7 @@
> #define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
> #define P2A6_RG_BC11_SW_EN BIT(23)
> #define P2A6_RG_OTG_VBUSCMP_EN BIT(20)
> +#define PA6_RG_U2_DISCTH GENMASK(7, 4)
>
> #define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C)
> #define P2D_FORCE_IDDIG BIT(9)
> @@ -107,6 +108,7 @@ struct xsphy_instance {
> int eye_src;
> int eye_vrt;
> int eye_term;
> + int discth;
Please see
https://sashiko.dev/#/patchset/20260413122836.4848-1-chunfeng.yun%40mediatek.com
> };
>
> struct mtk_xsphy {
> @@ -256,9 +258,12 @@ static void phy_parse_property(struct mtk_xsphy *xsphy,
> &inst->eye_vrt);
> device_property_read_u32(dev, "mediatek,eye-term",
> &inst->eye_term);
> - dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",
> + device_property_read_u32(dev, "mediatek,discth",
> + &inst->discth);
> + dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d, discth:%d\n",
> inst->efuse_intr, inst->eye_src,
> - inst->eye_vrt, inst->eye_term);
> + inst->eye_vrt, inst->eye_term,
> + inst->discth);
> break;
> case PHY_TYPE_USB3:
> device_property_read_u32(dev, "mediatek,efuse-intr",
> @@ -301,6 +306,9 @@ static void u2_phy_props_set(struct mtk_xsphy *xsphy,
> if (inst->eye_term)
> mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
> inst->eye_term);
> + if (inst->discth)
> + mtk_phy_update_field(pbase + XSP_USBPHYACR6, PA6_RG_U2_DISCTH,
> + inst->discth);
> }
>
> static void u3_phy_props_set(struct mtk_xsphy *xsphy,
> --
> 2.45.2
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