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* [PATCH RESEND v8 00/10] SPMI: Implement sub-devices and migrate drivers
From: AngeloGioacchino Del Regno @ 2026-05-11 10:07 UTC (permalink / raw)
  To: jic23
  Cc: dlechner, nuno.sa, andy, arnd, gregkh, srini, vkoul,
	neil.armstrong, sre, sboyd, angelogioacchino.delregno, krzk,
	dmitry.baryshkov, quic_wcheng, melody.olvera, quic_nsekar,
	ivo.ivanov.ivanov1, abelvesa, luca.weiss, konrad.dybcio,
	mitltlatltl, krishna.kurapati, linux-arm-msm, linux-iio,
	linux-kernel, linux-phy, linux-pm, kernel

Changes in v8:
 - Renamed *res to *sub_sdev in devm_spmi_subdevice_remove() (Andy)
 - Changed kerneldoc wording to "error pointer" for function
   spmi_subdevice_alloc_and_add() (Andy)
 - Shuffled around some assignments in spmi_subdevice_alloc_and_add() (Andy)
 - Used device_property_read_u32() instead of of_property_read_u32()
   in all of the migrated drivers (Andy)
 - Changed .max_register field in all of the migrated drivers from
   0x100 to 0xff (Andy)
 - Kept `sta1` declaration in reversed xmas tree order in function
   iadc_poll_wait_eoc() of qcom-spmi-iadc.c (Andy)

Changes in v7:
 - Added commit to cleanup redundant dev_name() in the pre-existing
   spmi_device_add() function
 - Added commit removing unneeded goto and improving spmi_device_add()
   readability by returning error in error path, and explicitly zero
   for success at the end.

Changes in v6:
 - Added commit to convert spmi.c to %pe error format and used
   %pe error format in spmi_subdevice code as wanted by Uwe Kleine-Konig

Changes in v5:
 - Changed dev_err to dev_err_probe in qcom-spmi-sdam (and done
   that even though I disagree - because I wanted this series to
   *exclusively* introduce the minimum required changes to
   migrate to the new API, but okay, whatever....!);
 - Added missing REGMAP dependency in Kconfig for qcom-spmi-sdam,
   phy-qcom-eusb2-repeater and qcom-coincell to resolve build
   issues when the already allowed COMPILE_TEST is enabled
   as pointed out by the test robot's randconfig builds.

Changes in v4:
 - Added selection of REGMAP_SPMI in Kconfig for qcom-coincell and
   for phy-qcom-eusb2-repeater to resolve undefined references when
   compiled with some randconfig

Changes in v3:
 - Fixed importing "SPMI" namespace in spmi-devres.c
 - Removed all instances of defensive programming, as pointed out by
   jic23 and Sebastian
 - Removed explicit casting as pointed out by jic23
 - Moved ida_free call to spmi_subdev_release() and simplified error
   handling in spmi_subdevice_alloc_and_add() as pointed out by jic23

Changes in v2:
 - Fixed missing `sparent` initialization in phy-qcom-eusb2-repeater
 - Changed val_bits to 8 in all Qualcomm drivers to ensure
   compatibility as suggested by Casey
 - Added struct device pointer in all conversion commits as suggested
   by Andy
 - Exported newly introduced functions with a new "SPMI" namespace
   and imported the same in all converted drivers as suggested by Andy
 - Added missing error checking for dev_set_name() call in spmi.c
   as suggested by Andy
 - Added comma to last entry of regmap_config as suggested by Andy

While adding support for newer MediaTek platforms, featuring complex
SPMI PMICs, I've seen that those SPMI-connected chips are internally
divided in various IP blocks, reachable in specific contiguous address
ranges... more or less like a MMIO, but over a slow SPMI bus instead.

I recalled that Qualcomm had something similar... and upon checking a
couple of devicetrees, yeah - indeed it's the same over there.

What I've seen then is a common pattern of reading the "reg" property
from devicetree in a struct member and then either
 A. Wrapping regmap_{read/write/etc}() calls in a function that adds
    the register base with "base + ..register", like it's done with
    writel()/readl() calls; or
 B. Doing the same as A. but without wrapper functions.

Even though that works just fine, in my opinion it's wrong.

The regmap API is way more complex than MMIO-only readl()/writel()
functions for multiple reasons (including supporting multiple busses
like SPMI, of course) - but everyone seemed to forget that regmap
can manage register base offsets transparently and automatically in
its API functions by simply adding a `reg_base` to the regmap_config
structure, which is used for initializing a `struct regmap`.

So, here we go: this series implements the software concept of an SPMI
Sub-Device (which, well, also reflects how Qualcomm and MediaTek's
actual hardware is laid out anyway).

               SPMI Controller
                     |                ______
                     |               /       Sub-Device 1
                     V              /
              SPMI Device (PMIC) ----------- Sub-Device 2
                                    \
                                     \______ Sub-Device 3

As per this implementation, an SPMI Sub-Device can be allocated/created
and added in any driver that implements a... well.. subdevice (!) with
an SPMI "main" device as its parent: this allows to create and finally
to correctly configure a regmap that is specific to the sub-device,
operating on its specific address range and reading, and writing, to
its registers with the regmap API taking care of adding the base address
of a sub-device's registers as per regmap API design.

All of the SPMI Sub-Devices are therefore added as children of the SPMI
Device (usually a PMIC), as communication depends on the PMIC's SPMI bus
to be available (and the PMIC to be up and running, of course).

Summarizing the dependency chain (which is obvious to whoever knows what
is going on with Qualcomm and/or MediaTek SPMI PMICs):
    "SPMI Sub-Device x...N" are children "SPMI Device"
    "SPMI Device" is a child of "SPMI Controller"

(that was just another way to say the same thing as the graph above anyway).

Along with the new SPMI Sub-Device registration functions, I have also
performed a conversion of some Qualcomm SPMI drivers and only where the
actual conversion was trivial.

I haven't included any conversion of more complex Qualcomm SPMI drivers
because I don't have the required bandwidth to do so (and besides, I think,
but haven't exactly verified, that some of those require SoCs that I don't
have for testing anyway).

AngeloGioacchino Del Regno (10):
  spmi: Remove redundant dev_name() print in spmi_device_add()
  spmi: Print error status with %pe format
  spmi: Remove unneeded goto in spmi_device_add() error path
  spmi: Implement spmi_subdevice_alloc_and_add() and devm variant
  nvmem: qcom-spmi-sdam: Migrate to devm_spmi_subdevice_alloc_and_add()
  power: reset: qcom-pon: Migrate to devm_spmi_subdevice_alloc_and_add()
  phy: qualcomm: eusb2-repeater: Migrate to
    devm_spmi_subdevice_alloc_and_add()
  misc: qcom-coincell: Migrate to devm_spmi_subdevice_alloc_and_add()
  iio: adc: qcom-spmi-iadc: Migrate to
    devm_spmi_subdevice_alloc_and_add()
  iio: adc: qcom-spmi-iadc: Remove regmap R/W wrapper functions

 drivers/iio/adc/qcom-spmi-iadc.c              | 109 ++++++++----------
 drivers/misc/Kconfig                          |   2 +
 drivers/misc/qcom-coincell.c                  |  38 ++++--
 drivers/nvmem/Kconfig                         |   1 +
 drivers/nvmem/qcom-spmi-sdam.c                |  38 ++++--
 drivers/phy/qualcomm/Kconfig                  |   2 +
 .../phy/qualcomm/phy-qcom-eusb2-repeater.c    |  55 +++++----
 drivers/power/reset/qcom-pon.c                |  33 ++++--
 drivers/spmi/spmi-devres.c                    |  24 ++++
 drivers/spmi/spmi.c                           |  95 +++++++++++++--
 include/linux/spmi.h                          |  16 +++
 11 files changed, 290 insertions(+), 123 deletions(-)

-- 
2.53.0


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* [PATCH RESEND v8 01/10] spmi: Remove redundant dev_name() print in spmi_device_add()
From: AngeloGioacchino Del Regno @ 2026-05-11 10:07 UTC (permalink / raw)
  To: jic23
  Cc: dlechner, nuno.sa, andy, arnd, gregkh, srini, vkoul,
	neil.armstrong, sre, sboyd, angelogioacchino.delregno, krzk,
	dmitry.baryshkov, quic_wcheng, melody.olvera, quic_nsekar,
	ivo.ivanov.ivanov1, abelvesa, luca.weiss, konrad.dybcio,
	mitltlatltl, krishna.kurapati, linux-arm-msm, linux-iio,
	linux-kernel, linux-phy, linux-pm, kernel, Andy Shevchenko
In-Reply-To: <20260511100805.121432-1-angelogioacchino.delregno@collabora.com>

Function spmi_device_add() uses dev_{dbg,err}() for respectively
debug and error prints, and passes the same device pointer as both
the dev_{dbg,err}() parameters and to a dev_name() that is part of
the actual message.
This means that the device name gets printed twice!

Remove the redundant dev_name() from the messages.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/spmi/spmi.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c
index e889b129f3ac..e93fc2c95759 100644
--- a/drivers/spmi/spmi.c
+++ b/drivers/spmi/spmi.c
@@ -68,12 +68,11 @@ int spmi_device_add(struct spmi_device *sdev)
 
 	err = device_add(&sdev->dev);
 	if (err < 0) {
-		dev_err(&sdev->dev, "Can't add %s, status %d\n",
-			dev_name(&sdev->dev), err);
+		dev_err(&sdev->dev, "Can't add device, status %d\n", err);
 		goto err_device_add;
 	}
 
-	dev_dbg(&sdev->dev, "device %s registered\n", dev_name(&sdev->dev));
+	dev_dbg(&sdev->dev, "device registered\n");
 
 err_device_add:
 	return err;
-- 
2.53.0


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* Re: [PATCH v2 0/4] Add USB Phy driver and binding changes for Qualcomm Shikra SoC
From: Krishna Kurapati @ 2026-05-11  9:06 UTC (permalink / raw)
  To: Vinod Koul
  Cc: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Bjorn Andersson, Konrad Dybcio, Xiangxu Yin, Johan Hovold,
	Loic Poulain, Kathiravan Thirumoorthy, Dmitry Baryshkov,
	linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <agBP_HeLmVAKLFUh@vaman>



On 5/10/2026 2:59 PM, Vinod Koul wrote:
> On 04-05-26, 22:36, Krishna Kurapati wrote:
>> This series adds Driver and binding changes for USB Phys on Shikra. There
>> are two USB controllers - One of them is SS capable and other is highspeed
>> only capable. The ss Phy init sequence is same as that of Talos.
> 
> Please check https://sashiko.dev/#/patchset/20260504170659.282532-1-krishna.kurapati%40oss.qualcomm.com
> 

Thanks for the report Vinod.

Will do the following:

1. On hs phy driver patch, will update commit text to mention that 
register init sequence of Shikra is same as that of Talos and hence the 
qcs615 init tbl is being reused.

2. On the super speed phy driver patch, I repsonded to Krzysztof 
comments as to why fallback copatible can't be used. Will update commit 
text appropriately once comments are all resolved.

[1]: 
https://lore.kernel.org/all/d52c5039-9431-44ed-9f3b-bb00d03ae176@oss.qualcomm.com/

Regards,
Krishna,

>>
>> Changes in v2:
>> - Separated the usb controller binding changes
>> - Updated commit texts.
>>
>> Krishna Kurapati (4):
>>    dt-bindings: phy: qcom,qusb2: Document QUSB2 Phy for Shikra
>>    dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for Shikra
>>    phy: qcom-qusb2: Add support for Shikra
>>    phy: qcom: qmp-usbc: Add qmp configuration for Shikra
>>
>>   .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml  |  2 ++
>>   .../devicetree/bindings/phy/qcom,qusb2-phy.yaml  |  1 +
>>   drivers/phy/qualcomm/phy-qcom-qmp-usbc.c         |  3 +++
>>   drivers/phy/qualcomm/phy-qcom-qusb2.c            | 16 ++++++++++++++++
>>   4 files changed, 22 insertions(+)
>>
>> -- 
>> 2.34.1
> 


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* Re: [PATCH v2 1/2] phy: rockchip: inno-hdmi: Add configure() and validate() ops
From: Jonas Karlman @ 2026-05-10 18:43 UTC (permalink / raw)
  To: Vinod Koul, Neil Armstrong, Heiko Stuebner
  Cc: linux-phy, linux-rockchip, linux-arm-kernel, linux-kernel
In-Reply-To: <20260510095731.1222705-2-jonas@kwiboo.se>

On 5/10/2026 11:57 AM, Jonas Karlman wrote:
> The commit 10ed34d6eaaf ("phy: Add HDMI configuration options")
> introduced a way for HDMI PHYs to be configured through the generic
> phy_configure() function.
> 
> This driver derives the TMDS character rate from the pixel clock and the
> PHY bus width setting. However, no in-tree consumer of this PHY has ever
> called phy_set_bus_width() to change the TMDS character rate as only
> 8-bit RGB output is supported by the HDMI display driver.
> 
> Add configure() and validate() ops to allow consumers to configure the
> TMDS character rate using phy_configure(). Fallback to the deprecated
> way of using the PHY bus width to configure the TMDS character rate.

I have now posted a patch "drm/rockchip: dw_hdmi: Configure HDMI PHY
in atomic_mode_set()" [1] that adds phy_validate() and phy_configure()
calls for this HDMI PHY.

[1] https://lore.kernel.org/dri-devel/20260510183114.1248840-10-jonas@kwiboo.se/

Regards,
Jonas

> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> ---
> Changes in v2:
> - Add validate() ops to validate that the TMDS rate is supported
> - Split out parts that remove the old workaround into a separate patch
> ---
>  drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 47 ++++++++++++++++++-
>  1 file changed, 46 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> index 1483907413fa..9cfe956fefe7 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> @@ -245,6 +245,7 @@ struct inno_hdmi_phy {
>  	struct clk *phyclk;
>  	unsigned long pixclock;
>  	unsigned long tmdsclock;
> +	struct phy_configure_opts_hdmi hdmi_cfg;
>  };
>  
>  struct pre_pll_config {
> @@ -554,7 +555,12 @@ static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
>  static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
>  					       unsigned long rate)
>  {
> -	int bus_width = phy_get_bus_width(inno->phy);
> +	int bus_width;
> +
> +	if (inno->hdmi_cfg.tmds_char_rate)
> +		return inno->hdmi_cfg.tmds_char_rate;
> +
> +	bus_width = phy_get_bus_width(inno->phy);
>  
>  	switch (bus_width) {
>  	case 4:
> @@ -602,6 +608,42 @@ static irqreturn_t inno_hdmi_phy_rk3328_irq(int irq, void *dev_id)
>  	return IRQ_HANDLED;
>  }
>  
> +static int inno_hdmi_phy_validate(struct phy *phy, enum phy_mode mode,
> +				  int submode, union phy_configure_opts *opts)
> +{
> +	const struct pre_pll_config *cfg = pre_pll_cfg_table;
> +	unsigned long tmdsclock;
> +
> +	if (!(mode == PHY_MODE_HDMI && submode == PHY_HDMI_MODE_TMDS))
> +		return -EINVAL;
> +
> +	if (!opts->hdmi.tmds_char_rate || opts->hdmi.tmds_char_rate > 594000000)
> +		return -EINVAL;
> +
> +	tmdsclock = opts->hdmi.tmds_char_rate;
> +	for (; cfg->pixclock != 0; cfg++)
> +		if (cfg->pixclock == tmdsclock && cfg->tmdsclock == tmdsclock)
> +			return 0;
> +
> +	return -EINVAL;
> +}
> +
> +static int inno_hdmi_phy_configure(struct phy *phy,
> +				   union phy_configure_opts *opts)
> +{
> +	struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
> +	int ret;
> +
> +	ret = inno_hdmi_phy_validate(phy, phy_get_mode(phy),
> +				     PHY_HDMI_MODE_TMDS, opts);
> +	if (ret)
> +		return ret;
> +
> +	inno->hdmi_cfg = opts->hdmi;
> +
> +	return 0;
> +}
> +
>  static int inno_hdmi_phy_power_on(struct phy *phy)
>  {
>  	struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
> @@ -670,6 +712,8 @@ static const struct phy_ops inno_hdmi_phy_ops = {
>  	.owner = THIS_MODULE,
>  	.power_on = inno_hdmi_phy_power_on,
>  	.power_off = inno_hdmi_phy_power_off,
> +	.configure = inno_hdmi_phy_configure,
> +	.validate = inno_hdmi_phy_validate,
>  };
>  
>  static const
> @@ -1392,6 +1436,7 @@ static int inno_hdmi_phy_probe(struct platform_device *pdev)
>  	}
>  
>  	phy_set_drvdata(inno->phy, inno);
> +	phy_set_mode_ext(inno->phy, PHY_MODE_HDMI, PHY_HDMI_MODE_TMDS);
>  	phy_set_bus_width(inno->phy, 8);
>  
>  	if (inno->plat_data->ops->init) {


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* Re: [PATCH v3 0/4] phy: phy-can-transceiver: Ad-hoc cleanups and refactoring
From: Andy Shevchenko @ 2026-05-10 12:51 UTC (permalink / raw)
  To: Vinod Koul
  Cc: Peng Fan, linux-can, linux-phy, linux-kernel, Marc Kleine-Budde,
	Vincent Mailhol, Neil Armstrong, Josua Mayer, Ulf Hansson
In-Reply-To: <agBjOmnpKuZoDfWG@vaman>

On Sun, May 10, 2026 at 04:21:38PM +0530, Vinod Koul wrote:
> On 04-05-26, 08:58, Andy Shevchenko wrote:
> > The driver does two things that need to be addressed:
> > - includes subject to remove gpio.h
> > - checks for error code from device property APIs when it can be done in
> >   a robust way
> > 
> > This series addresses the above and adds a couple of additional refactoring.
> 
> Sashiko flagged some issues, some of them not introduced by this, can
> you please check this:
> 
> https://sashiko.dev/#/patchset/20260504070054.29508-1-andriy.shevchenko%40linux.intel.com

"Could this result in a null pointer dereference if device_get_match_data()
returns null?"
Yes, it sounds legit but not introduced here.

"In the original code, the warning was suppressed when the property was missing
because err evaluated to -EINVAL. Now, if the property is absent, max_bitrate
is explicitly set to 0 in the else block, which then unconditionally triggers
this warning."
True, but I don't know which is better here, I consider that it's
good to inform user about default being used as a fallback. I can change
this back to the original logic. What do you prefer?

The third one is the repetition of the first one (see above).

TL;DR: The only one legitimated question is about a (new old) warning.

-- 
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Andy Shevchenko



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* Re: [RESEND 1/1] phy: freescale: imx8qm-hsio: provide regmap names
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
  To: Neil Armstrong, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, Alexander Stein
  Cc: linux-phy, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20260211144949.1128122-1-alexander.stein@ew.tq-group.com>


On Wed, 11 Feb 2026 15:49:48 +0100, Alexander Stein wrote:
> This driver uses multiple regmaps, which will causes name conflicts
> in debugfs like:
>   debugfs: '5f1a0000.phy' already exists in 'regmap'
> Fix this by using a dedicated regmap config for each resource, each
> having a dedicated regmap name.
> 
> 
> [...]

Applied, thanks!

[1/1] phy: freescale: imx8qm-hsio: provide regmap names
      commit: 057c81a17fffb17f66e5b4524d49b7caad3fe627

Best regards,
-- 
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* Re: [PATCHv2 0/2] phy: miphy28lp: build and simplify allocation
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
  To: linux-phy, Rosen Penev
  Cc: Neil Armstrong, Patrice Chotard, Kees Cook, Gustavo A. R. Silva,
	linux-kernel, linux-arm-kernel, linux-hardening
In-Reply-To: <20260306222457.8400-1-rosenp@gmail.com>


On Fri, 06 Mar 2026 14:24:55 -0800, Rosen Penev wrote:
> First patch allows compilation on at least x86.
> 
> Second uses a flexible array member to simplify allocation.
> 
> v2: add first patch and fix second.
> 
> Rosen Penev (2):
>   phy: miphy28lp: add COMPILE_TEST
>   phy: miphy28lp: kzalloc + kcalloc to single kzalloc
> 
> [...]

Applied, thanks!

[1/2] phy: miphy28lp: add COMPILE_TEST
      commit: cc68a1728abfcbde12d36015f244046ae74ddd44
[2/2] phy: miphy28lp: kzalloc + kcalloc to single kzalloc
      commit: f3508a61c892c592e4e893a3681e568a5c671027

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* Re: [PATCH v9] phy: Add generic PHY driver used by MACB/GEM on EyeQ5
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
  To: Neil Armstrong, Théo Lebrun
  Cc: linux-phy, linux-kernel, linux-mips, Vladimir Kondratiev,
	Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
	Thomas Petazzoni, Luca Ceresoli
In-Reply-To: <20260309-macb-phy-v9-0-5afd87d9db43@bootlin.com>


On Mon, 09 Mar 2026 15:37:33 +0100, Théo Lebrun wrote:
> EyeQ5 SoCs integrate two GEM instances. A system-controller register
> region named "OLB" has some control over the Ethernet PHY integration.
> 
> Extend the current OLB ecosystem with a new generic PHY driver.
>  - OLB is carried by one main platform driver: clk-eyeq.
>  - It instantiates auxiliary devices: reset-eyeq & pinctrl-eyeq5.
>  - We add a new one: phy-eyeq5-eth.
> 
> [...]

Applied, thanks!

[1/1] phy: Add driver for EyeQ5 Ethernet PHY wrapper
      commit: b6e33443876d0ca7e93cf949455e3c1a1a0aae24

Best regards,
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* Re: [PATCH v2] phy: renesas: phy-rzg3e-usb3: Fix malformed MODULE_AUTHOR string
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
  To: Biju
  Cc: Biju Das, Neil Armstrong, Geert Uytterhoeven, linux-phy,
	linux-kernel, Prabhakar Mahadev Lad, linux-renesas-soc,
	Pavel Machek
In-Reply-To: <20260319063211.5056-1-biju.das.jz@bp.renesas.com>


On Thu, 19 Mar 2026 06:32:07 +0000, Biju wrote:
> Fix a malformed MODULE_AUTHOR macro in the RZ/G3E USB3.0 PHY driver where
> the author's name and opening angle bracket were missing, leaving only the
> email address with a stray closing >. Correct it to the standard Name
> <email> format.
> 
> 

Applied, thanks!

[1/1] phy: renesas: phy-rzg3e-usb3: Fix malformed MODULE_AUTHOR string
      commit: 53f60930e3d20883364fc01fd46b6099acb8127a

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* Re: [PATCH] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
  To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Abel Vesa
  Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260318-eliza-bindings-qmp-phy-v1-1-96a0d529ad2d@oss.qualcomm.com>


On Wed, 18 Mar 2026 11:54:36 +0200, Abel Vesa wrote:
> Document the compatible for the USB QMP PHY found on the Qualcomm Eliza
> SoC.
> 
> It is fully compatible with the one found on Qualcomm SM8650, so add it
> with the SM8650 as fallback.
> 
> 
> [...]

Applied, thanks!

[1/1] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
      commit: d67a337d28a2d852ff539e983ad6790caf9c95f5

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* Re: [PATCH phy-next 0/3] Lynx 28G: better init(), exit(), power_on(), power_off()
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
  To: linux-phy, Vladimir Oltean
  Cc: netdev, Ioana Ciornei, Neil Armstrong, Josua Mayer, linux-kernel
In-Reply-To: <20260321011451.1557091-1-vladimir.oltean@nxp.com>


On Sat, 21 Mar 2026 03:14:48 +0200, Vladimir Oltean wrote:
> This is a set of 3 improvements to the 28G Lynx SerDes driver as found
> on NXP Layerscape:
> - avoid kernel hangs if lane resets/halts fail due to other bugs
> - actually have phy_power_down() cut power from lanes, not just halt them
> - allow consumers to call phy_exit(), to balance the phy->init_count
> 
> Especially change 3 will allow further development of the dpaa2-eth
> consumer. To permit phy_exit() and other patches in net-next to be
> submitted in this development cycle without functionally breaking
> networking, please apply this change on top of v7.0-rc1 and provide
> it as a stable tag to be pulled in netdev.
> 
> [...]

Applied, thanks!

[1/3] phy: lynx-28g: use timeouts when waiting for lane halt and reset
      commit: 905780855a320ab3dcf0e4eaebf544cb3e7b55f8
[2/3] phy: lynx-28g: truly power the lanes up or down
      commit: 5d38f693f16a0e9470fda530e01994f35fed8644
[3/3] phy: lynx-28g: implement phy_exit() operation
      commit: 0ee5cc59c0ee679e1a3a749cfc47834041763494

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* Re: [PATCH v2] phy: qcom: m31-eusb2: Make USB repeater optional
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
  To: Neil Armstrong, Abel Vesa
  Cc: linux-arm-msm, linux-phy, linux-kernel, Wesley Cheng,
	Dmitry Baryshkov, Bjorn Andersson
In-Reply-To: <20260302-phy-qcom-m31-eusb2-make-repeater-optional-v2-1-dbf714c72056@oss.qualcomm.com>


On Mon, 02 Mar 2026 10:34:46 +0200, Abel Vesa wrote:
> A repeater is not required for the PHY to function. On systems with
> multiple PHY instances connected to a multi-port controller, some PHYs
> may be unconnected. All PHYs must still probe successfully even without
> attached repeaters, otherwise the controller probe fails.
> 
> So make it optional.
> 
> [...]

Applied, thanks!

[1/1] phy: qcom: m31-eusb2: Make USB repeater optional
      commit: a62bfbcf2db4ae6eb7a544a40b1075a81784ea41

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* Re: (subset) [PATCH v4 0/2] Add edp reference clock for lemans
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: robin.clark, lumag, abhinav.kumar, sean, marijn.suijten,
	maarten.lankhorst, mripard, tzimmermann, airlied, simona, robh,
	krzk+dt, conor+dt, quic_mahap, andersson, konradybcio, mani,
	James.Bottomley, martin.petersen, kishon, cros-qcom-dts-watchers,
	Ritesh Kumar
  Cc: linux-phy, linux-arm-msm, dri-devel, freedreno, devicetree,
	linux-kernel, linux-scsi, quic_vproddut
In-Reply-To: <20260128114853.2543416-1-quic_riteshk@quicinc.com>


On Wed, 28 Jan 2026 17:18:48 +0530, Ritesh Kumar wrote:
> On lemans chipset, edp reference clock is being voted by ufs mem phy
> (ufs_mem_phy: phy@1d87000). But after commit 77d2fa54a945
> ("scsi: ufs: qcom : Refactor phy_power_on/off calls") edp reference
> clock is getting turned off, leading to below phy poweron failure on
> lemans edp phy.
> 
> [   19.830220] phy phy-aec2a00.phy.10: phy poweron failed --> -110
> [   19.842112] mdss_0_disp_cc_mdss_dptx0_link_clk status stuck at 'off'
> [   19.842131] WARNING: CPU: 2 PID: 371 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x174/0x18c
> [   19.984356] Hardware name: Qualcomm QCS9100 Ride (DT)
> [   19.989548] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [   19.996697] pc : clk_branch_toggle+0x174/0x18c
> [   20.001267] lr : clk_branch_toggle+0x174/0x18c
> [   20.005833] sp : ffff8000863ebbc0
> [   20.009251] x29: ffff8000863ebbd0 x28: 0000000000000000 x27: 0000000000000000
> [   20.016579] x26: 0000000000000000 x25: 0000000000000000 x24: 0000000000000001
> [   20.023915] x23: ffff0000c53de980 x22: 0000000000000001 x21: ffffb4b57fd8d710
> [   20.031245] x20: ffffb4b5bb238b88 x19: 0000000000000000 x18: ffffffffffff7198
> [   20.038584] x17: 0000000000000014 x16: ffffb4b5bb1e2330 x15: 0000000000000048
> [   20.045926] x14: 0000000000000000 x13: ffffb4b5bd386a48 x12: 0000000000000dfb
> [   20.053263] x11: 00000000000004a9 x10: ffffb4b5bd3e5a20 x9 : ffffb4b5bd386a48
> [   20.060600] x8 : 00000000ffffefff x7 : ffffb4b5bd3dea48 x6 : 00000000000004a9
> [   20.067934] x5 : ffff000eb7d38408 x4 : 40000000fffff4a9 x3 : ffff4b58fb2b7000
> [   20.075269] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000ec4fc3480
> [   20.082601] Call trace:
> [   20.085127]  clk_branch_toggle+0x174/0x18c (P)
> [   20.089705]  clk_branch2_enable+0x1c/0x28
> [   20.093829]  clk_core_enable+0x6c/0xac
> [   20.097687]  clk_enable+0x2c/0x4c
> [   20.101104]  clk_bulk_enable+0x4c/0xd8
> [   20.104964]  msm_dp_ctrl_enable_mainlink_clocks+0x184/0x24c [msm]
> [   20.111294]  msm_dp_ctrl_on_link+0xb0/0x400 [msm]
> [   20.116178]  msm_dp_display_process_hpd_high+0x110/0x190 [msm]
> [   20.122209]  msm_dp_hpd_plug_handle.isra.0+0xac/0x1c4 [msm]
> [   20.127983]  hpd_event_thread+0x320/0x5cc [msm]
> [   20.132680]  kthread+0x12c/0x204
> [   20.136011]  ret_from_fork+0x10/0x20
> [   20.139699] ---[ end trace 0000000000000000 ]---
> [   20.144489] Failed to enable clk 'ctrl_link': -16
> [   20.149340] [drm:msm_dp_ctrl_enable_mainlink_clocks [msm]] *ERROR* Unable to start link clocks. ret=-16
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: phy: qcom-edp: Add reference clock for sa8775p eDP PHY
      commit: 0cc64561b03d755bba54cbd0cf05e9210ab40a13

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* Re: [PATCH 0/6] phy: qcom-qmp: Clean up QSERDES COM and TXRX register headers
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: Shawn Guo
  Cc: Neil Armstrong, Dmitry Baryshkov, Abel Vesa, Konrad Dybcio,
	Xiangxu Yin, Manivannan Sadhasivam, Luca Weiss, linux-kernel,
	linux-arm-msm, linux-phy
In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com>


On Sat, 14 Mar 2026 13:13:19 +0800, Shawn Guo wrote:
> There are some duplications around QSERDES COM and TXRX v2/v3 register
> definitions.  The series tries to clean them up, and also rename
> v2 registers/headers to make the version explicit, just like all other
> versions of the QSERDES registers.
> 
> No functional changes is expected.
> 
> [...]

Applied, thanks!

[1/6] phy: qcom-qmp: Add missing QSERDES COM v2 registers
      commit: 52595824b0027d075470f7f08afe805844c1b079
[2/6] phy: qcom-qmp: Use explicit QSERDES COM v2 register definitions
      commit: 764f409b840ab400253215e765a72b903feb6afd
[3/6] phy: qcom-qmp-usbc: Use register definitions in qserdes-txrx-v3
      commit: 9dfdd6e7bebd63eeef0ba57493adee91c34ae338
[4/6] phy: qcom-qmp-usbc: Rename QCS615 DP PHY variables and functions
      commit: c834f0a69051e5db52172262dadf8f7b5ff58bd0
[5/6] phy: qcom-qmp: Drop unused register headers
      commit: 9b1270d2b85bb7ce6bbc71232375b21d8be0b799
[6/6] phy: qcom-qmp: Make QSERDES TXRX v2 registers explicit
      commit: c7cd4798fafa84581502094d0be282072851c9b7

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* Re: [PATCH] phy: tegra: xusb: Make USB_CONN_GPIO select conditional on GPIOLIB
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: Sasha Levin
  Cc: Neil Armstrong, Thierry Reding, Jonathan Hunter, Niklas Cassel,
	Vidya Sagar, linux-phy, linux-tegra, linux-kernel
In-Reply-To: <20260426000309.54959-1-sashal@kernel.org>


On Sat, 25 Apr 2026 20:03:09 -0400, Sasha Levin wrote:
> kconfiglint reports:
> 
>   K006: config PHY_TEGRA_XUSB selects USB_CONN_GPIO which depends on
>         GPIOLIB, but PHY_TEGRA_XUSB does not depend on GPIOLIB
>   K002: config PHY_TEGRA_XUSB selects visible symbol USB_CONN_GPIO
>         which has dependencies
> 
> [...]

Applied, thanks!

[1/1] phy: tegra: xusb: Make USB_CONN_GPIO select conditional on GPIOLIB
      commit: 18af47764d75bf2cd6297289255fd7f83967e7cf

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* Re: (subset) [PATCH RESEND v3 0/4] Add eMMC PHY support for Axiado AX3000 SoC
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: SriNavmani A, Prasad Bolisetty, Neil Armstrong, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Tzu-Hao Wei
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-kernel, openbmc
In-Reply-To: <20260504-axiado-ax3000-add-emmc-phy-driver-support-v3-0-3ab7eb45b0c5@axiado.com>


On Mon, 04 May 2026 09:38:31 +0800, Tzu-Hao Wei wrote:
> Axiado AX3000 SoC contains Arasan PHY which provides the interface to the
> HS200 eMMC controller.
> 
> This series includes:
> 1. Add bindings for Axiado AX3000 eMMC PHY
> 2. Add Axiado AX3000 eMMC phy driver
> 3. Update MAINTAINERS for the new driver
> 4. Update Axiado AX3000 device tree
> 
> [...]

Applied, thanks!

[1/4] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY
      commit: 1a75ecefa4fbedefc1600e43445de4e1e7f03b55
[2/4] phy: axiado: add Axiado eMMC PHY driver
      commit: 9e7dfa4bcd4e2c3541c4ee954ea5e66edab94d3f
[3/4] MAINTAINERS: Add Axiado AX3000 eMMC PHY driver
      commit: 13ee293a904b7b7b0507aaa8c71f7be7e683800e

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* Re: [PATCH v2] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Abel Vesa
  Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
	Krzysztof Kozlowski
In-Reply-To: <20260504-eliza-bindings-qmp-phy-v2-1-849c4de8d75f@oss.qualcomm.com>


On Mon, 04 May 2026 19:03:41 +0300, Abel Vesa wrote:
> Document the compatible for the USB QMP PHY found on the Qualcomm Eliza
> SoC.
> 
> It is fully compatible with the one found on Qualcomm SM8650, so add it
> with the SM8650 as fallback.
> 
> 
> [...]

Applied, thanks!

[1/1] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Eliza QMP PHY
      commit: d67a337d28a2d852ff539e983ad6790caf9c95f5

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* Re: [PATCH v2] dt-bindings: phy: qcom,snps-eusb2: Document the Eliza Synopsys eUSB2 PHY
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Abel Vesa, Abel Vesa
  Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, Konrad Dybcio
In-Reply-To: <20260504-eliza-bindings-phy-eusb2-v2-1-fa3a1fd65ab1@oss.qualcomm.com>


On Mon, 04 May 2026 19:06:46 +0300, Abel Vesa wrote:
> The Synopsys eUSB2 PHY found on the Eliza SoC is fully compatible with the
> one found the SM8550.
> 
> So document it by adding the compatible to the list that has the SM8550
> one as fallback.
> 
> 
> [...]

Applied, thanks!

[1/1] dt-bindings: phy: qcom,snps-eusb2: Document the Eliza Synopsys eUSB2 PHY
      commit: 78a6a90a5c4ac29d06fc8119885b80f919950d00

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* Re: [PATCH v3] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Nord QMP UFS PHY
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: Shawn Guo
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
	Dmitry Baryshkov, Bartosz Golaszewski, Deepti Jaggi, linux-phy,
	devicetree, linux-arm-msm, linux-kernel
In-Reply-To: <20260504081442.825908-1-shengchao.guo@oss.qualcomm.com>


On Mon, 04 May 2026 16:14:42 +0800, Shawn Guo wrote:
> Document QMP UFS PHY on Qualcomm Nord SoC.
> 
> 

Applied, thanks!

[1/1] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Nord QMP UFS PHY
      commit: 6d6ff64e01ddeb579bf0078e5b6d50c04035541e

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* Re: [PATCH v4 0/2] phy: spacemit: Add USB2 PHY support for K3 SoC
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Ze Huang, Yixun Lan
  Cc: Junzhong Pan, linux-phy, devicetree, linux-riscv, spacemit,
	linux-kernel, Krzysztof Kozlowski, Yao Zi
In-Reply-To: <20260305-11-k3-usb2-phy-v4-0-15554fb933bc@kernel.org>


On Thu, 05 Mar 2026 01:00:50 +0000, Yixun Lan wrote:
> The series trys to add USB2 PHY support for SpacemiT K3 SoC, while
> patch [1/2] implement a disconnect function which is needed during
> next connection.
> 
> No DTS part has been inclueded in this series, instead I plan to
> submit them later while adding USB host support.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: phy: spacemit: k3: add USB2 PHY support
      commit: ad8fdebd40fd25e86331886f4fc6951531691319
[2/2] phy: k1-usb: k3: add USB2 PHY support
      commit: 056ee8b37bc91e3230afa11ec1018fa898b983b8

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* Re: (subset) [PATCH v4 0/5] J722S SGMII support
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
  To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Neil Armstrong,
	Nora Schiffer
  Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
	Paolo Abeni, Siddharth Vadapalli, Roger Quadros, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, netdev, devicetree,
	linux-kernel, linux-phy, linux-arm-kernel, linux
In-Reply-To: <cover.1775559102.git.nora.schiffer@ew.tq-group.com>


On Tue, 07 Apr 2026 13:42:32 +0200, Nora Schiffer wrote:
> The J722S CPSW and SERDES are very similar to the variants found on the
> AM64, but they additionally support SGMII. Introduce new compatible
> strings for the J722S to add this support to the drivers.
> 
> This is a prerequisite for the Single-Pair Ethernet interface of the
> TQ-Systems MBa67xx baseboard for the TQMa67xx SoM, which will be
> submitted separately.
> 
> [...]

Applied, thanks!

[1/5] dt-bindings: phy: ti: phy-j721e-wiz: Add ti,j722s-wiz-10g compatible
      commit: 059f1a4c9e3aa44d888c0e7cf4559403eece0438
[2/5] dt-bindings: phy: ti: phy-gmii-sel: Add ti,j722s-phy-gmii-sel compatible
      commit: 567b3c62a7eb51db4cb562b416ec220132d524c9
[3/5] phy: ti: phy-j721e-wiz: add support for J722S SoC family
      commit: 61849b7afb579630fc45dbeaf5449b42b33cc70e
[4/5] phy: ti: gmii-sel: add support for J722S SoC family
      commit: d39cf00e7daea64889dda9abb0b7e6da04a69d04

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* Re: [PATCH] phy: renesas: rzg3e-usb3: Convert to FIELD_MODIFY()
From: Vinod Koul @ 2026-05-10 12:24 UTC (permalink / raw)
  To: Neil Armstrong, Biju Das, Geert Uytterhoeven; +Cc: linux-phy, linux-renesas-soc
In-Reply-To: <a52020ba597e2e213b161eee21239f10e6057d9d.1772705690.git.geert+renesas@glider.be>


On Thu, 05 Mar 2026 11:15:28 +0100, Geert Uytterhoeven wrote:
> Use the FIELD_MODIFY() helper instead of open-coding the same operation.
> 
> 

Applied, thanks!

[1/1] phy: renesas: rzg3e-usb3: Convert to FIELD_MODIFY()
      commit: 5e2871746039e69657623b222b30c1c6f52159f0

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* Re: [PATCH] phy: spacemit: Remove incorrect clk_disable() in spacemit_usb2phy_init()
From: Vinod Koul @ 2026-05-10 12:24 UTC (permalink / raw)
  To: Neil Armstrong, Yixun Lan, Ze Huang, Felix Gu
  Cc: linux-phy, linux-riscv, spacemit, linux-kernel
In-Reply-To: <20260326-k1-usb3-v1-1-0c2b6adf5185@gmail.com>


On Thu, 26 Mar 2026 00:23:58 +0800, Felix Gu wrote:
> When clk_enable() fails, the clock was never enabled. Calling
> clk_disable() in this error path is incorrect.
> 
> Remove the spurious clk_disable() call from the error handling
> in spacemit_usb2phy_init().
> 
> 
> [...]

Applied, thanks!

[1/1] phy: spacemit: Remove incorrect clk_disable() in spacemit_usb2phy_init()
      commit: a4058c09dd6e28ec33316fd6eb45ddae4cab1f31

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* Re: [PATCH v1] phy: eswin: Fix incorrect error check in probe()
From: Vinod Koul @ 2026-05-10 12:23 UTC (permalink / raw)
  To: neil.armstrong, linux-phy, linux-kernel, Yulin Lu
  Cc: linmin, ningyu, Dan Carpenter
In-Reply-To: <20260413070033.128-1-luyulin@eswincomputing.com>


On Mon, 13 Apr 2026 15:00:33 +0800, Yulin Lu wrote:
> devm_ioremap() returns NULL on failure, not an ERR_PTR.
> Using IS_ERR() to check the return value is incorrect.
> 
> Fix this by checking for NULL and returning -ENOMEM.
> 
> 

Applied, thanks!

[1/1] phy: eswin: Fix incorrect error check in probe()
      commit: c2cd08e8f150738515c8df415ad7ecfa3d38124a

Best regards,
-- 
~Vinod



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* Re: [PATCH] phy: qcom-qmp-ufs: Fix kaanapali PHY PLL lock failure after SM8650 G4 fix
From: Vinod Koul @ 2026-05-10 12:23 UTC (permalink / raw)
  To: neil.armstrong, konrad.dybcio, dmitry.baryshkov, mani, abel.vesa,
	Nitin Rawat
  Cc: linux-arm-msm, linux-phy, linux-kernel, stable
In-Reply-To: <20260415104851.2763238-1-nitin.rawat@oss.qualcomm.com>


On Wed, 15 Apr 2026 16:18:51 +0530, Nitin Rawat wrote:
> Commit 81af9e40e2e4 ("phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4")
> moved QPHY_V6_PCS_UFS_PLL_CNTL register configuration from the shared
> sm8650_ufsphy_g5_pcs table to the SM8650-specific sm8650_ufsphy_pcs base
> table to fix Gear 4 operation on SM8650.
> 
> However, this change inadvertently broke kaanapali and SM8750 SoCs
> which also rely on the shared sm8650_ufsphy_g5_pcs table for Gear 5
> configuration but use their own sm8750_ufsphy_pcs base table. After the
> change, kaanapali PHYs are left without the required PLL_CNTL = 0x33
> setting, causing the PHY PLL to remain at its hardware reset default
> value, preventing PLL lock and resulting in DME_LINKSTARTUP timeouts.
> 
> [...]

Applied, thanks!

[1/1] phy: qcom-qmp-ufs: Fix kaanapali PHY PLL lock failure after SM8650 G4 fix
      commit: 80305760d7a55b884fb9023c490b75568d1ea0b1

Best regards,
-- 
~Vinod



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