* [PATCH v3 net-next 0/2] Add support for dual port USXGMII+SGMII
From: Gokul Praveen @ 2026-06-30 13:43 UTC (permalink / raw)
To: conor+dt, devicetree, krzk+dt, linux-arm-kernel, linux-kernel,
linux-phy, neil.armstrong, nm, robh, sjakhade, kristo, vigneshr,
vkoul, yamonkar
This patch series enables dual port USXGMII and SGMII Ethernet mode
support on the TI J784S4 EVM platform using the CPSW9G Ethernet switch.
The CPSW9G instance supports both SGMII and USXGMII modes simultaneously
on MAC Ports 1 and 2, which connect to ENET Expansion 1 and ENET
Expansion 2 slots through the SERDES2 instance. The series includes:
Multilink SERDES configuration support added to the SERDES2 node by adding
the PLL1 refclk.
v2 <==> v1
===========
* Added modifications to the device tree bindings documentation.
v3 <=> v2
==========
* Added net-next suffix in the patch subject.
* Added a separate bindings patch and added appropriate subject
format expected for Bindings patches.
* Updated the cover letter description
Gokul Praveen (2):
arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node
dt-bindings: phy: cadence-torrent: Update property values to support 3
clocks
.../devicetree/bindings/phy/phy-cadence-torrent.yaml | 4 ++--
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
--
2.34.1
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* [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks
From: Gokul Praveen @ 2026-06-30 13:43 UTC (permalink / raw)
To: conor+dt, devicetree, krzk+dt, linux-arm-kernel, linux-kernel,
linux-phy, neil.armstrong, nm, robh, sjakhade, kristo, vigneshr,
vkoul, yamonkar
In-Reply-To: <20260630134324.61085-1-g-praveen@ti.com>
Update maxItems value of "clocks" property to 3 as description of
this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
and phy_en_refclk(optional))
Update the "clock-names" property as well with the 3 clocks.
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
.../devicetree/bindings/phy/phy-cadence-torrent.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 9af39b33646a..54fe78da297a 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -34,7 +34,7 @@ properties:
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 3
description:
PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
pll1_refclk is optional and used for multi-protocol configurations requiring
@@ -47,7 +47,7 @@ properties:
minItems: 1
items:
- const: refclk
- - enum: [ pll1_refclk, phy_en_refclk ]
+ - enum: [refclk, pll1_refclk, phy_en_refclk ]
reg:
minItems: 1
--
2.34.1
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* Re: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks
From: sashiko-bot @ 2026-06-30 13:48 UTC (permalink / raw)
To: Gokul Praveen
Cc: neil.armstrong, olteanv, devicetree, linux-phy, conor+dt, robh,
vkoul
In-Reply-To: <20260630134324.61085-3-g-praveen@ti.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `clock-names` schema definition incorrectly restricts the array to a maximum of 2 items and allows duplicate clock names. While the commit correctly updates `clocks` to allow `maxItems: 3`, it only modifies the second element of the `items` array for `clock-names`. In `dt-schema` (based on JSON Schema), defining `items` as an array of schemas implicitly limits the maximum number of items to the length of that array (because `additionalItems` is implicitly false). As a result, a device tree specifying 3 clocks will fail `dt_binding_check` validation. Additionally, adding `refclk` to the second element's `enum` creates a logic error, permitting redundant sequences such as `clock-names = "refclk", "refclk";`.
--
commit d737f6b2f91949e839e21f62c39ca9db8f322775
Author: Gokul Praveen <g-praveen@ti.com>
dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks
This commit updates the Cadence Torrent PHY device tree binding to support up
to 3 clocks. It increases the maxItems of the clocks property and updates the
clock-names property.
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646ac..54fe78da297a2 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>
> clocks:
> minItems: 1
> - maxItems: 2
> + maxItems: 3
> description:
> PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
[ ... ]
> @@ -47,7 +47,7 @@ properties:
> minItems: 1
> items:
> - const: refclk
> - - enum: [ pll1_refclk, phy_en_refclk ]
> + - enum: [refclk, pll1_refclk, phy_en_refclk ]
[Severity: Medium]
Will this fail schema validation when a device tree specifies 3 clocks?
Because the items sequence for clock-names only defines two elements, it
implicitly restricts the array to a maximum of 2 items. Even though the clocks
property was updated to maxItems: 3 above, the clock-names array is now
mismatched and will reject 3 items during dt_binding_check.
Also, does this unintentionally allow duplicate clock names? Adding refclk to
the second element's enum makes it possible to define a redundant sequence
like clock-names = "refclk", "refclk".
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260630134324.61085-1-g-praveen@ti.com?part=2
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* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform
From: Konrad Dybcio @ 2026-06-30 13:50 UTC (permalink / raw)
To: Rakesh Kota, Dmitry Baryshkov
Cc: Kamal Wadhwa, linux-arm-msm, sashiko-reviews, Komal Bajaj, robh,
linux-phy, neil.armstrong, vkoul, olteanv, krzk+dt, conor+dt,
devicetree, Jishnu Prakash
In-Reply-To: <20260630124220.4lja4zshpf66kwj3@hu-kotarake-hyd.qualcomm.com>
On 6/30/26 2:42 PM, Rakesh Kota wrote:
> On Sun, Jun 28, 2026 at 03:33:23PM +0300, Dmitry Baryshkov wrote:
>> On Thu, Jun 25, 2026 at 09:11:19PM +0530, Kamal Wadhwa wrote:
>>> On Wed, Jun 17, 2026 at 03:48:14PM +0300, Dmitry Baryshkov wrote:
>>>> On Mon, 18 May 2026 at 14:49, Kamal Wadhwa
>>>> <kamal.wadhwa@oss.qualcomm.com> wrote:
>>>>>
>>>>> On Sun, May 17, 2026 at 08:18:15PM +0300, Dmitry Baryshkov wrote:
>>>>>> On Thu, May 14, 2026 at 04:09:18PM +0530, Kamal Wadhwa wrote:
>>>>>>> On Wed, May 13, 2026 at 06:14:20PM +0300, Dmitry Baryshkov wrote:
>>>>>>>> On 13/05/2026 17:29, Rakesh Kota wrote:
>>>>>>>>> On Wed, May 13, 2026 at 03:01:47PM +0300, Dmitry Baryshkov wrote:
>>>>>>>>>> On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote:
>>>>>>>>>>> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
>>>>>>>>>>> - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy.
>>>>>>>>>>> - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125).
>>>>>>>>>>> --
>>>>>>>>>>>> +
>>>>>>>>>>>> + pm4125_s2: s2 {
>>>>>>>>>>>> + regulator-min-microvolt = <1000000>;
>>>>>>>>>>>> + regulator-max-microvolt = <1200000>;
>>>>>>>>>>>> + };
>>>>>>>>>>>
>>>>>>>>>>> Do these regulators need to explicitly define their input supply dependencies
>>>>>>>>>>> such as vdd_s2-supply?
>>>>>>>>>>>
>>>>>>>>>>> Without these properties, the regulator framework might be unaware that the
>>>>>>>>>>> PMIC regulators draw power from upstream supplies.
>>>>>>>>>>>
>>>>>>>>>>> If the kernel dynamically manages the upstream supply and its reference count
>>>>>>>>>>> drops to zero, could it be disabled, causing an unexpected power loss for
>>>>>>>>>>> downstream components?
>>>>>>>>>>
>>>>>>>>>> And this is a correct comment. Please provide missing supplies.
>>>>>>>>>>
>>>>>>>>> As per the Qualcomm system design, the parent-child supply relationship
>>>>>>>>> is managed by the RPM firmware, not the Linux regulator framework. The
>>>>>>>>> RPM ensures the parent supply is never disabled until all subsystem
>>>>>>>>> votes are cleared.
>>>>>>>>
>>>>>>>> How is this different from other, previous platforms?
>>>>>>>
>>>>>>> This is not different. In the previous platforms too this is taken care from the
>>>>>>> RPM/RPMH firmware side, the only case where we may need explicit vote to parent
>>>>>>> is for non-rpmh/rpm regulator rails (like i2c based regulator pm8008), which
>>>>>>> may have a RPM/RPMH regulator as a parent.
>>>>>>>
>>>>>>> Even on those previous targets the parent rail of all RPM/RPMH regulators are
>>>>>>> internally voted by RPM/RPMH FW at proper voltage with required headroom
>>>>>>> calculated based on the active child rails. This was done for all the
>>>>>>> subsystems (including APPS) regulators.
>>>>>>>
>>>>>>> So no explicit handling from the APPS is required for parent supply.
>>>>>>
>>>>>> You are explaining the driver behaviour. But the question is about the
>>>>>> hardware description. If there is no difference, please add necessary
>>>>>> supplies back.
>>>>>
>>>>> I understand your concern about descibing the parent-child relation in the
>>>>> devicetree, and given that we have been almost always followed this for all
>>>>> the previous targets, it will expected of us to add them.
>>>>
>>>> Yes.
>>>>
>>>>>
>>>>> However, we want to avoid the unnecessary access to the parent from APPS.
>>>>
>>>> Why? What is the reason? Do we want to do the same for all the
>>>> platforms? Only for Shikra? Something else?
>>>>
>>>>> At the moment, I do not see a way to avoid that, if we add the parent
>>>>> regulators.
>>>>
>>>> That depend on the answer to the previous question. In the end, we can
>>>> make the driver ignore the parents by removing them from the regulator
>>>> desc.
>>>
>>> Ok, this seems like a good suggestion, so you mean its ok if we define the
>>> regulator desc's supply column with NULL? And only keep that in the DT?
>>>
>>> you mean like this?
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/regulator/qcom-rpmh-regulator.c?h=v7.1#n1453
>>>
>>> (please let me know if i got that right. thanks)
>>
>> Yes. Don't forget to explain in the commit message, why you are doing
>> so.
>
> Currently, Agatti uses the same PMIC, so we cannot set the driver
> supply name reference to NULL. Since it's an older target,
> we'll need to run a regression before making any driver-level changes.
>
> Additionally, the child-to-parent regulator ganging differs between
> Shikra and Agatti:
>
> - On Agatti, l3 regulator is ganged with vdd_l13_l14_l15_l16
> - On Shikra, l3 is ganged with vdd_l2_l3
Is it configurable on the PMIC level? I was under the impression the
supply maps are fixed in hardware. Is there a chance the agatti
description is just wrong?
Konrad
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* Re: [PATCH v3 net-next 1/2] arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node
From: sashiko-bot @ 2026-06-30 13:53 UTC (permalink / raw)
To: Gokul Praveen
Cc: linux-phy, devicetree, olteanv, vkoul, neil.armstrong, conor+dt,
robh
In-Reply-To: <20260630134324.61085-2-g-praveen@ti.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
New issues:
- [Low] Adding a third clock to the 'serdes2' node violates the 'phy-cadence-torrent.yaml' DT binding. The subsequent binding update in the series is logically incomplete and fails to resolve the validation error.
- [Low] Missing whitespace after the comma in the 'clock-names' list.
Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but the commit fails to comprehensively fix the issue. It adds 'pll1_refclk' to fix multilink configuration for 'serdes2', but ignores identical SERDES nodes ('serdes0', 'serdes1', 'serdes4') that share the exact same bug.
--
commit c37d528887d49433e9d33970e77ad622c557ad5e
Author: Gokul Praveen <g-praveen@ti.com>
arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node
This commit adds the PLL1 refclk to the clocks and clock-names parameters
for the SERDES2 node. It addresses a multilink configuration failure that
occurs without PLL1 being present in the clocks list.
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 78fcd0c40abcf..da8d582574d03 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -122,8 +122,9 @@ serdes2: serdes@5020000 {
> resets = <&serdes_wiz2 0>;
> reset-names = "torrent_reset";
> clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
> <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
[Severity: High]
This is a pre-existing issue, but does the same fix need to be applied to
the other identical serdes nodes?
Other nodes like serdes0, serdes1, and serdes4 in
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi share the exact same
configuration issue where TI_WIZ_PLL1_REFCLK is in assigned-clocks but absent
from clocks:
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
Since serdes0 is also configured for multilink (PCIe + USB), will its
configuration fail without a similar update?
> - clock-names = "refclk", "phy_en_refclk";
> + clock-names = "refclk","pll1_refclk", "phy_en_refclk";
[Severity: Low]
Will this addition cause make dtbs_check to fail?
Adding a third item to clock-names exceeds the currently defined items in the
phy-cadence-torrent.yaml binding.
Even if a subsequent patch in the series updates the schema by modifying
maxItems and the enum for the second item, dt-schema enforces
additionalItems: false for arrays.
Unless a third item definition is explicitly added to the items array in the
schema, won't validation fail for this node?
[Severity: Low]
this isn't a bug, but there is a missing space after the first comma.
--
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* Re: [PATCH v4 3/5] arm64: dts: qcom: Add Shikra CQ2390M SoM platform
From: Konrad Dybcio @ 2026-06-30 13:56 UTC (permalink / raw)
To: Komal Bajaj, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Wesley Cheng, Ulf Hansson
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
monish.chunara, Rakesh Kota
In-Reply-To: <20260527-shikra-dt-v4-3-b5ca1fa0b392@oss.qualcomm.com>
On 5/27/26 5:53 PM, Komal Bajaj wrote:
> Add device tree include for the CQ2390M variant of the Shikra
> System-on-Module, a compact compute module integrating the Shikra SoC
> and PMIC for IoT applications, designed to mount on carrier boards.
>
> - shikra-cqm-som.dtsi: Retail SoM with modem (PM4125 and PM8005 PMIC)
>
> The DTSI includes the common shikra.dtsi, adds PM4125 and PM8005 PMIC
> peripheral definitions specific to this variant. Since PM8005 regulators
> are controlled by rpmpd, so disabling the pm8005 regulators.
>
> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
I'll pretend I don't see an issue with a volume button living on the
SoM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* Re: [PATCH v4 4/5] arm64: dts: qcom: Add Shikra IQ2390S SoM platform
From: Konrad Dybcio @ 2026-06-30 13:56 UTC (permalink / raw)
To: Komal Bajaj, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Wesley Cheng, Ulf Hansson
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
monish.chunara
In-Reply-To: <20260527-shikra-dt-v4-4-b5ca1fa0b392@oss.qualcomm.com>
On 5/27/26 5:53 PM, Komal Bajaj wrote:
> Add device tree include for the IQ2390S variant of the Shikra
> System-on-Module, an industrial compute module integrating the Shikra
> SoC and PMIC for industrial IoT applications, designed to mount on
> carrier boards.
>
> - shikra-iqs-som.dtsi: Industrial SoM without modem (PM8150 PMIC)
>
> The DTSI includes the common shikra.dtsi and adds PM8150 PMIC regulator
> definitions specific to this variant.
>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* Re: [PATCH v6 3/5] arm64: dts: qcom: Add Shikra CQ2390M SoM platform
From: Konrad Dybcio @ 2026-06-30 13:57 UTC (permalink / raw)
To: Komal Bajaj, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Wesley Cheng, Ulf Hansson
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
monish.chunara, Rakesh Kota, Dmitry Baryshkov
In-Reply-To: <20260612-shikra-dt-v6-3-6b6cb58db477@oss.qualcomm.com>
On 6/12/26 7:27 PM, Komal Bajaj wrote:
> Add device tree include for the CQ2390M variant of the Shikra
> System-on-Module, a compact compute module integrating the Shikra SoC
> and PMIC for IoT applications, designed to mount on carrier boards.
>
> - shikra-cqm-som.dtsi: Retail SoM with modem (PM4125 and PM8005 PMIC)
>
> The DTSI includes the common shikra.dtsi, adds PM4125 and PM8005 PMIC
> peripheral definitions specific to this variant. Since PM8005 regulators
> are controlled by rpmpd, so disabling the pm8005 regulators.
>
> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* Re: [PATCH v6 4/5] arm64: dts: qcom: Add Shikra IQ2390S SoM platform
From: Konrad Dybcio @ 2026-06-30 13:57 UTC (permalink / raw)
To: Komal Bajaj, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Wesley Cheng, Ulf Hansson
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
monish.chunara, Dmitry Baryshkov
In-Reply-To: <20260612-shikra-dt-v6-4-6b6cb58db477@oss.qualcomm.com>
On 6/12/26 7:27 PM, Komal Bajaj wrote:
> Add device tree include for the IQ2390S variant of the Shikra
> System-on-Module, an industrial compute module integrating the Shikra
> SoC and PMIC for industrial IoT applications, designed to mount on
> carrier boards.
>
> - shikra-iqs-som.dtsi: Industrial SoM without modem (PM8150 PMIC)
>
> The DTSI includes the common shikra.dtsi and adds PM8150 PMIC regulator
> definitions specific to this variant.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* Re: [PATCH v3 0/4] phy: qcom: qmp-pcie: Add PCIe PHY support for Hawi
From: Matthew Leung @ 2026-06-30 16:25 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Krzysztof Kozlowski
In-Reply-To: <20260618-hawi-phy-pcie-v3-0-3fa42ca45ea4@oss.qualcomm.com>
Hello,
Gentle ping for this patch series.
Best regards,
Matthew Leung
On Thu, Jun 18, 2026 at 09:54:35PM +0000, Matthew Leung wrote:
> This series adds QMP PCIe PHY support for the Qualcomm Hawi SoC. The Hawi
> platform features two PCIe PHY configurations: Gen3 x2 and Gen4 x1.
>
> The Gen3 x2 PHY uses v10 register definitions, while the Gen4 x1 PHY uses
> v10.60 register definitions.
>
> The series adds:
> - device tree bindings
> - v10 register offset headers
> - v10.60 register offset headers
> - driver support with PHY initialization tables for both configurations
>
> Overlap:
> The series has overlap with "phy: qcom: Introduce USB support for Hawi"
> by Ronak Raheja (see link [1]). Both patch series introduce a subset of
> v10 registers (this series for PCIe and Ronak's for USB). I have
> coordinated with Ronak regarding the overlap, and we can update the
> series to resolve any overlap based on the order of merging.
>
> Link: https://lore.kernel.org/all/20260508213234.4643-1-ronak.raheja@oss.qualcomm.com/ [1]
>
> Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> ---
> Changes in v3:
> - Squashed v10 register offsets into a single change
> - Squashed v10.60 register offsets into a single change
> - Removed USB mentions from header comments; offsets are PCIe-specific
> - Reused the tx offset for the v10.60 combined txrx module instead of
> introducing a separate txrx offset
> - Link to v2: https://patch.msgid.link/20260604-hawi-phy-pcie-v2-0-be908d3560db@oss.qualcomm.com
>
> Changes in v2:
> - Rebased onto v7.1-rc6
> - Patch 1: no change (Reviewed-by carried forward)
> - Patch 9: rename QPHY_PCIE_V10_60_PCS_PCS_TX_RX_CONFIG to
> QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG to be consistent with the
> naming convention used in previous pcs-pcie headers
> - Patch 10: update usage of renamed macro
> - Link to v1: https://patch.msgid.link/20260508-hawi-phy-pcie-v1-0-237b894353fc@oss.qualcomm.com
>
> To: Vinod Koul <vkoul@kernel.org>
> To: Neil Armstrong <neil.armstrong@linaro.org>
> To: Rob Herring <robh@kernel.org>
> To: Krzysztof Kozlowski <krzk+dt@kernel.org>
> To: Conor Dooley <conor+dt@kernel.org>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-phy@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
>
> ---
> Matthew Leung (4):
> dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Hawi compatibles
> phy: qcom-qmp: Add v10 register offsets
> phy: qcom-qmp: Add v10.60 register offsets
> phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Hawi
>
> .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 +
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 375 +++++++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h | 18 +
> .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h | 26 ++
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 22 ++
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h | 23 ++
> .../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 49 +++
> .../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h | 55 +++
> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 47 +++
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h | 109 ++++++
> drivers/phy/qualcomm/phy-qcom-qmp.h | 10 +
> 11 files changed, 740 insertions(+)
> ---
> base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
> change-id: 20260506-hawi-phy-pcie-283933b4113e
>
> Best regards,
> --
> Matthew Leung <matthew.leung@oss.qualcomm.com>
>
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* [PATCH V2 0/2] arm64: dts: qcom: Shikra SD Card support
From: Monish Chunara @ 2026-06-30 16:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng,
Ulf Hansson, Kernel Team
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
Nitin Rawat, Pradeep Pragallapati, Komal Bajaj, Monish Chunara,
Konrad Dybcio
This is v2 of the Shikra SD Card support series.
This series adds SD card support for the Shikra platform.
The first patch adds the SDHC2 controller node and the necessary pinctrl
configurations to the base Shikra SoC dtsi. The second patch enables
this support on the Shikra EVK (CQS, CQM, and IQS variants) by defining
the regulator supplies and the card detection GPIO.
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
Changes in v2:
- Rectify the alignment for clocks and interconnect properties for SD
card
- Link to v1: https://lore.kernel.org/all/20260604122045.494712-1-monish.chunara@oss.qualcomm.com
Testing:
- Validated on Shikra EVK variants.
This series depends on:
- https://lore.kernel.org/all/20260612-shikra-dt-v6-2-6b6cb58db477@oss.qualcomm.com
Monish Chunara (2):
arm64: dts: qcom: Add SD Card support for Shikra SoC
arm64: dts: qcom: Enable SD card for Shikra EVK
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 18 ++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 18 ++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 18 ++++
arch/arm64/boot/dts/qcom/shikra.dtsi | 97 +++++++++++++++++++++
4 files changed, 151 insertions(+)
--
2.34.1
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^ permalink raw reply
* [PATCH V2 1/2] arm64: dts: qcom: Add SD Card support for Shikra SoC
From: Monish Chunara @ 2026-06-30 16:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng,
Ulf Hansson, Kernel Team
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
Nitin Rawat, Pradeep Pragallapati, Komal Bajaj, Monish Chunara,
Konrad Dybcio
In-Reply-To: <20260630165700.1886608-1-monish.chunara@oss.qualcomm.com>
Add support for SD card on Shikra SoC and enable the required pinctrl
configurations.
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 97 ++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index e67fe047a683..cfdee8a2526e 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -829,6 +829,53 @@ rclk-pins {
bias-bus-hold;
};
};
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <14>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <14>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <14>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_card_det_n: sd-card-det-n-state {
+ pins = "gpio89";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
pmu@c91000 {
@@ -1081,6 +1128,56 @@ opp-384000000 {
};
};
+ sdhc_2: mmc@4784000 {
+ compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x4784000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ bus-width = <4>;
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ iommus = <&apps_smmu 0x0a0 0x0>;
+
+ interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &config_noc SLAVE_SDCC_2 RPM_ACTIVE_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table-2 {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+ };
+ };
+
gpi_dma0: dma-controller@4a00000 {
compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x04a00000 0x0 0x60000>;
--
2.34.1
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^ permalink raw reply related
* [PATCH V2 2/2] arm64: dts: qcom: Enable SD card for Shikra EVK
From: Monish Chunara @ 2026-06-30 16:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng,
Ulf Hansson, Kernel Team
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
Nitin Rawat, Pradeep Pragallapati, Komal Bajaj, Monish Chunara,
Konrad Dybcio
In-Reply-To: <20260630165700.1886608-1-monish.chunara@oss.qualcomm.com>
Enable SD card for Shikra CQS, CQM and IQS EVK variants. Configure the
vmmc/vqmmc regulators and gpio-based card detection for each board
variant.
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 18 ++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 18 ++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 18 ++++++++++++++++++
3 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 683b5245923b..8212bd41f74e 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -7,6 +7,7 @@
#include "shikra-cqm-som.dtsi"
#include "shikra-evk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Shikra CQM EVK";
@@ -15,6 +16,7 @@ / {
aliases {
mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
serial0 = &uart0;
serial1 = &uart8;
};
@@ -95,6 +97,22 @@ &sdhc_1 {
status = "okay";
};
+&sdhc_2 {
+ vmmc-supply = <&pm4125_l21>;
+ vqmmc-supply = <&pm4125_l4>;
+
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
&uart8 {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index 26ff8007a819..5341e145977c 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -7,6 +7,7 @@
#include "shikra-cqm-som.dtsi"
#include "shikra-evk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Shikra CQS EVK";
@@ -15,6 +16,7 @@ / {
aliases {
mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
serial0 = &uart0;
serial1 = &uart8;
};
@@ -95,6 +97,22 @@ &sdhc_1 {
status = "okay";
};
+&sdhc_2 {
+ vmmc-supply = <&pm4125_l21>;
+ vqmmc-supply = <&pm4125_l4>;
+
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
&uart8 {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index fd691d53a0fa..0548de0d3a74 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -7,6 +7,7 @@
#include "shikra-iqs-som.dtsi"
#include "shikra-evk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Shikra IQS EVK";
@@ -15,6 +16,7 @@ / {
aliases {
mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
serial0 = &uart0;
serial1 = &uart8;
};
@@ -103,6 +105,22 @@ &sdhc_1 {
status = "okay";
};
+&sdhc_2 {
+ vmmc-supply = <&pm8150_l10>;
+ vqmmc-supply = <&pm8150_l2>;
+
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
&uart8 {
status = "okay";
--
2.34.1
--
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* Re: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks
From: Conor Dooley @ 2026-06-30 17:05 UTC (permalink / raw)
To: Gokul Praveen
Cc: conor+dt, devicetree, krzk+dt, linux-arm-kernel, linux-kernel,
linux-phy, neil.armstrong, nm, robh, sjakhade, kristo, vigneshr,
vkoul, yamonkar
In-Reply-To: <20260630134324.61085-3-g-praveen@ti.com>
[-- Attachment #1.1: Type: text/plain, Size: 1647 bytes --]
On Tue, Jun 30, 2026 at 07:13:24PM +0530, Gokul Praveen wrote:
> Update maxItems value of "clocks" property to 3 as description of
> this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
> and phy_en_refclk(optional))
>
> Update the "clock-names" property as well with the 3 clocks.
>
> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
> ---
> .../devicetree/bindings/phy/phy-cadence-torrent.yaml | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646a..54fe78da297a 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>
> clocks:
> minItems: 1
> - maxItems: 2
> + maxItems: 3
> description:
> PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
> pll1_refclk is optional and used for multi-protocol configurations requiring
> @@ -47,7 +47,7 @@ properties:
> minItems: 1
> items:
> - const: refclk
> - - enum: [ pll1_refclk, phy_en_refclk ]
> + - enum: [refclk, pll1_refclk, phy_en_refclk ]
This does not do what you want it to do, I would think, since it means
you can only have two clock names.
Additionally, please restrict 3 clocks to only whatever new TI device
actually has 3 clocks.
pw-bot: changes-requested
Thanks,
Conor.
>
> reg:
> minItems: 1
> --
> 2.34.1
>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 112 bytes --]
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^ permalink raw reply
* [PATCH 0/9] PCI: qcom: Add PCIe support for Shikra SoC
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
Add PCIe support for Shikra target, by adding dt-bindings for phy,
controller and corresponding phy & controller drivers/device-tree
changes.
Shikra RC is connected to TC9563 PCIe switch on all three
EVK variants: CQS, CQM and IQS. The individual downstream ports
of TC9563 connect like below:
DSP1: M.2 B-Key for 5G Modem
DSP2: M.2 M-Key for NVMe
DSP3: Embedded ethernet device
Power and reset to M.2 B and M.2 M slot are controlled via
TC9563 GPIO's. Hence, add DT nodes to enable TC9563 switch
and include corresponding changes to configure power/reset
to TC9563 endpoints as part of power on sequence.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
Sushrut Shree Trivedi (9):
dt-bindings: phy: sc8280xp-qmp-pcie: Document Shikra PCIe phy
dt-bindings: PCI: qcom: Document the Shikra PCIe Controller
dt-bindings: PCI: Add bindings for endpoint gpios
PCI: qcom: Add support for Shikra
phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Shikra
PCI/pwrctrl: tc9563: Add API to control endpoint power and reset
arm64: dts: qcom: shikra: Add PCIe PHY and controller nodes
arm64: dts: qcom: shikra-evk: Add TC9563 PCIe switch node for PCIe
arm64: dts: qcom: shikra-(cqm/cqs/iqs)-evk: Enable PCIe PHY node
.../devicetree/bindings/pci/qcom,shikra-pcie.yaml | 211 +++++++++++++++++++++
.../devicetree/bindings/pci/toshiba,tc9563.yaml | 22 ++-
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 +
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 7 +
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 7 +
arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 152 +++++++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 7 +
arch/arm64/boot/dts/qcom/shikra.dtsi | 154 +++++++++++++++
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c | 152 ++++++++++++---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 73 +++++++
11 files changed, 764 insertions(+), 24 deletions(-)
---
base-commit: 565fa02f75448ce1ddd18bda6b31ad985cf75411
change-id: 20260701-shikra-upstream-14b8668f1001
Best regards,
--
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^ permalink raw reply
* [PATCH 1/9] dt-bindings: phy: sc8280xp-qmp-pcie: Document Shikra PCIe phy
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Document the compatible of the Shikra PCIe phy which supports
Gen2x1.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 108cf9dc86ea..b9b0fa26347b 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -34,6 +34,7 @@ properties:
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
- qcom,sdx65-qmp-gen4x2-pcie-phy
+ - qcom,shikra-qmp-gen2x1-pcie-phy
- qcom,sm8150-qmp-gen3x1-pcie-phy
- qcom,sm8150-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
@@ -166,6 +167,7 @@ allOf:
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
+ - qcom,shikra-qmp-gen2x1-pcie-phy
- qcom,sm8150-qmp-gen3x1-pcie-phy
- qcom,sm8150-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
--
2.43.0
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* [PATCH 2/9] dt-bindings: PCI: qcom: Document the Shikra PCIe Controller
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Add a dedicated schema for the PCIe controller found on the Shikra
platform.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
.../devicetree/bindings/pci/qcom,shikra-pcie.yaml | 211 +++++++++++++++++++++
1 file changed, 211 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml
new file mode 100644
index 000000000000..f9d1dba9dd2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml
@@ -0,0 +1,211 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,shikra-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shikra PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm Shikra SoC (and compatible) PCIe root complex controller is based on
+ the Synopsys DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,shikra-pcie
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 7
+ maxItems: 9
+
+ clock-names:
+ minItems: 7
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_memnoc_pcie # PCIe SF MEMNOC clock
+ - const: tile # PCIe tile SYS NoC clock
+ - const: qmip_pcie_ahb # QMIP PCIe AHB clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 9
+
+ interrupt-names:
+ minItems: 8
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: pci # PCIe core reset
+ - const: link_down # PCIe link down reset
+
+required:
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
+ #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@45e8000 {
+ device_type = "pci";
+ compatible = "qcom,shikra-pcie";
+ reg = <0x0 0x045e8000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf1d>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x1000>,
+ <0x0 0x60100000 0x0 0x100000>,
+ <0x0 0x045eb000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>,
+ <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x0000000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
+ <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>,
+ <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_memnoc_pcie",
+ "tile",
+ "qmip_pcie_ahb";
+
+ assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&system_noc MASTER_PCIE2_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &config_noc SLAVE_PCIE2_0 RPM_ACTIVE_TAG>;
+
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x800 0x1>,
+ <0x100 &apps_smmu 0x801 0x1>;
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_GDSC>;
+
+ max-link-speed = <2>;
+
+ operating-points-v2 = <&pcie_opp_table>;
+
+ status = "disabled";
+
+ pcie_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <250000 1>;
+ opp-level = <1>;
+ };
+
+ /* GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <500000 1>;
+ opp-level = <2>;
+ };
+ };
+ };
+ };
--
2.43.0
--
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* [PATCH 3/9] dt-bindings: PCI: Add bindings for endpoint gpios
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Add devicetree bindings for TC9563 GPIO's which are
used to control endpoint power and reset.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
.../devicetree/bindings/pci/toshiba,tc9563.yaml | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
index b3ad05d90201..f9f71f28aa92 100644
--- a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
+++ b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml
@@ -26,6 +26,11 @@ properties:
reg:
maxItems: 1
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
resx-gpios:
maxItems: 1
description:
@@ -69,6 +74,17 @@ $defs:
type: object
properties:
+ reset-gpios:
+ description:
+ Specify the TC9563 GPIO used to reset the endpoint
+ connected to the particular TC9563 downstream port.
+
+ ep-pwr-en-gpios:
+ description:
+ Specify the TC9563 GPIO used for enabling power to
+ the endpoint connected to the particular TC9563
+ downstream port.
+
toshiba,tx-amplitude-microvolt:
description:
Change Tx Margin setting for low power consumption.
@@ -104,7 +120,7 @@ examples:
#address-cells = <3>;
#size-cells = <2>;
- pcie@0 {
+ tc9563: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -120,6 +136,7 @@ examples:
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
+ #gpio-cells = <2>;
ranges;
bus-range = <0x02 0xff>;
@@ -154,6 +171,9 @@ examples:
device_type = "pci";
ranges;
bus-range = <0x04 0xff>;
+
+ ep-pwr-en-gpio = <&tc9563 2 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tc9563 5 GPIO_ACTIVE_LOW>;
};
pcie@3,0 {
--
2.43.0
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* [PATCH 4/9] PCI: qcom: Add support for Shikra
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Add support for the single PCIe controller on Shikra platform
which is capable of Gen2x1 operation.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index d8eb52857f69..19daadee65f7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -2309,6 +2309,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
+ { .compatible = "qcom,shikra-pcie", .data = &cfg_1_9_0 },
{ }
};
--
2.43.0
--
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* [PATCH 5/9] phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Shikra
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Add QMP PCIe PHY Gen2x1 support.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 73 ++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index d3effad7a074..e0995e4d5f2d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2172,6 +2172,50 @@ static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
};
+static const struct qmp_phy_init_tbl shikra_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0xf),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x6),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0xf),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x9),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x3),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0xd),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x35),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x4),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_EP_DIV, 0x19),
+};
+
static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
@@ -3911,6 +3955,32 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
.phy_status = PHYSTATUS,
};
+static const struct qmp_phy_cfg shikra_pciephy_cfg = {
+ .lanes = 1,
+
+ .offsets = &qmp_pcie_offsets_v2,
+
+ .tbls = {
+ .serdes = shikra_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(shikra_pcie_serdes_tbl),
+ .tx = qcs615_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl),
+ .rx = qcs615_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl),
+ .pcs = qcs615_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl),
+ },
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = pciephy_v2_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+};
+
+
static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.lanes = 1,
@@ -5603,6 +5673,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
}, {
.compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
.data = &sdx65_qmp_pciephy_cfg,
+ }, {
+ .compatible = "qcom,shikra-qmp-gen2x1-pcie-phy",
+ .data = &shikra_pciephy_cfg,
}, {
.compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
.data = &sm8250_qmp_gen3x1_pciephy_cfg,
--
2.43.0
--
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* [PATCH 6/9] PCI/pwrctrl: tc9563: Add API to control endpoint power and reset
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Some platform utilise TC9563 GPIOs to enable power and
control reset of endpoints.
This patch adds support to parse endpoint reset and power enable
gpios from each TC9563 port node in the devicetree. To configure
these GPIO's during the POWER ON sequence, two new API's are
introduced: tc9563_ep_pwr_en() and tc9563_ep_assert_deassert_reset().
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c | 152 ++++++++++++++++++++++++++-----
1 file changed, 129 insertions(+), 23 deletions(-)
diff --git a/drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c b/drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c
index 1555e8a9b3ca..de68b9836645 100644
--- a/drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c
+++ b/drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c
@@ -62,6 +62,8 @@
#define TC9563_TX_MARGIN_MIN_UA 400000
+#define TC9563_GPIO_NONE (-1)
+
/*
* From TC9563 PORSYS rev 0.2, figure 1.1 POR boot sequence
* wait for 10ms for the internal osc frequency to stabilize.
@@ -91,6 +93,10 @@ struct tc9563_pwrctrl_cfg {
u8 nfts[2]; /* GEN1 & GEN2 */
bool disable_dfe;
bool disable_port;
+
+ int ep_reset_gpio;
+ int ep_pwr_en_gpio;
+
};
#define TC9563_PWRCTL_MAX_SUPPLY 6
@@ -256,6 +262,89 @@ static int tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl *tc9563,
ARRAY_SIZE(common_pwroff_seq));
}
+static int tc9563_pwrctrl_ep_pwr_en(struct tc9563_pwrctrl *tc9563,
+ enum tc9563_pwrctrl_ports port,
+ bool enable, int ep_pwr_en_gpio)
+{
+ u32 ep_pwr_en_gpio_mask, val;
+ int ret;
+
+ if (ep_pwr_en_gpio == TC9563_GPIO_NONE)
+ return 0;
+
+ ep_pwr_en_gpio_mask = BIT(ep_pwr_en_gpio);
+
+ /* Set TC9563 GPIO as output */
+ ret = tc9563_pwrctrl_i2c_read(tc9563->client, TC9563_GPIO_CONFIG,
+ &val);
+ if (ret)
+ return ret;
+
+ val &= ~ep_pwr_en_gpio_mask;
+
+ ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_GPIO_CONFIG,
+ val);
+ if (ret)
+ return ret;
+
+ /* Toggle 0->1 to enable power */
+ ret = tc9563_pwrctrl_i2c_read(tc9563->client, TC9563_RESET_GPIO,
+ &val);
+ if (ret)
+ return ret;
+
+ val = enable ? (val | ep_pwr_en_gpio_mask) : (val & ~ep_pwr_en_gpio_mask);
+
+ return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_RESET_GPIO, val);
+
+}
+
+static int tc9563_pwrctrl_ep_assert_deassert_reset(struct tc9563_pwrctrl *tc9563,
+ enum tc9563_pwrctrl_ports port,
+ bool deassert, int ep_reset_gpio)
+{
+ u32 ep_reset_gpio_mask, val;
+ int ret;
+
+ if (ep_reset_gpio == TC9563_GPIO_NONE) {
+ switch (port) {
+ case TC9563_DSP1:
+ ep_reset_gpio = 0x2;
+ break;
+ case TC9563_DSP2:
+ ep_reset_gpio = 0x3;
+ break;
+ default:
+ return 0;
+ }
+ }
+
+ ep_reset_gpio_mask = BIT(ep_reset_gpio);
+
+ /* Set TC9563 GPIO as output */
+ ret = tc9563_pwrctrl_i2c_read(tc9563->client, TC9563_GPIO_CONFIG,
+ &val);
+ if (ret)
+ return ret;
+
+ val &= ~ep_reset_gpio_mask;
+
+ ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_GPIO_CONFIG,
+ val);
+ if (ret)
+ return ret;
+
+ /* Assert-deassert endpoint reset */
+ ret = tc9563_pwrctrl_i2c_read(tc9563->client, TC9563_RESET_GPIO,
+ &val);
+ if (ret)
+ return ret;
+
+ val = deassert ? (val | ep_reset_gpio_mask) : (val & ~ep_reset_gpio_mask);
+
+ return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_RESET_GPIO, val);
+}
+
static int tc9563_pwrctrl_set_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
enum tc9563_pwrctrl_ports port,
bool is_l1, u32 ns)
@@ -400,28 +489,17 @@ static int tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl *tc9563,
ARRAY_SIZE(nfts_seq));
}
-static int tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl *tc9563,
- bool deassert)
-{
- int ret, val;
-
- ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_GPIO_CONFIG,
- TC9563_GPIO_MASK);
- if (ret)
- return ret;
-
- val = deassert ? TC9563_GPIO_DEASSERT_BITS : 0;
-
- return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_RESET_GPIO, val);
-}
-
static int tc9563_pwrctrl_parse_device_dt(struct tc9563_pwrctrl *tc9563,
struct device_node *node,
enum tc9563_pwrctrl_ports port)
{
struct tc9563_pwrctrl_cfg *cfg = &tc9563->cfg[port];
+ struct of_phandle_args args;
int ret;
+ cfg->ep_reset_gpio = TC9563_GPIO_NONE;
+ cfg->ep_pwr_en_gpio = TC9563_GPIO_NONE;
+
/* Disable port if the status of the port is disabled. */
if (!of_device_is_available(node)) {
cfg->disable_port = true;
@@ -436,6 +514,18 @@ static int tc9563_pwrctrl_parse_device_dt(struct tc9563_pwrctrl *tc9563,
if (ret && ret != -EINVAL)
return ret;
+ ret = of_parse_phandle_with_fixed_args(node, "ep-pwr-en-gpios", 2, 0, &args);
+ if (ret && ret != -ENOENT)
+ return ret;
+ else if (!ret)
+ cfg->ep_pwr_en_gpio = args.args[0];
+
+ ret = of_parse_phandle_with_fixed_args(node, "reset-gpios", 2, 0, &args);
+ if (ret && ret != -ENOENT)
+ return ret;
+ else if (!ret)
+ cfg->ep_reset_gpio = args.args[0];
+
ret = of_property_read_u32(node, "toshiba,tx-amplitude-microvolt", &cfg->tx_amp);
if (ret && ret != -EINVAL)
return ret;
@@ -478,18 +568,28 @@ static int tc9563_pwrctrl_power_on(struct pci_pwrctrl *pwrctrl)
fsleep(TC9563_OSC_STAB_DELAY_US);
- ret = tc9563_pwrctrl_assert_deassert_reset(tc9563, false);
- if (ret)
- goto power_off;
-
for (i = 0; i < TC9563_MAX; i++) {
cfg = &tc9563->cfg[i];
+
ret = tc9563_pwrctrl_disable_port(tc9563, i);
if (ret) {
dev_err(dev, "Disabling port failed\n");
goto power_off;
}
+ ret = tc9563_pwrctrl_ep_assert_deassert_reset(tc9563, i, false,
+ cfg->ep_reset_gpio);
+ if (ret) {
+ dev_err(dev, "Assert EP reset failed\n");
+ goto power_off;
+ }
+
+ ret = tc9563_pwrctrl_ep_pwr_en(tc9563, i, true, cfg->ep_pwr_en_gpio);
+ if (ret) {
+ dev_err(dev, "Enabling EP Power failed\n");
+ goto power_off;
+ }
+
ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(tc9563, i, false, cfg->l0s_delay);
if (ret) {
dev_err(dev, "Setting L0s entry delay failed\n");
@@ -519,11 +619,17 @@ static int tc9563_pwrctrl_power_on(struct pci_pwrctrl *pwrctrl)
dev_err(dev, "Disabling DFE failed\n");
goto power_off;
}
+
+ ret = tc9563_pwrctrl_ep_assert_deassert_reset(tc9563, i, true,
+ cfg->ep_reset_gpio);
+ if (ret) {
+ dev_err(dev, "De-assert EP reset failed\n");
+ goto power_off;
+ }
+
}
- ret = tc9563_pwrctrl_assert_deassert_reset(tc9563, true);
- if (!ret)
- return 0;
+ return 0;
power_off:
tc9563_pwrctrl_power_off(&tc9563->pwrctrl);
@@ -601,7 +707,7 @@ static int tc9563_pwrctrl_probe(struct platform_device *pdev)
port++;
ret = tc9563_pwrctrl_parse_device_dt(tc9563,
child1, port);
- if (ret)
+ if (port + 1 >= TC9563_MAX || ret)
break;
}
}
--
2.43.0
--
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^ permalink raw reply related
* [PATCH 7/9] arm64: dts: qcom: shikra: Add PCIe PHY and controller nodes
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Shikra supports single PCIe instance with 5GT/s x1 lane.
Add PCIe controller and PHY node for this single instance.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 154 +++++++++++++++++++++++++++++++++++
1 file changed, 154 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index e67fe047a683..74d51ba5bde3 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -998,6 +998,160 @@ tsens0: thermal-sensor@4411000 {
#thermal-sensor-cells = <1>;
};
+ pcie: pcie@45e8000 {
+ device_type = "pci";
+ compatible = "qcom,shikra-pcie";
+ reg = <0x0 0x045e8000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf1d>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x1000>,
+ <0x0 0x60100000 0x0 0x100000>,
+ <0x0 0x045eb000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>,
+ <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x0000000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
+ <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>,
+ <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_memnoc_pcie",
+ "tile",
+ "qmip_pcie_ahb";
+
+ assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&system_noc MASTER_PCIE2_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &config_noc SLAVE_PCIE2_0 RPM_ACTIVE_TAG>;
+
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x800 0x1>,
+ <0x100 &apps_smmu 0x801 0x1>;
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_GDSC>;
+
+ max-link-speed = <2>;
+
+ operating-points-v2 = <&pcie_opp_table>;
+
+ status = "disabled";
+
+ pcie_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <250000 1>;
+ opp-level = <1>;
+ };
+
+ /* GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <500000 1>;
+ opp-level = <2>;
+ };
+ };
+
+ pcie_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ bus-range = <0x01 0x8>;
+
+ phys = <&pcie_phy>;
+ };
+ };
+
+ pcie_phy: phy@45ee000 {
+ compatible = "qcom,shikra-qmp-gen2x1-pcie-phy";
+ reg = <0x0 0x045ee000 0x0 0x1000>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+ <&gcc GCC_PCIE_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
--
2.43.0
--
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^ permalink raw reply related
* [PATCH 8/9] arm64: dts: qcom: shikra-evk: Add TC9563 PCIe switch node for PCIe
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Add a node for the TC9563 PCIe switch connected to PCIe. The switch
has three downstream ports.Two embedded Ethernet devices are present
on one of the downstream ports. All the ports present in the
node represent the downstream ports and embedded endpoints.
Power to the TC9563 is supplied through two LDO regulators, which
are on by default and are added as fixed regulators. TC9563 can be
configured through I2C.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 152 +++++++++++++++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
index 5411f22426b7..b6d24fe5fb61 100644
--- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
@@ -3,6 +3,136 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+/ {
+ aliases {
+ i2c3 = &i2c3;
+ };
+
+ vreg_0p9: regulator-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_0P9";
+
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_1p8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_1P8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&pcie {
+ wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
+
+ iommu-map = <0x0 &apps_smmu 0x0800 0x1>,
+ <0x100 &apps_smmu 0x0801 0x1>,
+ <0x208 &apps_smmu 0x0802 0x1>,
+ <0x210 &apps_smmu 0x0803 0x1>,
+ <0x218 &apps_smmu 0x0804 0x1>,
+ <0x300 &apps_smmu 0x0805 0x1>,
+ <0x400 &apps_smmu 0x0806 0x1>,
+ <0x500 &apps_smmu 0x0807 0x1>,
+ <0x501 &apps_smmu 0x0808 0x1>;
+
+ pinctrl-0 = <&pcie_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie_port0 {
+
+ tc9563: pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vreg_0p9>;
+ vdd18-supply = <&vreg_1p8>;
+ vdd09-supply = <&vreg_0p9>;
+ vddio1-supply = <&vreg_1p8>;
+ vddio2-supply = <&vreg_1p8>;
+ vddio18-supply = <&vreg_1p8>;
+
+ i2c-parent = <&i2c3 0x77>;
+
+ resx-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+
+ ep-pwr-en-gpios = <&tc9563 2 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tc9563 5 GPIO_ACTIVE_LOW>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+
+ ep-pwr-en-gpios = <&tc9563 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tc9563 3 GPIO_ACTIVE_LOW>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
&qupv3_0 {
firmware-name = "qcom/shikra/qupv3fw.elf";
@@ -10,11 +140,33 @@ &qupv3_0 {
};
&tlmm {
+ pcie_default_state: pcie-default-state {
+ clkreq-pins {
+ pins = "gpio117";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio119";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio88";
function = "gpio";
bias-pull-down;
};
+
+ tc9563_resx_n: tc9563-resx-state {
+ pins = "gpio118";
+ function = "gpio";
+ bias-disable;
+ };
};
&uart0 {
--
2.43.0
--
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^ permalink raw reply related
* [PATCH 9/9] arm64: dts: qcom: shikra-(cqm/cqs/iqs)-evk: Enable PCIe PHY node
From: Sushrut Shree Trivedi @ 2026-06-30 19:02 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Andersson,
Chaitanya Chundru, Bartosz Golaszewski, Konrad Dybcio
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-pci,
Sushrut Shree Trivedi
In-Reply-To: <20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com>
Enable the PCIe PHY for the single PCIe intance on the Shikra
CQS, CQM and the IQS platforms.
IQS platform uses a different powergrid than CQS/CQM which explain
the different PHY supplies for IQS variant.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 7 +++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 7 +++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 7 +++++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 683b5245923b..06ad32041546 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -60,6 +60,13 @@ vreg_pmu_ch1: ldo4 {
};
};
+&pcie_phy {
+ vdda-phy-supply = <&pm4125_l13>;
+ vdda-pll-supply = <&pm4125_l9>;
+
+ status = "okay";
+};
+
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index 26ff8007a819..e467c46a55c0 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -60,6 +60,13 @@ vreg_pmu_ch1: ldo4 {
};
};
+&pcie_phy {
+ vdda-phy-supply = <&pm4125_l13>;
+ vdda-pll-supply = <&pm4125_l9>;
+
+ status = "okay";
+};
+
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index fd691d53a0fa..a7628443cb36 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -68,6 +68,13 @@ vreg_pmu_ch1: ldo4 {
};
};
+&pcie_phy {
+ vdda-phy-supply = <&pm8150_l12>;
+ vdda-pll-supply = <&pm8150_l9>;
+
+ status = "okay";
+};
+
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
--
2.43.0
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [PATCH v5 3/5] phy: fsl-imx8mq-usb: add runtime PM support
From: Frank Li @ 2026-06-30 19:06 UTC (permalink / raw)
To: Xu Yang
Cc: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Jun Li, linux-phy, imx,
linux-arm-kernel, linux-kernel, Xu Yang
In-Reply-To: <20260630-imx8mp-usb-phy-improvement-v5-3-25d616403844@nxp.com>
On Tue, Jun 30, 2026 at 06:11:30PM +0800, Xu Yang wrote:
> From: Xu Yang <xu.yang_2@nxp.com>
>
> Add runtime PM to ensure the PHY is properly powered and clocked during
> register access, preventing potential system hangs.
>
> It guards register access in the following scenarios:
> - PHY operations: init() and power_on/off() callbacks are guarded by
> phy core
> - Type-C orientation switching when PHY/Controller are suspended which
> needs explicitly care
> - Future PHY control port register regmap debugfs access
>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
>
> ---
> Changes in v5:
> - use non-devm PM runtime callback to correctly enable/disable clocks
> when unbind the device
> Changes in v4:
> - replace guard() with PM_RUNTIME_ACQUIRE()
> Changes in v3:
> - new patch
> ---
> drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 64 +++++++++++++++++++++---------
> 1 file changed, 45 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
> index 3a5788c609e1..9d1dd0e7352e 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
> @@ -9,6 +9,7 @@
> #include <linux/of.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/regulator/consumer.h>
> #include <linux/usb/typec_mux.h>
>
> @@ -136,17 +137,15 @@ static int tca_blk_typec_switch_set(struct typec_switch_dev *sw,
> {
> struct imx8mq_usb_phy *imx_phy = typec_switch_get_drvdata(sw);
> struct tca_blk *tca = imx_phy->tca;
> - int ret;
>
> if (tca->orientation == orientation)
> return 0;
>
> - ret = clk_prepare_enable(imx_phy->clk);
> - if (ret)
> - return ret;
> + PM_RUNTIME_ACQUIRE(&imx_phy->phy->dev, pm);
> + if (PM_RUNTIME_ACQUIRE_ERR(&pm))
> + return -ENXIO;
>
> tca_blk_orientation_set(tca, orientation);
> - clk_disable_unprepare(imx_phy->clk);
>
> return 0;
> }
> @@ -620,16 +619,6 @@ static int imx8mq_phy_power_on(struct phy *phy)
> if (ret)
> return ret;
>
> - ret = clk_prepare_enable(imx_phy->clk);
> - if (ret)
> - return ret;
> -
> - ret = clk_prepare_enable(imx_phy->alt_clk);
> - if (ret) {
> - clk_disable_unprepare(imx_phy->clk);
> - return ret;
> - }
> -
> /* Disable rx term override */
> value = readl(imx_phy->base + PHY_CTRL6);
> value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL;
> @@ -648,8 +637,6 @@ static int imx8mq_phy_power_off(struct phy *phy)
> value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL;
> writel(value, imx_phy->base + PHY_CTRL6);
>
> - clk_disable_unprepare(imx_phy->alt_clk);
> - clk_disable_unprepare(imx_phy->clk);
> regulator_disable(imx_phy->vbus);
>
> return 0;
> @@ -693,13 +680,13 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, imx_phy);
>
> - imx_phy->clk = devm_clk_get(dev, "phy");
> + imx_phy->clk = devm_clk_get_enabled(dev, "phy");
> if (IS_ERR(imx_phy->clk)) {
> dev_err(dev, "failed to get imx8mq usb phy clock\n");
> return PTR_ERR(imx_phy->clk);
> }
>
> - imx_phy->alt_clk = devm_clk_get_optional(dev, "alt");
> + imx_phy->alt_clk = devm_clk_get_optional_enabled(dev, "alt");
> if (IS_ERR(imx_phy->alt_clk))
> return dev_err_probe(dev, PTR_ERR(imx_phy->alt_clk),
> "Failed to get alt clk\n");
> @@ -708,6 +695,9 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
> if (IS_ERR(imx_phy->base))
> return PTR_ERR(imx_phy->base);
>
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> +
devm_pm_runtime_enable();
runtime pm will be always on active status, why suspend it?
> phy_ops = of_device_get_match_data(dev);
> if (!phy_ops)
> return -EINVAL;
> @@ -737,15 +727,51 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
>
> static void imx8mq_usb_phy_remove(struct platform_device *pdev)
> {
> + struct device *dev = &pdev->dev;
> +
> + pm_runtime_get_sync(dev);
> + pm_runtime_disable(dev);
> + pm_runtime_put_noidle(dev);
> +}
> +
> +static int imx8mq_usb_phy_runtime_suspend(struct device *dev)
> +{
> + struct imx8mq_usb_phy *imx_phy = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(imx_phy->alt_clk);
> + clk_disable_unprepare(imx_phy->clk);
can you switch to use bulk clk api.
Frank
> +
> + return 0;
> +}
> +
> +static int imx8mq_usb_phy_runtime_resume(struct device *dev)
> +{
> + struct imx8mq_usb_phy *imx_phy = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = clk_prepare_enable(imx_phy->clk);
> + if (ret)
> + return ret;
>
> + ret = clk_prepare_enable(imx_phy->alt_clk);
> + if (ret) {
> + clk_disable_unprepare(imx_phy->clk);
> + return ret;
> + }
> +
> + return 0;
> }
>
> +static DEFINE_RUNTIME_DEV_PM_OPS(imx8mq_usb_phy_pm_ops, imx8mq_usb_phy_runtime_suspend,
> + imx8mq_usb_phy_runtime_resume, NULL);
> +
> static struct platform_driver imx8mq_usb_phy_driver = {
> .probe = imx8mq_usb_phy_probe,
> .remove = imx8mq_usb_phy_remove,
> .driver = {
> .name = "imx8mq-usb-phy",
> .of_match_table = imx8mq_usb_phy_of_match,
> + .pm = pm_ptr(&imx8mq_usb_phy_pm_ops),
> .suppress_bind_attrs = true,
> }
> };
>
> --
> 2.34.1
>
>
--
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