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From: Mario Limonciello <mario.limonciello@amd.com>
To: <perry.yuan@amd.com>, <gautham.shenoy@amd.com>
Cc: Linux PM <linux-pm@vger.kernel.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Huang Rui <ray.huang@amd.com>,
	Mario Limonciello <mario.limonciello@amd.com>
Subject: [PATCH v14 1/5] cpufreq: acpi: move MSR_K7_HWCR_CPB_DIS_BIT into msr-index.h
Date: Mon, 24 Jun 2024 16:33:56 -0500	[thread overview]
Message-ID: <20240624213400.67773-2-mario.limonciello@amd.com> (raw)
In-Reply-To: <20240624213400.67773-1-mario.limonciello@amd.com>

From: Perry Yuan <perry.yuan@amd.com>

There are some other drivers also need to use the
MSR_K7_HWCR_CPB_DIS_BIT for CPB control bit, so it makes sense to move
the definition to a common header file to allow other driver to use it.

No intentional functional impact.

Suggested-by: Gautham Ranjal Shenoy <gautham.shenoy@amd.com>
Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Acked-by: Huang Rui <ray.huang@amd.com>
Link: https://lore.kernel.org/r/78b6c75e6cffddce3e950dd543af6ae9f8eeccc3.1718988436.git.perry.yuan@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 arch/x86/include/asm/msr-index.h | 2 ++
 drivers/cpufreq/acpi-cpufreq.c   | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e022e6eb766c..384739d592af 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -781,6 +781,8 @@
 #define MSR_K7_HWCR_IRPERF_EN		BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
 #define MSR_K7_FID_VID_CTL		0xc0010041
 #define MSR_K7_FID_VID_STATUS		0xc0010042
+#define MSR_K7_HWCR_CPB_DIS_BIT		25
+#define MSR_K7_HWCR_CPB_DIS		BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT)
 
 /* K6 MSRs */
 #define MSR_K6_WHCR			0xc0000082
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 37f1cdf46d29..2fc82831bddd 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -50,8 +50,6 @@ enum {
 #define AMD_MSR_RANGE		(0x7)
 #define HYGON_MSR_RANGE		(0x7)
 
-#define MSR_K7_HWCR_CPB_DIS	(1ULL << 25)
-
 struct acpi_cpufreq_data {
 	unsigned int resume;
 	unsigned int cpu_feature;
-- 
2.43.0


  reply	other threads:[~2024-06-24 21:34 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-24 21:33 [PATCH v14 0/5] AMD Pstate Driver Core Performance Boost Mario Limonciello
2024-06-24 21:33 ` Mario Limonciello [this message]
2024-06-24 21:33 ` [PATCH v14 2/5] cpufreq: amd-pstate: initialize core precision boost state Mario Limonciello
2024-06-24 21:33 ` [PATCH v14 3/5] cpufreq: amd-pstate: Cap the CPPC.max_perf to nominal_perf if CPB is off Mario Limonciello
2024-06-24 21:33 ` [PATCH v14 4/5] Documentation: cpufreq: amd-pstate: update doc for Per CPU boost control method Mario Limonciello
2024-06-25 12:03   ` Gautham R.Shenoy
2024-06-24 21:34 ` [PATCH v14 5/5] cpufreq: Only disable boost during cpu online when using frequency tables Mario Limonciello
2024-06-25  6:30   ` Viresh Kumar
2024-06-25 12:31     ` Mario Limonciello
2024-06-26  3:11       ` Viresh Kumar
2024-06-26  3:14         ` Mario Limonciello
2024-06-26  3:17           ` Viresh Kumar
2024-06-26  3:20             ` Mario Limonciello
2024-06-26  3:25               ` Viresh Kumar
2024-06-26  3:27                 ` Viresh Kumar
2024-06-26  3:33                   ` Mario Limonciello
2024-06-26  3:44                     ` Viresh Kumar
2024-06-26  3:46                       ` Mario Limonciello
2024-06-25 11:55   ` Gautham R.Shenoy
2024-06-25 12:32     ` Mario Limonciello

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