* [PATCH v2 01/28] interconnect: qcom: sc8280xp: specify num_links for qnm_a1noc_cfg
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-08 12:59 ` Konrad Dybcio
2025-07-04 16:35 ` [PATCH v2 02/28] interconnect: qcom: sc8180x: specify num_nodes Dmitry Baryshkov
` (27 subsequent siblings)
28 siblings, 1 reply; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
The qnm_a1noc_cfg declaration didn't include .num_links definition, fix
it.
Fixes: f29dabda7917 ("interconnect: qcom: Add SC8280XP interconnect provider")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sc8280xp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c
index 0270f6c64481a92149cb19556acdc6e2fead39c9..c646cdf8a19bf6f5a581cd9491b104259259fff3 100644
--- a/drivers/interconnect/qcom/sc8280xp.c
+++ b/drivers/interconnect/qcom/sc8280xp.c
@@ -48,6 +48,7 @@ static struct qcom_icc_node qnm_a1noc_cfg = {
.id = SC8280XP_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
+ .num_links = 1,
.links = { SC8280XP_SLAVE_SERVICE_A1NOC },
};
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 02/28] interconnect: qcom: sc8180x: specify num_nodes
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 01/28] interconnect: qcom: sc8280xp: specify num_links for qnm_a1noc_cfg Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-08 13:00 ` Konrad Dybcio
2025-07-04 16:35 ` [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array Dmitry Baryshkov
` (26 subsequent siblings)
28 siblings, 1 reply; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Specify .num_nodes for several BCMs which missed this declaration.
Fixes: 04548d4e2798 ("interconnect: qcom: sc8180x: Reformat node and bcm definitions")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sc8180x.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c
index a741badaa966e0b1d0e0117f73f5d37c6ef9f19d..4dd1d2f2e8216271c15b91b726d4f0c46994ae78 100644
--- a/drivers/interconnect/qcom/sc8180x.c
+++ b/drivers/interconnect/qcom/sc8180x.c
@@ -1492,34 +1492,40 @@ static struct qcom_icc_bcm bcm_sh3 = {
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
+ .num_nodes = 1,
.nodes = { &slv_qns_gemnoc_sf }
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
+ .num_nodes = 1,
.nodes = { &slv_qxs_imem }
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = true,
+ .num_nodes = 1,
.nodes = { &slv_qns_gemnoc_gc }
};
static struct qcom_icc_bcm bcm_co2 = {
.name = "CO2",
+ .num_nodes = 1,
.nodes = { &mas_qnm_npu }
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = true,
+ .num_nodes = 2,
.nodes = { &slv_srvc_aggre1_noc,
&slv_qns_cnoc }
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
+ .num_nodes = 1,
.nodes = { &slv_qxs_pimem }
};
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 01/28] interconnect: qcom: sc8280xp: specify num_links for qnm_a1noc_cfg Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 02/28] interconnect: qcom: sc8180x: specify num_nodes Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-08 16:41 ` Konrad Dybcio
2025-07-18 13:38 ` Georgi Djakov
2025-07-04 16:35 ` [PATCH v2 04/28] interconnect: qcom: rpmh: make link_nodes " Dmitry Baryshkov
` (25 subsequent siblings)
28 siblings, 2 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Having the .num_nodes as a separate struct field can provoke errors as
it is easy to omit it or to put an incorrect value into that field. Turn
.nodes into a NULL-terminated array, removing a need for a separate
.num_nodes field.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/bcm-voter.c | 4 +-
drivers/interconnect/qcom/icc-rpmh.c | 2 +-
drivers/interconnect/qcom/icc-rpmh.h | 2 -
drivers/interconnect/qcom/qcs615.c | 78 ++++++++++-------------------
drivers/interconnect/qcom/qcs8300.c | 75 ++++++++++------------------
drivers/interconnect/qcom/qdu1000.c | 37 +++++---------
drivers/interconnect/qcom/sa8775p.c | 84 +++++++++++--------------------
drivers/interconnect/qcom/sar2130p.c | 48 ++++++------------
drivers/interconnect/qcom/sc7180.c | 75 +++++++++-------------------
drivers/interconnect/qcom/sc7280.c | 81 ++++++++++--------------------
drivers/interconnect/qcom/sc8180x.c | 69 +++++++++-----------------
drivers/interconnect/qcom/sc8280xp.c | 93 ++++++++++-------------------------
drivers/interconnect/qcom/sdm670.c | 74 +++++++++-------------------
drivers/interconnect/qcom/sdm845.c | 86 +++++++++++---------------------
drivers/interconnect/qcom/sdx55.c | 60 ++++++++--------------
drivers/interconnect/qcom/sdx65.c | 61 ++++++++---------------
drivers/interconnect/qcom/sdx75.c | 33 +++++--------
drivers/interconnect/qcom/sm6350.c | 78 ++++++++++-------------------
drivers/interconnect/qcom/sm7150.c | 80 +++++++++---------------------
drivers/interconnect/qcom/sm8150.c | 86 +++++++++++---------------------
drivers/interconnect/qcom/sm8250.c | 83 +++++++++++--------------------
drivers/interconnect/qcom/sm8350.c | 77 ++++++++++-------------------
drivers/interconnect/qcom/sm8450.c | 72 +++++++++------------------
drivers/interconnect/qcom/sm8550.c | 57 +++++++--------------
drivers/interconnect/qcom/sm8650.c | 51 +++++++------------
drivers/interconnect/qcom/sm8750.c | 57 +++++++--------------
drivers/interconnect/qcom/x1e80100.c | 57 +++++++--------------
27 files changed, 541 insertions(+), 1119 deletions(-)
diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
index a2d437a05a11fa7325f944865c81a3ac7dbb203e..4fa960630d28f338f484794d271a5b52f3e698d3 100644
--- a/drivers/interconnect/qcom/bcm-voter.c
+++ b/drivers/interconnect/qcom/bcm-voter.c
@@ -68,7 +68,7 @@ static void bcm_aggregate_mask(struct qcom_icc_bcm *bcm)
bcm->vote_x[bucket] = 0;
bcm->vote_y[bucket] = 0;
- for (i = 0; i < bcm->num_nodes; i++) {
+ for (i = 0; bcm->nodes[i]; i++) {
node = bcm->nodes[i];
/* If any vote in this bucket exists, keep the BCM enabled */
@@ -97,7 +97,7 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
u64 temp;
for (bucket = 0; bucket < QCOM_ICC_NUM_BUCKETS; bucket++) {
- for (i = 0; i < bcm->num_nodes; i++) {
+ for (i = 0; bcm->nodes[i]; i++) {
node = bcm->nodes[i];
temp = bcm_div(node->sum_avg[bucket] * bcm->aux_data.width,
node->buswidth * node->channels);
diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
index 001404e91041597eab7f251606873182e52e360c..7854e3a60d97eb3cdb0a5c1f1b77a96afc104009 100644
--- a/drivers/interconnect/qcom/icc-rpmh.c
+++ b/drivers/interconnect/qcom/icc-rpmh.c
@@ -184,7 +184,7 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
bcm->vote_scale = 1000;
/* Link Qnodes to their respective BCMs */
- for (i = 0; i < bcm->num_nodes; i++) {
+ for (i = 0; bcm->nodes[i]; i++) {
qn = bcm->nodes[i];
qn->bcms[qn->num_bcms] = bcm;
qn->num_bcms++;
diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
index bd8d730249b1c9e5b37afbee485b9500a8028c2e..0018aa74187edcac9a0492c737771d957a133cc0 100644
--- a/drivers/interconnect/qcom/icc-rpmh.h
+++ b/drivers/interconnect/qcom/icc-rpmh.h
@@ -126,7 +126,6 @@ struct qcom_icc_node {
* communicating with RPMh
* @list: used to link to other bcms when compiling lists for commit
* @ws_list: used to keep track of bcms that may transition between wake/sleep
- * @num_nodes: total number of @num_nodes
* @nodes: list of qcom_icc_nodes that this BCM encapsulates
*/
struct qcom_icc_bcm {
@@ -142,7 +141,6 @@ struct qcom_icc_bcm {
struct bcm_db aux_data;
struct list_head list;
struct list_head ws_list;
- size_t num_nodes;
struct qcom_icc_node *nodes[];
};
diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom/qcs615.c
index 7e59e91ce886d641599a780b0f0d56a9e64b7de4..acf452b5ed023b2e42b23f7455e57ab124bfa524 100644
--- a/drivers/interconnect/qcom/qcs615.c
+++ b/drivers/interconnect/qcom/qcs615.c
@@ -1069,20 +1069,17 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 37,
.nodes = { &qhm_spdm, &qnm_snoc,
&qhs_a1_noc_cfg, &qhs_aop,
&qhs_aoss, &qhs_camera_cfg,
@@ -1101,157 +1098,134 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_ufs_mem_cfg, &qhs_usb2,
&qhs_usb3, &qhs_venus_cfg,
&qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc,
- &srvc_cnoc },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
- .num_nodes = 8,
.nodes = { &qhm_qspi, &xm_sdc1,
&xm_sdc2, &qhs_ahb2phy_east,
&qhs_ahb2phy_west, &qhs_qspi,
- &qhs_sdc1, &qhs_sdc2 },
+ &qhs_sdc1, &qhs_sdc2, NULL },
};
static struct qcom_icc_bcm bcm_ip0 = {
.name = "IP0",
- .num_nodes = 1,
- .nodes = { &ipa_core_slave },
+ .nodes = { &ipa_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
- .num_nodes = 7,
.nodes = { &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp,
&qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0,
&qxm_camnoc_hf1, &qxm_mdp0,
- &qxm_rot },
+ &qxm_rot, NULL },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
- .num_nodes = 2,
- .nodes = { &qxm_camnoc_sf, &qns2_mem_noc },
+ .nodes = { &qxm_camnoc_sf, &qns2_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_mm3 = {
.name = "MM3",
- .num_nodes = 2,
- .nodes = { &qxm_venus0, &qxm_venus_arm9 },
+ .nodes = { &qxm_venus0, &qxm_venus_arm9, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 2,
- .nodes = { &qhm_qup0, &qhm_qup1 },
+ .nodes = { &qhm_qup0, &qhm_qup1, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
- .num_nodes = 1,
- .nodes = { &acm_apps },
+ .nodes = { &acm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
- .num_nodes = 1,
- .nodes = { &qns_gem_noc_snoc },
+ .nodes = { &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qns_memnoc_gc },
+ .nodes = { &qns_memnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 2,
- .nodes = { &srvc_aggre2_noc, &qns_cnoc },
+ .nodes = { &srvc_aggre2_noc, &qns_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
- .num_nodes = 2,
- .nodes = { &qnm_gemnoc_pcie, &xs_pcie },
+ .nodes = { &qnm_gemnoc_pcie, &xs_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn12 = {
.name = "SN12",
- .num_nodes = 2,
- .nodes = { &qxm_pimem, &xm_gic },
+ .nodes = { &qxm_pimem, &xm_gic, NULL },
};
static struct qcom_icc_bcm bcm_sn13 = {
.name = "SN13",
- .num_nodes = 1,
- .nodes = { &qnm_lpass_anoc },
+ .nodes = { &qnm_lpass_anoc, NULL },
};
static struct qcom_icc_bcm bcm_sn14 = {
.name = "SN14",
- .num_nodes = 1,
- .nodes = { &qns_pcie_snoc },
+ .nodes = { &qns_pcie_snoc, NULL },
};
static struct qcom_icc_bcm bcm_sn15 = {
.name = "SN15",
- .num_nodes = 1,
- .nodes = { &qnm_gemnoc },
+ .nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qcom/qcs8300.c
index e7a1b2fc69babe15b914da8d3a3769bfed110179..0987a7e9dddda298b1afca4ad95f6d8a909d57e6 100644
--- a/drivers/interconnect/qcom/qcs8300.c
+++ b/drivers/interconnect/qcom/qcs8300.c
@@ -1477,26 +1477,22 @@ static struct qcom_icc_node srvc_snoc = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 2,
- .nodes = { &qxm_crypto_0, &qxm_crypto_1 },
+ .nodes = { &qxm_crypto_0, &qxm_crypto_1, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 2,
- .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
- .num_nodes = 66,
.nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3,
&qhs_anoc_throttle_cfg, &qhs_aoss,
&qhs_apss, &qhs_boot_rom,
@@ -1529,147 +1525,126 @@ static struct qcom_icc_bcm bcm_cn1 = {
&qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
&qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
&qns_snoc_cfg, &qxs_boot_imem,
- &qxs_imem, &xs_sys_tcu_cfg },
+ &qxs_imem, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_cn2 = {
.name = "CN2",
- .num_nodes = 3,
.nodes = { &qhs_qup0, &qhs_qup1,
- &qhs_qup3 },
+ &qhs_qup3, NULL },
};
static struct qcom_icc_bcm bcm_cn3 = {
.name = "CN3",
- .num_nodes = 2,
- .nodes = { &xs_pcie_0, &xs_pcie_1 },
+ .nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_bcm bcm_gna0 = {
.name = "GNA0",
- .num_nodes = 1,
- .nodes = { &qxm_dsp0 },
+ .nodes = { &qxm_dsp0, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 4,
.nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
- &qnm_mdp0_1, &qns_mem_noc_hf },
+ &qnm_mdp0_1, &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
- .num_nodes = 6,
.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
&qnm_video0, &qnm_video_cvp,
- &qnm_video_v_cpu, &qns_mem_noc_sf },
+ &qnm_video_v_cpu, &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_nsa0 = {
.name = "NSA0",
- .num_nodes = 2,
- .nodes = { &qns_hcp, &qns_nsp_gemnoc },
+ .nodes = { &qns_hcp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_nsa1 = {
.name = "NSA1",
- .num_nodes = 1,
- .nodes = { &qxm_nsp },
+ .nodes = { &qxm_nsp, NULL },
};
static struct qcom_icc_bcm bcm_pci0 = {
.name = "PCI0",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.vote_scale = 1,
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.vote_scale = 1,
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup2 = {
.name = "QUP2",
.vote_scale = 1,
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qup3_core_slave },
+ .nodes = { &qup3_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
- .num_nodes = 1,
- .nodes = { &chm_apps },
+ .nodes = { &chm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 2,
- .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
+ .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 2,
- .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
+ .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
- .num_nodes = 2,
- .nodes = { &qns_sysnoc, &qnm_lpass_noc },
+ .nodes = { &qns_sysnoc, &qnm_lpass_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c
index a7392eb73d4a990ec65e9d55f3d0429d05270802..727482c0f7f8f15e32cf508a5f7300546e9d2daf 100644
--- a/drivers/interconnect/qcom/qdu1000.c
+++ b/drivers/interconnect/qcom/qdu1000.c
@@ -770,19 +770,16 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
- .num_nodes = 44,
.nodes = { &qhm_qpic, &qhm_qspi,
&qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave,
&qnm_gemnoc_pcie, &xm_sdc,
@@ -804,68 +801,56 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
&qns_modem, &qxs_imem,
&qxs_pimem, &xs_ethernet_ss,
- &xs_qdss_stm, &xs_sys_tcu_cfg
- },
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
- .num_nodes = 2,
- .nodes = { &qup0_core_slave, &qup1_core_slave },
+ .nodes = { &qup0_core_slave, &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
- .num_nodes = 11,
.nodes = { &alm_sys_tcu, &chm_apps,
&qnm_ecpri_dma, &qnm_fec_2_gemnoc,
&qnm_pcie, &qnm_snoc_gc,
&qnm_snoc_sf, &qxm_mdsp,
&qns_gem_noc_cnoc, &qns_modem_slave,
- &qns_pcie
- },
+ &qns_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
- .num_nodes = 6,
.nodes = { &qhm_gic, &qxm_pimem,
&xm_gic, &xm_qdss_etr0,
- &xm_qdss_etr1, &qns_gemnoc_gc
- },
+ &xm_qdss_etr1, &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 5,
.nodes = { &qnm_aggre_noc, &qxm_ecpri_gsi,
&xm_ecpri_dma, &qns_anoc_snoc_gsi,
- &qns_ecpri_gemnoc
- },
+ &qns_ecpri_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
- .num_nodes = 2,
- .nodes = { &qns_pcie_gemnoc, &xs_pcie },
+ .nodes = { &qns_pcie_gemnoc, &xs_pcie, NULL },
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
index 04b4abbf44875c767ac67c552b36a8c64a06b2c3..6bbe2fe03f791dd5d3606114d71d62057ddc52d2 100644
--- a/drivers/interconnect/qcom/sa8775p.c
+++ b/drivers/interconnect/qcom/sa8775p.c
@@ -1603,26 +1603,22 @@ static struct qcom_icc_node srvc_snoc = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = 0x8,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 2,
- .nodes = { &qxm_crypto_0, &qxm_crypto_1 },
+ .nodes = { &qxm_crypto_0, &qxm_crypto_1, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 2,
- .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
- .num_nodes = 76,
.nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
&qhs_ahb2phy2, &qhs_ahb2phy3,
&qhs_anoc_throttle_cfg, &qhs_aoss,
@@ -1660,164 +1656,140 @@ static struct qcom_icc_bcm bcm_cn1 = {
&qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
&qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
&qns_snoc_cfg, &qxs_boot_imem,
- &qxs_imem, &xs_sys_tcu_cfg },
+ &qxs_imem, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_cn2 = {
.name = "CN2",
- .num_nodes = 4,
.nodes = { &qhs_qup0, &qhs_qup1,
- &qhs_qup2, &qhs_qup3 },
+ &qhs_qup2, &qhs_qup3, NULL },
};
static struct qcom_icc_bcm bcm_cn3 = {
.name = "CN3",
- .num_nodes = 2,
- .nodes = { &xs_pcie_0, &xs_pcie_1 },
+ .nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_bcm bcm_gna0 = {
.name = "GNA0",
- .num_nodes = 1,
- .nodes = { &qxm_dsp0 },
+ .nodes = { &qxm_dsp0, NULL },
};
static struct qcom_icc_bcm bcm_gnb0 = {
.name = "GNB0",
- .num_nodes = 1,
- .nodes = { &qxm_dsp1 },
+ .nodes = { &qxm_dsp1, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 5,
.nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
&qnm_mdp0_1, &qnm_mdp1_0,
- &qns_mem_noc_hf },
+ &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
- .num_nodes = 7,
.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
&qnm_video0, &qnm_video1,
&qnm_video_cvp, &qnm_video_v_cpu,
- &qns_mem_noc_sf },
+ &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_nsa0 = {
.name = "NSA0",
- .num_nodes = 2,
- .nodes = { &qns_hcp, &qns_nsp_gemnoc },
+ .nodes = { &qns_hcp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_nsa1 = {
.name = "NSA1",
- .num_nodes = 1,
- .nodes = { &qxm_nsp },
+ .nodes = { &qxm_nsp, NULL },
};
static struct qcom_icc_bcm bcm_nsb0 = {
.name = "NSB0",
- .num_nodes = 2,
- .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp },
+ .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp, NULL },
};
static struct qcom_icc_bcm bcm_nsb1 = {
.name = "NSB1",
- .num_nodes = 1,
- .nodes = { &qxm_nspb },
+ .nodes = { &qxm_nspb, NULL },
};
static struct qcom_icc_bcm bcm_pci0 = {
.name = "PCI0",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup2 = {
.name = "QUP2",
.vote_scale = 1,
- .num_nodes = 2,
- .nodes = { &qup2_core_slave, &qup3_core_slave },
+ .nodes = { &qup2_core_slave, &qup3_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
- .num_nodes = 1,
- .nodes = { &chm_apps },
+ .nodes = { &chm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 2,
- .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
+ .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 2,
- .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
+ .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
- .num_nodes = 2,
- .nodes = { &qns_sysnoc, &qnm_lpass_noc },
+ .nodes = { &qns_sysnoc, &qnm_lpass_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qcom/sar2130p.c
index 9eac0ac7681273d6f4350f4431b81ce94dbada3f..cae3601b6789ff38e7bd88c60c4c8dd8d00e8850 100644
--- a/drivers/interconnect/qcom/sar2130p.c
+++ b/drivers/interconnect/qcom/sar2130p.c
@@ -1490,21 +1490,18 @@ static struct qcom_icc_node srvc_snoc = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.enable_mask = BIT(0),
.keepalive = true,
- .num_nodes = 48,
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
&xm_qdss_dap, &qhs_ahb2phy0,
&qhs_aoss, &qhs_camera_cfg,
@@ -1528,109 +1525,96 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qns_snoc_cfg, &qxs_imem,
&qxs_pimem, &srvc_cnoc,
&xs_pcie_0, &xs_pcie_1,
- &xs_qdss_stm, &xs_sys_tcu_cfg },
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.enable_mask = BIT(0),
- .num_nodes = 2,
- .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
+ .nodes = { &qxm_nsp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.enable_mask = BIT(0),
- .num_nodes = 11,
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
&qnm_camnoc_sf, &qnm_lsr,
&qnm_mdp, &qnm_mnoc_cfg,
&qnm_video, &qnm_video_cv_cpu,
&qnm_video_cvp, &qnm_video_v_cpu,
- &qns_mem_noc_sf },
+ &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.enable_mask = BIT(0),
- .num_nodes = 13,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
&chm_apps, &qnm_gpu,
&qnm_mnoc_hf, &qnm_mnoc_sf,
&qnm_nsp_gemnoc, &qnm_pcie,
&qnm_snoc_gc, &qnm_snoc_sf,
&qxm_wlan_q6, &qns_gem_noc_cnoc,
- &qns_pcie },
+ &qns_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.enable_mask = BIT(0),
- .num_nodes = 4,
.nodes = { &qhm_gic, &qxm_pimem,
- &xm_gic, &qns_gemnoc_gc },
+ &xm_gic, &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 1,
- .nodes = { &qnm_lpass_noc },
+ .nodes = { &qnm_lpass_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c
index af2be15438403e4b46fca464b84abd1e0ebebe76..6397d693918b41e35684b180fd6b8f5cb359386e 100644
--- a/drivers/interconnect/qcom/sc7180.c
+++ b/drivers/interconnect/qcom/sc7180.c
@@ -1240,42 +1240,36 @@ static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 48,
.nodes = { &qnm_snoc,
&xm_qdss_dap,
&qhs_a1_noc_cfg,
@@ -1323,14 +1317,12 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_venus_cfg,
&qhs_venus_throttle_cfg,
&qhs_vsense_ctrl_cfg,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = false,
- .num_nodes = 8,
.nodes = { &qxm_camnoc_hf0_uncomp,
&qxm_camnoc_hf1_uncomp,
&qxm_camnoc_sf_uncomp,
@@ -1338,70 +1330,60 @@ static struct qcom_icc_bcm bcm_mm1 = {
&qxm_mdp0,
&qxm_rot,
&qxm_venus0,
- &qxm_venus_arm9
- },
+ &qxm_venus_arm9, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_sys_tcu },
+ .nodes = { &acm_sys_tcu, NULL },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_sf },
+ .nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qup_core_master_1, &qup_core_master_2 },
+ .nodes = { &qup_core_master_1, &qup_core_master_2, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_cmpnoc },
+ .nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_apps0 },
+ .nodes = { &acm_apps0, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_cdsp_gemnoc },
+ .nodes = { &qns_cdsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
.keepalive = false,
- .num_nodes = 8,
.nodes = { &qhm_qspi,
&xm_sdc2,
&xm_emmc,
@@ -1409,64 +1391,55 @@ static struct qcom_icc_bcm bcm_cn1 = {
&qhs_emmc_cfg,
&qhs_pdm,
&qhs_qspi,
- &qhs_sdc2
- },
+ &qhs_sdc2, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qxm_pimem, &qns_gemnoc_gc },
+ .nodes = { &qxm_pimem, &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_co2 = {
.name = "CO2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_npu },
+ .nodes = { &qnm_npu, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_co3 = {
.name = "CO3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_npu_dsp },
+ .nodes = { &qxm_npu_dsp, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn12 = {
.name = "SN12",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_gemnoc },
+ .nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c
index 905403a3a930a2e1cd01f62e375e60c6b2d524f7..54e4ce9009bd498a840832e3f63dd9abfb86f837 100644
--- a/drivers/interconnect/qcom/sc7280.c
+++ b/drivers/interconnect/qcom/sc7280.c
@@ -1462,26 +1462,22 @@ static struct qcom_icc_node srvc_snoc = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 2,
- .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
- .num_nodes = 47,
.nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap,
&qhs_ahb2phy0, &qhs_ahb2phy1,
&qhs_camera_cfg, &qhs_clk_ctl,
@@ -1504,154 +1500,131 @@ static struct qcom_icc_bcm bcm_cn1 = {
&qns_mnoc_cfg, &qns_snoc_cfg,
&qnm_cnoc2_cnoc3, &qhs_aoss,
&qhs_apss, &qns_cnoc3_cnoc2,
- &qns_cnoc_a2noc, &qns_ddrss_cfg },
+ &qns_cnoc_a2noc, &qns_ddrss_cfg, NULL },
};
static struct qcom_icc_bcm bcm_cn2 = {
.name = "CN2",
- .num_nodes = 6,
.nodes = { &qhs_lpass_cfg, &qhs_pdm,
&qhs_qspi, &qhs_sdc1,
- &qhs_sdc2, &qhs_sdc4 },
+ &qhs_sdc2, &qhs_sdc4, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
- .num_nodes = 1,
- .nodes = { &qns_nsp_gemnoc },
+ .nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_co3 = {
.name = "CO3",
- .num_nodes = 1,
- .nodes = { &qxm_nsp },
+ .nodes = { &qxm_nsp, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
- .num_nodes = 2,
- .nodes = { &qxm_camnoc_hf, &qxm_mdp0 },
+ .nodes = { &qxm_camnoc_hf, &qxm_mdp0, NULL },
};
static struct qcom_icc_bcm bcm_mm4 = {
.name = "MM4",
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_sf },
+ .nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_mm5 = {
.name = "MM5",
- .num_nodes = 3,
.nodes = { &qnm_video0, &qxm_camnoc_icp,
- &qxm_camnoc_sf },
+ &qxm_camnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
- .num_nodes = 2,
- .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
+ .nodes = { &alm_gpu_tcu, &alm_sys_tcu, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
- .num_nodes = 1,
- .nodes = { &qnm_cmpnoc },
+ .nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
- .num_nodes = 1,
- .nodes = { &chm_apps },
+ .nodes = { &chm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
- .num_nodes = 1,
- .nodes = { &xm_pcie3_0 },
+ .nodes = { &xm_pcie3_0, NULL },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
- .num_nodes = 1,
- .nodes = { &xm_pcie3_1 },
+ .nodes = { &xm_pcie3_1, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn14 = {
.name = "SN14",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c
index 4dd1d2f2e8216271c15b91b726d4f0c46994ae78..0640ee55220d54fc977dc98f65644ecf7f50508f 100644
--- a/drivers/interconnect/qcom/sc8180x.c
+++ b/drivers/interconnect/qcom/sc8180x.c
@@ -1346,47 +1346,40 @@ static struct qcom_icc_node slv_qup_core_2 = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
- .num_nodes = 1,
- .nodes = { &slv_ebi }
+ .nodes = { &slv_ebi, NULL }
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &slv_ebi }
+ .nodes = { &slv_ebi, NULL }
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &slv_qns_llcc }
+ .nodes = { &slv_qns_llcc, NULL }
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
- .num_nodes = 1,
- .nodes = { &slv_qns_mem_noc_hf }
+ .nodes = { &slv_qns_mem_noc_hf, NULL }
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &slv_qns_cdsp_mem_noc }
+ .nodes = { &slv_qns_cdsp_mem_noc, NULL }
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &mas_qxm_crypto }
+ .nodes = { &mas_qxm_crypto, NULL }
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 57,
.nodes = { &mas_qnm_snoc,
&slv_qhs_a1_noc_cfg,
&slv_qhs_a2_noc_cfg,
@@ -1443,124 +1436,108 @@ static struct qcom_icc_bcm bcm_cn0 = {
&slv_qhs_usb3_2,
&slv_qhs_venus_cfg,
&slv_qhs_vsense_ctrl_cfg,
- &slv_srvc_cnoc }
+ &slv_srvc_cnoc, NULL }
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
- .num_nodes = 7,
.nodes = { &mas_qxm_camnoc_hf0_uncomp,
&mas_qxm_camnoc_hf1_uncomp,
&mas_qxm_camnoc_sf_uncomp,
&mas_qxm_camnoc_hf0,
&mas_qxm_camnoc_hf1,
&mas_qxm_mdp0,
- &mas_qxm_mdp1 }
+ &mas_qxm_mdp1, NULL }
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
- .num_nodes = 3,
.nodes = { &mas_qup_core_0,
&mas_qup_core_1,
- &mas_qup_core_2 }
+ &mas_qup_core_2, NULL }
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
- .num_nodes = 1,
- .nodes = { &slv_qns_gem_noc_snoc }
+ .nodes = { &slv_qns_gem_noc_snoc, NULL }
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
- .num_nodes = 6,
.nodes = { &mas_qxm_camnoc_sf,
&mas_qxm_rot,
&mas_qxm_venus0,
&mas_qxm_venus1,
&mas_qxm_venus_arm9,
- &slv_qns2_mem_noc }
+ &slv_qns2_mem_noc, NULL }
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &mas_acm_apps }
+ .nodes = { &mas_acm_apps, NULL }
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
- .num_nodes = 1,
- .nodes = { &slv_qns_gemnoc_sf }
+ .nodes = { &slv_qns_gemnoc_sf, NULL }
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
- .num_nodes = 1,
- .nodes = { &slv_qxs_imem }
+ .nodes = { &slv_qxs_imem, NULL }
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &slv_qns_gemnoc_gc }
+ .nodes = { &slv_qns_gemnoc_gc, NULL }
};
static struct qcom_icc_bcm bcm_co2 = {
.name = "CO2",
- .num_nodes = 1,
- .nodes = { &mas_qnm_npu }
+ .nodes = { &mas_qnm_npu, NULL }
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = true,
- .num_nodes = 2,
.nodes = { &slv_srvc_aggre1_noc,
- &slv_qns_cnoc }
+ &slv_qns_cnoc, NULL }
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 1,
- .nodes = { &slv_qxs_pimem }
+ .nodes = { &slv_qxs_pimem, NULL }
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
- .num_nodes = 4,
.nodes = { &slv_xs_pcie_0,
&slv_xs_pcie_1,
&slv_xs_pcie_2,
- &slv_xs_pcie_3 }
+ &slv_xs_pcie_3, NULL }
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
- .num_nodes = 1,
- .nodes = { &mas_qnm_aggre1_noc }
+ .nodes = { &mas_qnm_aggre1_noc, NULL }
};
static struct qcom_icc_bcm bcm_sn11 = {
.name = "SN11",
- .num_nodes = 1,
- .nodes = { &mas_qnm_aggre2_noc }
+ .nodes = { &mas_qnm_aggre2_noc, NULL }
};
static struct qcom_icc_bcm bcm_sn14 = {
.name = "SN14",
- .num_nodes = 1,
- .nodes = { &slv_qns_pcie_mem_noc }
+ .nodes = { &slv_qns_pcie_mem_noc, NULL }
};
static struct qcom_icc_bcm bcm_sn15 = {
.name = "SN15",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &mas_qnm_gemnoc }
+ .nodes = { &mas_qnm_gemnoc, NULL }
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c
index c646cdf8a19bf6f5a581cd9491b104259259fff3..1a9b97aa9e1c5bec0cda12cb4c5a8b14af970358 100644
--- a/drivers/interconnect/qcom/sc8280xp.c
+++ b/drivers/interconnect/qcom/sc8280xp.c
@@ -1714,20 +1714,17 @@ static struct qcom_icc_node srvc_snoc = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 9,
.nodes = { &qnm_gemnoc_cnoc,
&qnm_gemnoc_pcie,
&xs_pcie_0,
@@ -1736,13 +1733,11 @@ static struct qcom_icc_bcm bcm_cn0 = {
&xs_pcie_2b,
&xs_pcie_3a,
&xs_pcie_3b,
- &xs_pcie_4
- },
+ &xs_pcie_4, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
- .num_nodes = 67,
.nodes = { &qhs_ahb2phy0,
&qhs_ahb2phy1,
&qhs_ahb2phy2,
@@ -1809,51 +1804,42 @@ static struct qcom_icc_bcm bcm_cn1 = {
&qns_mnoc_cfg,
&qns_snoc_cfg,
&qns_snoc_sf_bridge_cfg,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_cn2 = {
.name = "CN2",
- .num_nodes = 4,
.nodes = { &qhs_qspi,
&qhs_qup0,
&qhs_qup1,
- &qhs_qup2
- },
+ &qhs_qup2, NULL },
};
static struct qcom_icc_bcm bcm_cn3 = {
.name = "CN3",
- .num_nodes = 3,
.nodes = { &qxs_imem,
&xs_smss,
- &xs_sys_tcu_cfg
- },
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 5,
.nodes = { &qnm_camnoc_hf,
&qnm_mdp0_0,
&qnm_mdp0_1,
&qnm_mdp1_0,
- &qns_mem_noc_hf
- },
+ &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
- .num_nodes = 8,
.nodes = { &qnm_rot_0,
&qnm_rot_1,
&qnm_video0,
@@ -1861,133 +1847,108 @@ static struct qcom_icc_bcm bcm_mm1 = {
&qnm_video_cvp,
&qxm_camnoc_icp,
&qxm_camnoc_sf,
- &qns_mem_noc_sf
- },
+ &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_nsa0 = {
.name = "NSA0",
- .num_nodes = 2,
.nodes = { &qns_nsp_gemnoc,
- &qxs_nsp_xfr
- },
+ &qxs_nsp_xfr, NULL },
};
static struct qcom_icc_bcm bcm_nsa1 = {
.name = "NSA1",
- .num_nodes = 1,
- .nodes = { &qxm_nsp },
+ .nodes = { &qxm_nsp, NULL },
};
static struct qcom_icc_bcm bcm_nsb0 = {
.name = "NSB0",
- .num_nodes = 2,
.nodes = { &qns_nspb_gemnoc,
- &qxs_nspb_xfr
- },
+ &qxs_nspb_xfr, NULL },
};
static struct qcom_icc_bcm bcm_nsb1 = {
.name = "NSB1",
- .num_nodes = 1,
- .nodes = { &qxm_nspb },
+ .nodes = { &qxm_nspb, NULL },
};
static struct qcom_icc_bcm bcm_pci0 = {
.name = "PCI0",
- .num_nodes = 1,
- .nodes = { &qns_pcie_gem_noc },
+ .nodes = { &qns_pcie_gem_noc, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup2 = {
.name = "QUP2",
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup2_core_slave },
+ .nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
- .num_nodes = 1,
- .nodes = { &chm_apps },
+ .nodes = { &chm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 2,
.nodes = { &qns_a1noc_snoc,
- &qnm_aggre1_noc
- },
+ &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 2,
.nodes = { &qns_a2noc_snoc,
- &qnm_aggre2_noc
- },
+ &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
- .num_nodes = 2,
.nodes = { &qns_aggre_usb_snoc,
- &qnm_aggre_usb_noc
- },
+ &qnm_aggre_usb_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
- .num_nodes = 2,
.nodes = { &qns_sysnoc,
- &qnm_lpass_noc
- },
+ &qnm_lpass_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c
index 907e1ff4ff81796ec9459ccc72a3f8c5d110ec57..7a61e2472319b0f6a2a3dee5df014640345e3e79 100644
--- a/drivers/interconnect/qcom/sdm670.c
+++ b/drivers/interconnect/qcom/sdm670.c
@@ -1049,105 +1049,90 @@ static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_apps_io },
+ .nodes = { &qns_apps_io, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = true,
- .num_nodes = 7,
.nodes = { &qxm_camnoc_hf0_uncomp,
&qxm_camnoc_hf1_uncomp,
&qxm_camnoc_sf_uncomp,
&qxm_camnoc_hf0,
&qxm_camnoc_hf1,
&qxm_mdp0,
- &qxm_mdp1
- },
+ &qxm_mdp1, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_memnoc_snoc },
+ .nodes = { &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns2_mem_noc },
+ .nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_tcu },
+ .nodes = { &acm_tcu, NULL },
};
static struct qcom_icc_bcm bcm_mm3 = {
.name = "MM3",
.keepalive = false,
- .num_nodes = 5,
- .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
+ .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9, NULL },
};
static struct qcom_icc_bcm bcm_sh5 = {
.name = "SH5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_apps },
+ .nodes = { &qnm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_memnoc_sf },
+ .nodes = { &qns_memnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 41,
.nodes = { &qhm_spdm,
&qnm_snoc,
&qhs_a1_noc_cfg,
@@ -1188,78 +1173,67 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_venus_cfg,
&qhs_vsense_ctrl_cfg,
&qns_cnoc_a2noc,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qhm_qup1, &qhm_qup2 },
+ .nodes = { &qhm_qup1, &qhm_qup2, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_memnoc_gc },
+ .nodes = { &qns_memnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_cnoc },
+ .nodes = { &qns_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qxm_pimem, &qxs_pimem },
+ .nodes = { &qxm_pimem, &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qnm_aggre1_noc, &srvc_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qnm_aggre2_noc, &srvc_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn11 = {
.name = "SN11",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qnm_gladiator_sodv, &xm_gic },
+ .nodes = { &qnm_gladiator_sodv, &xm_gic, NULL },
};
static struct qcom_icc_bcm bcm_sn13 = {
.name = "SN13",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_memnoc },
+ .nodes = { &qnm_memnoc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c
index 855802be93fea1d999bc8a885f36c3c318e1d86d..9d5bd2c9943b620b41d70e9c56f8ddc32c75d5a7 100644
--- a/drivers/interconnect/qcom/sdm845.c
+++ b/drivers/interconnect/qcom/sdm845.c
@@ -1267,105 +1267,90 @@ static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_apps_io },
+ .nodes = { &qns_apps_io, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = true,
- .num_nodes = 7,
.nodes = { &qxm_camnoc_hf0_uncomp,
&qxm_camnoc_hf1_uncomp,
&qxm_camnoc_sf_uncomp,
&qxm_camnoc_hf0,
&qxm_camnoc_hf1,
&qxm_mdp0,
- &qxm_mdp1
- },
+ &qxm_mdp1, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_memnoc_snoc },
+ .nodes = { &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns2_mem_noc },
+ .nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_tcu },
+ .nodes = { &acm_tcu, NULL },
};
static struct qcom_icc_bcm bcm_mm3 = {
.name = "MM3",
.keepalive = false,
- .num_nodes = 5,
- .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
+ .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9, NULL },
};
static struct qcom_icc_bcm bcm_sh5 = {
.name = "SH5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_apps },
+ .nodes = { &qnm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_memnoc_sf },
+ .nodes = { &qns_memnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = false,
- .num_nodes = 47,
.nodes = { &qhm_spdm,
&qhm_tic,
&qnm_snoc,
@@ -1412,106 +1397,91 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_venus_cfg,
&qhs_vsense_ctrl_cfg,
&qns_cnoc_a2noc,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qhm_qup1, &qhm_qup2 },
+ .nodes = { &qhm_qup1, &qhm_qup2, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_memnoc_gc },
+ .nodes = { &qns_memnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_cnoc },
+ .nodes = { &qns_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_pimem },
+ .nodes = { &qxm_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.keepalive = false,
- .num_nodes = 3,
- .nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg },
+ .nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_pcie },
+ .nodes = { &qxs_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_pcie_gen3 },
+ .nodes = { &qxs_pcie_gen3, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc },
+ .nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn11 = {
.name = "SN11",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc },
+ .nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn12 = {
.name = "SN12",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qnm_gladiator_sodv, &xm_gic },
+ .nodes = { &qnm_gladiator_sodv, &xm_gic, NULL },
};
static struct qcom_icc_bcm bcm_sn14 = {
.name = "SN14",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_pcie_anoc },
+ .nodes = { &qnm_pcie_anoc, NULL },
};
static struct qcom_icc_bcm bcm_sn15 = {
.name = "SN15",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_memnoc },
+ .nodes = { &qnm_memnoc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c
index 4117db046fa00c634a43d9287711589315f60210..af273e39eef3e90519635d1c310dc108a9f8b708 100644
--- a/drivers/interconnect/qcom/sdx55.c
+++ b/drivers/interconnect/qcom/sdx55.c
@@ -646,141 +646,121 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_pn0 = {
.name = "PN0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qhm_snoc_cfg },
+ .nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xm_apps_rdwr },
+ .nodes = { &xm_apps_rdwr, NULL },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qns_memnoc_snoc, &qns_sys_pcie },
+ .nodes = { &qns_memnoc_snoc, &qns_sys_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_snoc_memnoc },
+ .nodes = { &qns_snoc_memnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_pn1 = {
.name = "PN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xm_sdc1 },
+ .nodes = { &xm_sdc1, NULL },
};
static struct qcom_icc_bcm bcm_pn2 = {
.name = "PN2",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qhm_audio, &qhm_spmi_fetcher1 },
+ .nodes = { &qhm_audio, &qhm_spmi_fetcher1, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_pn3 = {
.name = "PN3",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qhm_blsp1, &qhm_qpic },
+ .nodes = { &qhm_blsp1, &qhm_qpic, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_sys_tcu_cfg },
+ .nodes = { &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_pn5 = {
.name = "PN5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_pcie },
+ .nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
- .num_nodes = 5,
- .nodes = { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc },
+ .nodes = { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qhm_qdss_bam, &xm_qdss_etr },
+ .nodes = { &qhm_qdss_bam, &xm_qdss_etr, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_memnoc },
+ .nodes = { &qnm_memnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_memnoc_pcie },
+ .nodes = { &qnm_memnoc_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn11 = {
.name = "SN11",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qnm_ipa, &xm_ipa2pcie_slv },
+ .nodes = { &qnm_ipa, &xm_ipa2pcie_slv, NULL },
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c
index d3a6c6c148e5dedc95dbac3ad9b20538ce56a16d..cf24f94eef6e0e1a7c1e957e07a316803942d174 100644
--- a/drivers/interconnect/qcom/sdx65.c
+++ b/drivers/interconnect/qcom/sdx65.c
@@ -607,21 +607,18 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_pn0 = {
.name = "PN0",
.keepalive = true,
- .num_nodes = 26,
.nodes = { &qhm_snoc_cfg,
&qhs_aoss,
&qhs_apss,
@@ -647,127 +644,109 @@ static struct qcom_icc_bcm bcm_pn0 = {
&qhs_tlmm,
&qhs_usb3,
&qhs_usb3_phy,
- &srvc_snoc
- },
+ &srvc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_pn1 = {
.name = "PN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xm_sdc1 },
+ .nodes = { &xm_sdc1, NULL },
};
static struct qcom_icc_bcm bcm_pn2 = {
.name = "PN2",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qhm_audio, &qhm_spmi_fetcher1 },
+ .nodes = { &qhm_audio, &qhm_spmi_fetcher1, NULL },
};
static struct qcom_icc_bcm bcm_pn3 = {
.name = "PN3",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qhm_blsp1, &qhm_qpic },
+ .nodes = { &qhm_blsp1, &qhm_qpic, NULL },
};
static struct qcom_icc_bcm bcm_pn4 = {
.name = "PN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_memnoc_snoc },
+ .nodes = { &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xm_apps_rdwr },
+ .nodes = { &xm_apps_rdwr, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_snoc_memnoc },
+ .nodes = { &qns_snoc_memnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_sys_tcu_cfg },
+ .nodes = { &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_pcie },
+ .nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qhm_qdss_bam, &xm_qdss_etr },
+ .nodes = { &qhm_qdss_bam, &xm_qdss_etr, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
- .num_nodes = 4,
- .nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc },
+ .nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_memnoc },
+ .nodes = { &qnm_memnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_memnoc_pcie },
+ .nodes = { &qnm_memnoc_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qnm_ipa, &xm_ipa2pcie_slv },
+ .nodes = { &qnm_ipa, &xm_ipa2pcie_slv, NULL },
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c
index 7ef1f17f3292e15959cb06e3d8d8c5f3c6ecd060..ea799f7ec0c5a7e87bf6243471120c917d100ff6 100644
--- a/drivers/interconnect/qcom/sdx75.c
+++ b/drivers/interconnect/qcom/sdx75.c
@@ -794,14 +794,12 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 39,
.nodes = { &qhm_pcie_rscc, &qnm_gemnoc_cnoc,
&ps_eth0_cfg, &ps_eth1_cfg,
&qhs_audio, &qhs_clk_ctl,
@@ -821,57 +819,50 @@ static struct qcom_icc_bcm bcm_cn0 = {
&srvc_pcie_system_noc, &srvc_system_noc,
&xs_pcie_0, &xs_pcie_1,
&xs_pcie_2, &xs_qdss_stm,
- &xs_sys_tcu_cfg },
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_qp0 = {
.name = "QP0",
- .num_nodes = 1,
- .nodes = { &qpic_core_slave },
+ .nodes = { &qpic_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
- .num_nodes = 10,
.nodes = { &alm_sys_tcu, &chm_apps,
&qnm_gemnoc_cfg, &qnm_mdsp,
&qnm_snoc_sf, &xm_gic,
&xm_ipa2pcie, &qns_gemnoc_cnoc,
- &qns_pcie, &srvc_gemnoc },
+ &qns_pcie, &srvc_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
- .num_nodes = 21,
.nodes = { &xm_pcie3_0, &xm_pcie3_1,
&xm_pcie3_2, &qhm_audio,
&qhm_gic, &qhm_qdss_bam,
@@ -882,19 +873,17 @@ static struct qcom_icc_bcm bcm_sn1 = {
&xm_emac_0, &xm_emac_1,
&xm_qdss_etr0, &xm_qdss_etr1,
&xm_sdc1, &xm_sdc4,
- &xm_usb3 },
+ &xm_usb3, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 2,
- .nodes = { &qnm_aggre_noc, &qns_a1noc },
+ .nodes = { &qnm_aggre_noc, &qns_a1noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 2,
- .nodes = { &qnm_pcie, &qns_pcie_gemnoc },
+ .nodes = { &qnm_pcie, &qns_pcie_gemnoc, NULL },
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c
index f41d7e19ba269cba7cc07b0136a6d1fcccd8af4d..016f75ef970648b00a87483a6dee04dd8208726f 100644
--- a/drivers/interconnect/qcom/sm6350.c
+++ b/drivers/interconnect/qcom/sm6350.c
@@ -1166,21 +1166,18 @@ static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 41,
.nodes = { &qnm_snoc,
&xm_qdss_dap,
&qhs_a1_noc_cfg,
@@ -1221,173 +1218,148 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_venus_cfg,
&qhs_venus_throttle_cfg,
&qhs_vsense_ctrl_cfg,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
.keepalive = false,
- .num_nodes = 6,
.nodes = { &xm_emmc,
&xm_sdc2,
&qhs_ahb2phy2,
&qhs_emmc_cfg,
&qhs_pdm,
- &qhs_sdc2
- },
+ &qhs_sdc2, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_cdsp_gemnoc },
+ .nodes = { &qns_cdsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_co2 = {
.name = "CO2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_npu },
+ .nodes = { &qnm_npu, NULL },
};
static struct qcom_icc_bcm bcm_co3 = {
.name = "CO3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_npu_dsp },
+ .nodes = { &qxm_npu_dsp, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = true,
- .num_nodes = 5,
.nodes = { &qxm_camnoc_hf0_uncomp,
&qxm_camnoc_icp_uncomp,
&qxm_camnoc_sf_uncomp,
&qxm_camnoc_hf,
- &qxm_mdp0
- },
+ &qxm_mdp0, NULL },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_sf },
+ .nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_mm3 = {
.name = "MM3",
.keepalive = false,
- .num_nodes = 4,
- .nodes = { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf },
+ .nodes = { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = false,
- .num_nodes = 4,
- .nodes = { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave },
+ .nodes = { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_sys_tcu },
+ .nodes = { &acm_sys_tcu, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_cmpnoc },
+ .nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_apps },
+ .nodes = { &acm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_gemnoc },
+ .nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom/sm7150.c
index c8c77407cd508dfede2821b7d52bf9da54283bad..3892e49e614ba189d29d9bb6f278835283bfaac0 100644
--- a/drivers/interconnect/qcom/sm7150.c
+++ b/drivers/interconnect/qcom/sm7150.c
@@ -1185,35 +1185,30 @@ static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = true,
- .num_nodes = 8,
.nodes = { &qxm_camnoc_hf0_uncomp,
&qxm_camnoc_rt_uncomp,
&qxm_camnoc_sf_uncomp,
@@ -1221,84 +1216,71 @@ static struct qcom_icc_bcm bcm_mm1 = {
&qxm_camnoc_hf,
&qxm_camnoc_rt,
&qxm_mdp0,
- &qxm_mdp1
- },
+ &qxm_mdp1, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_gem_noc_snoc },
+ .nodes = { &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_sys_tcu },
+ .nodes = { &acm_sys_tcu, NULL },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
.keepalive = false,
- .num_nodes = 2,
.nodes = { &qxm_camnoc_nrt,
- &qns2_mem_noc
- },
+ &qns2_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_mm3 = {
.name = "MM3",
.keepalive = false,
- .num_nodes = 5,
.nodes = { &qxm_camnoc_sf,
&qxm_rot,
&qxm_venus0,
&qxm_venus1,
- &qxm_venus_arm9
- },
+ &qxm_venus_arm9, NULL },
};
static struct qcom_icc_bcm bcm_sh5 = {
.name = "SH5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_apps },
+ .nodes = { &acm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sh8 = {
.name = "SH8",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_cdsp_gemnoc },
+ .nodes = { &qns_cdsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_sh10 = {
.name = "SH10",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_npu },
+ .nodes = { &qnm_npu, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 54,
.nodes = { &qhm_tsif,
&xm_emmc,
&xm_sdc2,
@@ -1352,79 +1334,65 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_venus_throttle_cfg,
&qhs_vsense_ctrl_cfg,
&qns_cnoc_a2noc,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = false,
- .num_nodes = 2,
.nodes = { &qhm_qup_center,
- &qhm_qup_north
- },
+ &qhm_qup_north, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
- .num_nodes = 2,
.nodes = { &qnm_aggre1_noc,
- &qns_a1noc_snoc
- },
+ &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_sn11 = {
.name = "SN11",
.keepalive = false,
- .num_nodes = 2,
.nodes = { &qnm_aggre2_noc,
- &qns_a2noc_snoc
- },
+ &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_sn12 = {
.name = "SN12",
.keepalive = false,
- .num_nodes = 2,
.nodes = { &qxm_pimem,
- &xm_gic
- },
+ &xm_gic, NULL },
};
static struct qcom_icc_bcm bcm_sn14 = {
.name = "SN14",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_pcie_gemnoc },
+ .nodes = { &qns_pcie_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn15 = {
.name = "SN15",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_gemnoc },
+ .nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c
index edfe824cad3533cfc6263c2031838f96e1986fa5..c5dc5b55ae564683dd169de621fffcd7449a70f5 100644
--- a/drivers/interconnect/qcom/sm8150.c
+++ b/drivers/interconnect/qcom/sm8150.c
@@ -1284,126 +1284,108 @@ static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = false,
- .num_nodes = 7,
.nodes = { &qxm_camnoc_hf0_uncomp,
&qxm_camnoc_hf1_uncomp,
&qxm_camnoc_sf_uncomp,
&qxm_camnoc_hf0,
&qxm_camnoc_hf1,
&qxm_mdp0,
- &qxm_mdp1
- },
+ &qxm_mdp1, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_gem_noc_snoc },
+ .nodes = { &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qxm_camnoc_sf, &qns2_mem_noc },
+ .nodes = { &qxm_camnoc_sf, &qns2_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &acm_gpu_tcu, &acm_sys_tcu },
+ .nodes = { &acm_gpu_tcu, &acm_sys_tcu, NULL },
};
static struct qcom_icc_bcm bcm_mm3 = {
.name = "MM3",
.keepalive = false,
- .num_nodes = 4,
- .nodes = { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
+ .nodes = { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9, NULL },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_cmpnoc },
+ .nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_bcm bcm_sh5 = {
.name = "SH5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &acm_apps },
+ .nodes = { &acm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_cdsp_mem_noc },
+ .nodes = { &qns_cdsp_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_co1 = {
.name = "CO1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_npu },
+ .nodes = { &qnm_npu, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 53,
.nodes = { &qhm_spdm,
&qnm_snoc,
&qhs_a1_noc_cfg,
@@ -1456,85 +1438,73 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_venus_cfg,
&qhs_vsense_ctrl_cfg,
&qns_cnoc_a2noc,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = false,
- .num_nodes = 3,
- .nodes = { &qhm_qup0, &qhm_qup1, &qhm_qup2 },
+ .nodes = { &qhm_qup0, &qhm_qup1, &qhm_qup2, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 3,
- .nodes = { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc },
+ .nodes = { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &xs_pcie_0, &xs_pcie_1 },
+ .nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn11 = {
.name = "SN11",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn12 = {
.name = "SN12",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qxm_pimem, &xm_gic },
+ .nodes = { &qxm_pimem, &xm_gic, NULL },
};
static struct qcom_icc_bcm bcm_sn14 = {
.name = "SN14",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn15 = {
.name = "SN15",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_gemnoc },
+ .nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c
index cc1b14c1352910fd450c334fa90f2a0b390bb9bc..cd7a37ecb9b55e40e9a90a9b649ae8cced1d1bb3 100644
--- a/drivers/interconnect/qcom/sm8250.c
+++ b/drivers/interconnect/qcom/sm8250.c
@@ -1399,105 +1399,91 @@ static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = false,
- .num_nodes = 3,
- .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
+ .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
+ .nodes = { &alm_gpu_tcu, &alm_sys_tcu, NULL },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_sf },
+ .nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = false,
- .num_nodes = 3,
- .nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master },
+ .nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_cmpnoc },
+ .nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_bcm bcm_mm3 = {
.name = "MM3",
.keepalive = false,
- .num_nodes = 5,
- .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp },
+ .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1,
+ &qnm_video_cvp, NULL },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &chm_apps },
+ .nodes = { &chm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_cdsp_mem_noc },
+ .nodes = { &qns_cdsp_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 52,
.nodes = { &qnm_snoc,
&xm_qdss_dap,
&qhs_a1_noc_cfg,
@@ -1549,92 +1535,79 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_venus_cfg,
&qhs_vsense_ctrl_cfg,
&qns_cnoc_a2noc,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_imem },
+ .nodes = { &qxs_imem, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_co2 = {
.name = "CO2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_npu },
+ .nodes = { &qnm_npu, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_pcie_modem },
+ .nodes = { &xs_pcie_modem, NULL },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &xs_pcie_0, &xs_pcie_1 },
+ .nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_gemnoc_pcie },
+ .nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn11 = {
.name = "SN11",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_gemnoc },
+ .nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_sn12 = {
.name = "SN12",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c
index 38105ead4f29548ab32c60aeba224fbf3909667c..3fa17b5786b726a8a61c347f9e2bb61dc0709546 100644
--- a/drivers/interconnect/qcom/sm8350.c
+++ b/drivers/interconnect/qcom/sm8350.c
@@ -1270,28 +1270,24 @@ static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 2,
- .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
.keepalive = false,
- .num_nodes = 47,
.nodes = { &xm_qdss_dap,
&qhs_ahb2phy0,
&qhs_ahb2phy1,
@@ -1338,161 +1334,138 @@ static struct qcom_icc_bcm bcm_cn1 = {
&qns_ddrss_cfg,
&qns_mnoc_cfg,
&qns_snoc_cfg,
- &srvc_cnoc
- },
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_cn2 = {
.name = "CN2",
.keepalive = false,
- .num_nodes = 5,
- .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 },
+ .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_nsp_gemnoc },
+ .nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_co3 = {
.name = "CO3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxm_nsp },
+ .nodes = { &qxm_nsp, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = false,
- .num_nodes = 3,
- .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
+ .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1, NULL },
};
static struct qcom_icc_bcm bcm_mm4 = {
.name = "MM4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_sf },
+ .nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_mm5 = {
.name = "MM5",
.keepalive = false,
- .num_nodes = 6,
.nodes = { &qnm_camnoc_icp,
&qnm_camnoc_sf,
&qnm_video0,
&qnm_video1,
&qnm_video_cvp,
- &qxm_rot
- },
+ &qxm_rot, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
- .num_nodes = 2,
- .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
+ .nodes = { &alm_gpu_tcu, &alm_sys_tcu, NULL },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_cmpnoc },
+ .nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &chm_apps },
+ .nodes = { &chm_apps, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_gc },
+ .nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qxs_pimem },
+ .nodes = { &qxs_pimem, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xs_qdss_stm },
+ .nodes = { &xs_qdss_stm, NULL },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xm_pcie3_0 },
+ .nodes = { &xm_pcie3_0, NULL },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &xm_pcie3_1 },
+ .nodes = { &xm_pcie3_1, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn14 = {
.name = "SN14",
.keepalive = false,
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c
index eb7e17df32ba656cf1934e0fc112189966b22ac2..94e60b5067625606e2b141fbde1b5d90425386d3 100644
--- a/drivers/interconnect/qcom/sm8450.c
+++ b/drivers/interconnect/qcom/sm8450.c
@@ -1340,21 +1340,18 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = 0x8,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.enable_mask = 0x1,
.keepalive = true,
- .num_nodes = 55,
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
&qhs_ahb2phy0, &qhs_ahb2phy1,
&qhs_aoss, &qhs_camera_cfg,
@@ -1382,160 +1379,139 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qxs_imem, &qxs_pimem,
&srvc_cnoc, &xs_pcie_0,
&xs_pcie_1, &xs_qdss_stm,
- &xs_sys_tcu_cfg },
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.enable_mask = 0x1,
- .num_nodes = 2,
- .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
+ .nodes = { &qxm_nsp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.enable_mask = 0x1,
- .num_nodes = 12,
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
&qnm_camnoc_sf, &qnm_mdp,
&qnm_mnoc_cfg, &qnm_rot,
&qnm_vapss_hcp, &qnm_video,
&qnm_video_cv_cpu, &qnm_video_cvp,
- &qnm_video_v_cpu, &qns_mem_noc_sf },
+ &qnm_video_v_cpu, &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup2 = {
.name = "QUP2",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup2_core_slave },
+ .nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.enable_mask = 0x1,
- .num_nodes = 7,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
&qnm_nsp_gemnoc, &qnm_pcie,
&qnm_snoc_gc, &qns_gem_noc_cnoc,
- &qns_pcie },
+ &qns_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.enable_mask = 0x1,
- .num_nodes = 4,
.nodes = { &qhm_gic, &qxm_pimem,
- &xm_gic, &qns_gemnoc_gc },
+ &xm_gic, &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 1,
- .nodes = { &qnm_lpass_noc },
+ .nodes = { &qnm_lpass_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_acv_disp = {
.name = "ACV",
.enable_mask = 0x1,
- .num_nodes = 1,
- .nodes = { &ebi_disp },
+ .nodes = { &ebi_disp, NULL },
};
static struct qcom_icc_bcm bcm_mc0_disp = {
.name = "MC0",
- .num_nodes = 1,
- .nodes = { &ebi_disp },
+ .nodes = { &ebi_disp, NULL },
};
static struct qcom_icc_bcm bcm_mm0_disp = {
.name = "MM0",
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf_disp },
+ .nodes = { &qns_mem_noc_hf_disp, NULL },
};
static struct qcom_icc_bcm bcm_mm1_disp = {
.name = "MM1",
.enable_mask = 0x1,
- .num_nodes = 3,
.nodes = { &qnm_mdp_disp, &qnm_rot_disp,
- &qns_mem_noc_sf_disp },
+ &qns_mem_noc_sf_disp, NULL },
};
static struct qcom_icc_bcm bcm_sh0_disp = {
.name = "SH0",
- .num_nodes = 1,
- .nodes = { &qns_llcc_disp },
+ .nodes = { &qns_llcc_disp, NULL },
};
static struct qcom_icc_bcm bcm_sh1_disp = {
.name = "SH1",
.enable_mask = 0x1,
- .num_nodes = 1,
- .nodes = { &qnm_pcie_disp },
+ .nodes = { &qnm_pcie_disp, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
index fdb97d1f1d074d17b55f10a5852ce80388b611b7..39101b4a423c1bb404a80a83eaf1ff96ccbf2bad 100644
--- a/drivers/interconnect/qcom/sm8550.c
+++ b/drivers/interconnect/qcom/sm8550.c
@@ -1120,21 +1120,18 @@ static struct qcom_icc_node qns_gemnoc_sf = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = 0x8,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.enable_mask = 0x1,
.keepalive = true,
- .num_nodes = 54,
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
&qhs_ahb2phy1, &qhs_apss,
&qhs_camera_cfg, &qhs_clk_ctl,
@@ -1161,126 +1158,110 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_aoss, &qhs_tme_cfg,
&qss_cfg, &qss_ddrss_cfg,
&qxs_boot_imem, &qxs_imem,
- &xs_pcie_0, &xs_pcie_1 },
+ &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
- .num_nodes = 1,
- .nodes = { &qhs_display_cfg },
+ .nodes = { &qhs_display_cfg, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.enable_mask = 0x1,
- .num_nodes = 2,
- .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
+ .nodes = { &qxm_nsp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_lp0 = {
.name = "LP0",
- .num_nodes = 2,
- .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
+ .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.enable_mask = 0x1,
- .num_nodes = 8,
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
&qnm_camnoc_sf, &qnm_vapss_hcp,
&qnm_video_cv_cpu, &qnm_video_cvp,
- &qnm_video_v_cpu, &qns_mem_noc_sf },
+ &qnm_video_v_cpu, &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup2 = {
.name = "QUP2",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup2_core_slave },
+ .nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.enable_mask = 0x1,
- .num_nodes = 13,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
&chm_apps, &qnm_gpu,
&qnm_mdsp, &qnm_mnoc_hf,
&qnm_mnoc_sf, &qnm_nsp_gemnoc,
&qnm_pcie, &qnm_snoc_gc,
&qnm_snoc_sf, &qns_gem_noc_cnoc,
- &qns_pcie },
+ &qns_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.enable_mask = 0x1,
- .num_nodes = 3,
.nodes = { &qhm_gic, &xm_gic,
- &qns_gemnoc_gc },
+ &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c
index b7c321f4e4b51cbcb138e906e561325393e3e14e..9ec2f1308923e5f69c102d2c2d25d25b42711fa0 100644
--- a/drivers/interconnect/qcom/sm8650.c
+++ b/drivers/interconnect/qcom/sm8650.c
@@ -1492,21 +1492,18 @@ static struct qcom_icc_node qns_gemnoc_sf = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(0),
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.enable_mask = BIT(0),
.keepalive = true,
- .num_nodes = 59,
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
&qhs_ahb2phy1, &qhs_camera_cfg,
&qhs_clk_ctl, &qhs_cpr_cx,
@@ -1536,80 +1533,70 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qhs_tme_cfg, &qss_apss,
&qss_cfg, &qss_ddrss_cfg,
&qxs_imem, &srvc_cnoc_main,
- &xs_pcie_0, &xs_pcie_1 },
+ &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.enable_mask = BIT(0),
- .num_nodes = 2,
- .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
+ .nodes = { &qnm_nsp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_lp0 = {
.name = "LP0",
- .num_nodes = 2,
- .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
+ .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.enable_mask = BIT(0),
- .num_nodes = 8,
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
&qnm_camnoc_sf, &qnm_vapss_hcp,
&qnm_video_cv_cpu, &qnm_video_cvp,
- &qnm_video_v_cpu, &qns_mem_noc_sf },
+ &qnm_video_v_cpu, &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup2 = {
.name = "QUP2",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup2_core_slave },
+ .nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.enable_mask = BIT(0),
- .num_nodes = 15,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
&alm_ubwc_p_tcu, &chm_apps,
&qnm_gpu, &qnm_mdsp,
@@ -1617,32 +1604,28 @@ static struct qcom_icc_bcm bcm_sh1 = {
&qnm_nsp_gemnoc, &qnm_pcie,
&qnm_snoc_sf, &qnm_ubwc_p,
&xm_gic, &qns_gem_noc_cnoc,
- &qns_pcie },
+ &qns_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom/sm8750.c
index 69bc22222075280365eb419f1ad140d1aa4e752d..eba39bf966c27254ca5df43c9acd7435a69726a2 100644
--- a/drivers/interconnect/qcom/sm8750.c
+++ b/drivers/interconnect/qcom/sm8750.c
@@ -1194,21 +1194,18 @@ static struct qcom_icc_node qns_gemnoc_sf = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(0),
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.enable_mask = BIT(0),
.keepalive = true,
- .num_nodes = 44,
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
&qhs_ahb2phy1, &qhs_camera_cfg,
&qhs_clk_ctl, &qhs_crypto0_cfg,
@@ -1230,127 +1227,111 @@ static struct qcom_icc_bcm bcm_cn0 = {
&qns_apss, &qss_cfg,
&qss_ddrss_cfg, &qxs_boot_imem,
&qxs_imem, &qxs_modem_boot_imem,
- &srvc_cnoc_main, &xs_pcie },
+ &srvc_cnoc_main, &xs_pcie, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
- .num_nodes = 5,
.nodes = { &qhs_display_cfg, &qhs_i2c,
&qhs_qup02, &qhs_qup1,
- &qhs_qup2 },
+ &qhs_qup2, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.enable_mask = BIT(0),
- .num_nodes = 2,
- .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
+ .nodes = { &qnm_nsp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_lp0 = {
.name = "LP0",
- .num_nodes = 2,
- .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
+ .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.enable_mask = BIT(0),
- .num_nodes = 9,
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf,
&qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf,
&qnm_vapss_hcp, &qnm_video_cv_cpu,
&qnm_video_mvp, &qnm_video_v_cpu,
- &qns_mem_noc_sf },
+ &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup2 = {
.name = "QUP2",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup2_core_slave },
+ .nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.enable_mask = BIT(0),
- .num_nodes = 14,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
&chm_apps, &qnm_gpu,
&qnm_mdsp, &qnm_mnoc_hf,
&qnm_mnoc_sf, &qnm_nsp_gemnoc,
&qnm_pcie, &qnm_snoc_sf,
&xm_gic, &chs_ubwc_p,
- &qns_gem_noc_cnoc, &qns_pcie },
+ &qns_gem_noc_cnoc, &qns_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_ubw0 = {
.name = "UBW0",
- .num_nodes = 1,
- .nodes = { &qnm_ubwc_p },
+ .nodes = { &qnm_ubwc_p, NULL },
};
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
index 2c46fdb4a0543f8345e03dbfe83d3a7ab95bd17c..f83a881b2becba9f7806bcc8f945e970596554b2 100644
--- a/drivers/interconnect/qcom/x1e80100.c
+++ b/drivers/interconnect/qcom/x1e80100.c
@@ -1356,20 +1356,17 @@ static struct qcom_icc_node qns_aggre_usb_south_snoc = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
- .num_nodes = 1,
- .nodes = { &qxm_crypto },
+ .nodes = { &qxm_crypto, NULL },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
- .num_nodes = 63,
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
&qhs_ahb2phy1, &qhs_ahb2phy2,
&qhs_av1_enc_cfg, &qhs_camera_cfg,
@@ -1401,122 +1398,106 @@ static struct qcom_icc_bcm bcm_cn0 = {
&xs_pcie_1, &xs_pcie_2,
&xs_pcie_3, &xs_pcie_4,
&xs_pcie_5, &xs_pcie_6a,
- &xs_pcie_6b },
+ &xs_pcie_6b, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
- .num_nodes = 1,
- .nodes = { &qhs_display_cfg },
+ .nodes = { &qhs_display_cfg, NULL },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
- .num_nodes = 2,
- .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
+ .nodes = { &qxm_nsp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_bcm bcm_lp0 = {
.name = "LP0",
- .num_nodes = 2,
- .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
+ .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &ebi },
+ .nodes = { &ebi, NULL },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
- .num_nodes = 1,
- .nodes = { &qns_mem_noc_hf },
+ .nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
- .num_nodes = 10,
.nodes = { &qnm_av1_enc, &qnm_camnoc_hf,
&qnm_camnoc_icp, &qnm_camnoc_sf,
&qnm_eva, &qnm_mdp,
&qnm_video, &qnm_video_cv_cpu,
- &qnm_video_v_cpu, &qns_mem_noc_sf },
+ &qnm_video_v_cpu, &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_bcm bcm_pc0 = {
.name = "PC0",
- .num_nodes = 1,
- .nodes = { &qns_pcie_mem_noc },
+ .nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup0_core_slave },
+ .nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup1_core_slave },
+ .nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_qup2 = {
.name = "QUP2",
.keepalive = true,
.vote_scale = 1,
- .num_nodes = 1,
- .nodes = { &qup2_core_slave },
+ .nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_llcc },
+ .nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
- .num_nodes = 13,
.nodes = { &alm_gpu_tcu, &alm_pcie_tcu,
&alm_sys_tcu, &chm_apps,
&qnm_gpu, &qnm_lpass,
&qnm_mnoc_hf, &qnm_mnoc_sf,
&qnm_nsp_noc, &qnm_pcie,
&xm_gic, &qns_gem_noc_cnoc,
- &qns_pcie },
+ &qns_pcie, NULL },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
- .num_nodes = 1,
- .nodes = { &qns_gemnoc_sf },
+ .nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
- .num_nodes = 1,
- .nodes = { &qnm_aggre1_noc },
+ .nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
- .num_nodes = 1,
- .nodes = { &qnm_aggre2_noc },
+ .nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
- .num_nodes = 1,
- .nodes = { &qnm_usb_anoc },
+ .nodes = { &qnm_usb_anoc, NULL },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array
2025-07-04 16:35 ` [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array Dmitry Baryshkov
@ 2025-07-08 16:41 ` Konrad Dybcio
2025-07-18 13:38 ` Georgi Djakov
1 sibling, 0 replies; 38+ messages in thread
From: Konrad Dybcio @ 2025-07-08 16:41 UTC (permalink / raw)
To: Dmitry Baryshkov, Georgi Djakov, Bjorn Andersson
Cc: linux-arm-msm, linux-pm, linux-kernel
On 7/4/25 6:35 PM, Dmitry Baryshkov wrote:
> Having the .num_nodes as a separate struct field can provoke errors as
> it is easy to omit it or to put an incorrect value into that field. Turn
> .nodes into a NULL-terminated array, removing a need for a separate
> .num_nodes field.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
I'm not totally sure.. failing to NULL-terminate is as easy to overlook
as failing to add .num_nodes
At the end of the day, potayto/potato, even the memory footprint doesn't
change.. But if you insist, please make sure that the mass-update didn't
miss anything, so someone in 2 years doesn't decide that actually counting
the items is a better idea instead.
Konrad
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array
2025-07-04 16:35 ` [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array Dmitry Baryshkov
2025-07-08 16:41 ` Konrad Dybcio
@ 2025-07-18 13:38 ` Georgi Djakov
2025-07-18 17:26 ` Dmitry Baryshkov
1 sibling, 1 reply; 38+ messages in thread
From: Georgi Djakov @ 2025-07-18 13:38 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Hi Dmitry,
On 7/4/25 7:35 PM, Dmitry Baryshkov wrote:
> Having the .num_nodes as a separate struct field can provoke errors as
> it is easy to omit it or to put an incorrect value into that field. Turn
> .nodes into a NULL-terminated array, removing a need for a separate
> .num_nodes field.
I am not entirely convinced that an error in the termination is more
unlikely than an error in the num_nodes. Aren't we trading one kind of
error for another? Also if we omit the num_nodes i expect that just the
QoS of a specific path will fail, but if we miss the NULL - worse things
might happen.
[..]
> 27 files changed, 541 insertions(+), 1119 deletions(-)
The negative diffstat is nice.
>
> diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
> index a2d437a05a11fa7325f944865c81a3ac7dbb203e..4fa960630d28f338f484794d271a5b52f3e698d3 100644
> --- a/drivers/interconnect/qcom/bcm-voter.c
> +++ b/drivers/interconnect/qcom/bcm-voter.c
> @@ -68,7 +68,7 @@ static void bcm_aggregate_mask(struct qcom_icc_bcm *bcm)
> bcm->vote_x[bucket] = 0;
> bcm->vote_y[bucket] = 0;
>
> - for (i = 0; i < bcm->num_nodes; i++) {
> + for (i = 0; bcm->nodes[i]; i++) {
> node = bcm->nodes[i];
I like better the single memory access and the two registers comparison
that we already have, but both are fine as we are not in some critical
section.
[..]
> diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
> index bd8d730249b1c9e5b37afbee485b9500a8028c2e..0018aa74187edcac9a0492c737771d957a133cc0 100644
> --- a/drivers/interconnect/qcom/icc-rpmh.h
> +++ b/drivers/interconnect/qcom/icc-rpmh.h
> @@ -126,7 +126,6 @@ struct qcom_icc_node {
> * communicating with RPMh
> * @list: used to link to other bcms when compiling lists for commit
> * @ws_list: used to keep track of bcms that may transition between wake/sleep
> - * @num_nodes: total number of @num_nodes
> * @nodes: list of qcom_icc_nodes that this BCM encapsulates
> */
> struct qcom_icc_bcm {
> @@ -142,7 +141,6 @@ struct qcom_icc_bcm {
> struct bcm_db aux_data;
> struct list_head list;
> struct list_head ws_list;
> - size_t num_nodes;
So no change in memory footprint, as now instead of the num_nodes, there
will be an additional NULL pointer for termination.
[..]
Well, this approach is also good. The existing one just follows the pattern
used by other frameworks, that seemed more common and thus make the code
easier to read and review.
I don't see a strong argument to switch to a NULL terminated arrays (yet),
as it does not make things any better for performance/memory, so I'm not
sure if it's worth reshuffling the 10k+ LoC in drivers. Is there any other
argument that i miss?
Thanks,
Georgi
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array
2025-07-18 13:38 ` Georgi Djakov
@ 2025-07-18 17:26 ` Dmitry Baryshkov
2025-07-18 22:17 ` Konrad Dybcio
0 siblings, 1 reply; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-18 17:26 UTC (permalink / raw)
To: Georgi Djakov; +Cc: Bjorn Andersson, linux-arm-msm, linux-pm, linux-kernel
On Fri, Jul 18, 2025 at 04:38:02PM +0300, Georgi Djakov wrote:
> Hi Dmitry,
>
> On 7/4/25 7:35 PM, Dmitry Baryshkov wrote:
> > Having the .num_nodes as a separate struct field can provoke errors as
> > it is easy to omit it or to put an incorrect value into that field. Turn
> > .nodes into a NULL-terminated array, removing a need for a separate
> > .num_nodes field.
>
> I am not entirely convinced that an error in the termination is more
> unlikely than an error in the num_nodes. Aren't we trading one kind of
> error for another? Also if we omit the num_nodes i expect that just the
> QoS of a specific path will fail, but if we miss the NULL - worse things
> might happen.
Exactly, that's the point. It is easy to miss num_nodes, while omitting
NULL will crash the driver. So the error will be noted during
development.
>
> [..]
> > 27 files changed, 541 insertions(+), 1119 deletions(-)
>
> The negative diffstat is nice.
>
> >
> > diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
> > index a2d437a05a11fa7325f944865c81a3ac7dbb203e..4fa960630d28f338f484794d271a5b52f3e698d3 100644
> > --- a/drivers/interconnect/qcom/bcm-voter.c
> > +++ b/drivers/interconnect/qcom/bcm-voter.c
> > @@ -68,7 +68,7 @@ static void bcm_aggregate_mask(struct qcom_icc_bcm *bcm)
> > bcm->vote_x[bucket] = 0;
> > bcm->vote_y[bucket] = 0;
> > - for (i = 0; i < bcm->num_nodes; i++) {
> > + for (i = 0; bcm->nodes[i]; i++) {
> > node = bcm->nodes[i];
>
> I like better the single memory access and the two registers comparison
> that we already have, but both are fine as we are not in some critical
> section.
>
> [..]
> > diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
> > index bd8d730249b1c9e5b37afbee485b9500a8028c2e..0018aa74187edcac9a0492c737771d957a133cc0 100644
> > --- a/drivers/interconnect/qcom/icc-rpmh.h
> > +++ b/drivers/interconnect/qcom/icc-rpmh.h
> > @@ -126,7 +126,6 @@ struct qcom_icc_node {
> > * communicating with RPMh
> > * @list: used to link to other bcms when compiling lists for commit
> > * @ws_list: used to keep track of bcms that may transition between wake/sleep
> > - * @num_nodes: total number of @num_nodes
> > * @nodes: list of qcom_icc_nodes that this BCM encapsulates
> > */
> > struct qcom_icc_bcm {
> > @@ -142,7 +141,6 @@ struct qcom_icc_bcm {
> > struct bcm_db aux_data;
> > struct list_head list;
> > struct list_head ws_list;
> > - size_t num_nodes;
>
> So no change in memory footprint, as now instead of the num_nodes, there
> will be an additional NULL pointer for termination.
>
> [..]
>
> Well, this approach is also good. The existing one just follows the pattern
> used by other frameworks, that seemed more common and thus make the code
> easier to read and review.
>
> I don't see a strong argument to switch to a NULL terminated arrays (yet),
> as it does not make things any better for performance/memory, so I'm not
> sure if it's worth reshuffling the 10k+ LoC in drivers. Is there any other
> argument that i miss?
Well, two arguments:
- Two first patches in the series (which fix num_links / num_nodes).
- I think we should drop the old (static IDs) code path. Switching to
dynamic IDs would require reshuffling of the drivers (and these
arrays) anyway.
>
> Thanks,
> Georgi
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array
2025-07-18 17:26 ` Dmitry Baryshkov
@ 2025-07-18 22:17 ` Konrad Dybcio
2025-07-18 22:44 ` Dmitry Baryshkov
0 siblings, 1 reply; 38+ messages in thread
From: Konrad Dybcio @ 2025-07-18 22:17 UTC (permalink / raw)
To: Dmitry Baryshkov, Georgi Djakov
Cc: Bjorn Andersson, linux-arm-msm, linux-pm, linux-kernel
On 7/18/25 7:26 PM, Dmitry Baryshkov wrote:
> On Fri, Jul 18, 2025 at 04:38:02PM +0300, Georgi Djakov wrote:
>> Hi Dmitry,
>>
>> On 7/4/25 7:35 PM, Dmitry Baryshkov wrote:
>>> Having the .num_nodes as a separate struct field can provoke errors as
>>> it is easy to omit it or to put an incorrect value into that field. Turn
>>> .nodes into a NULL-terminated array, removing a need for a separate
>>> .num_nodes field.
>>
>> I am not entirely convinced that an error in the termination is more
>> unlikely than an error in the num_nodes. Aren't we trading one kind of
>> error for another? Also if we omit the num_nodes i expect that just the
>> QoS of a specific path will fail, but if we miss the NULL - worse things
>> might happen.
>
> Exactly, that's the point. It is easy to miss num_nodes, while omitting
> NULL will crash the driver. So the error will be noted during
> development.
I really don't wanna step on your development, but again, I don't think
this is a good solution.. maybe WARN_ON(!desc->num_nodes) would be better?
Some static checks?
Konrad
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array
2025-07-18 22:17 ` Konrad Dybcio
@ 2025-07-18 22:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-18 22:44 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Georgi Djakov, Bjorn Andersson, linux-arm-msm, linux-pm,
linux-kernel
On Sat, Jul 19, 2025 at 12:17:47AM +0200, Konrad Dybcio wrote:
> On 7/18/25 7:26 PM, Dmitry Baryshkov wrote:
> > On Fri, Jul 18, 2025 at 04:38:02PM +0300, Georgi Djakov wrote:
> >> Hi Dmitry,
> >>
> >> On 7/4/25 7:35 PM, Dmitry Baryshkov wrote:
> >>> Having the .num_nodes as a separate struct field can provoke errors as
> >>> it is easy to omit it or to put an incorrect value into that field. Turn
> >>> .nodes into a NULL-terminated array, removing a need for a separate
> >>> .num_nodes field.
> >>
> >> I am not entirely convinced that an error in the termination is more
> >> unlikely than an error in the num_nodes. Aren't we trading one kind of
> >> error for another? Also if we omit the num_nodes i expect that just the
> >> QoS of a specific path will fail, but if we miss the NULL - worse things
> >> might happen.
> >
> > Exactly, that's the point. It is easy to miss num_nodes, while omitting
> > NULL will crash the driver. So the error will be noted during
> > development.
>
> I really don't wanna step on your development, but again, I don't think
No worries :-)
> this is a good solution.. maybe WARN_ON(!desc->num_nodes) would be better?
> Some static checks?
Another option would be to follow RPM path: move links into external
array and use ARRAY_SIZE. It's still error prone, but it is easier to
spot.
But really... For the array of pointers NULL trailer is the most logical
way of specifying the end of it.
>
> Konrad
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v2 04/28] interconnect: qcom: rpmh: make link_nodes a NULL_terminated array
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (2 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 03/28] interconnect: qcom: rpmh: make nodes a NULL_terminated array Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 05/28] interconnect: qcom: sc7280: convert to dynamic IDs Dmitry Baryshkov
` (24 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Having the .num_links as a separate struct field can provoke errors as
it is easy to omit it or to put an incorrect value into that field. Turn
.link_nodes into a NULL-terminated array, removing a need for a separate
.num_links field if .link_nodes is being used. This creates a deviation
between non-dynamic and dynamic ID cases, but it won't stay like that
for too long.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/icc-rpmh.c | 7 +-
drivers/interconnect/qcom/icc-rpmh.h | 4 +-
drivers/interconnect/qcom/sa8775p.c | 395 ++++++++++++++++++-----------------
3 files changed, 207 insertions(+), 199 deletions(-)
diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
index 7854e3a60d97eb3cdb0a5c1f1b77a96afc104009..941692cbaf208c66a27dda2e6902b2f26f605840 100644
--- a/drivers/interconnect/qcom/icc-rpmh.c
+++ b/drivers/interconnect/qcom/icc-rpmh.c
@@ -302,10 +302,11 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
node->data = qn;
icc_node_add(node, provider);
- for (j = 0; j < qn->num_links; j++) {
- if (desc->alloc_dyn_id)
+ if (desc->alloc_dyn_id) {
+ for (j = 0; qn->link_nodes[j]; j++)
icc_link_nodes(node, &qn->link_nodes[j]->node);
- else
+ } else {
+ for (j = 0; j < qn->num_links; j++)
icc_link_create(node, qn->links[j]);
}
diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
index 0018aa74187edcac9a0492c737771d957a133cc0..742941a296ac0a2e3d3e7147c25f750965a36647 100644
--- a/drivers/interconnect/qcom/icc-rpmh.h
+++ b/drivers/interconnect/qcom/icc-rpmh.h
@@ -83,7 +83,6 @@ struct qcom_icc_qosbox {
* @name: the node name used in debugfs
* @links: an array of nodes where we can go next while traversing
* @id: a unique node identifier
- * @link_nodes: links associated with this node
* @node: icc_node associated with this node
* @num_links: the total number of @links
* @channels: num of channels at this node
@@ -93,12 +92,12 @@ struct qcom_icc_qosbox {
* @bcms: list of bcms associated with this logical node
* @num_bcms: num of @bcms
* @qosbox: QoS config data associated with node
+ * @link_nodes: links associated with this node
*/
struct qcom_icc_node {
const char *name;
u16 links[MAX_LINKS];
u16 id;
- struct qcom_icc_node **link_nodes;
struct icc_node *node;
u16 num_links;
u16 channels;
@@ -108,6 +107,7 @@ struct qcom_icc_node {
struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE];
size_t num_bcms;
const struct qcom_icc_qosbox *qosbox;
+ struct qcom_icc_node *link_nodes[];
};
/**
diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
index 6bbe2fe03f791dd5d3606114d71d62057ddc52d2..a7049eb22d1e064afea17812637b720f907de90e 100644
--- a/drivers/interconnect/qcom/sa8775p.c
+++ b/drivers/interconnect/qcom/sa8775p.c
@@ -213,192 +213,168 @@ static struct qcom_icc_node qxm_qup3 = {
.name = "qxm_qup3",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emac_1 = {
.name = "xm_emac_1",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb2_2 = {
.name = "xm_usb2_2",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto_0 = {
.name = "qxm_crypto_0",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto_1 = {
.name = "qxm_crypto_1",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_card = {
.name = "xm_ufs_card",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qup2_core_slave },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qup3_core_master = {
.name = "qup3_core_master",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qup3_core_slave },
+ .link_nodes = { &qup3_core_slave, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
.channels = 1,
.buswidth = 16,
- .num_links = 82,
- .link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
&qhs_ahb2phy2, &qhs_ahb2phy3,
&qhs_anoc_throttle_cfg, &qhs_aoss,
&qhs_apss, &qhs_boot_rom,
@@ -438,1166 +414,1197 @@ static struct qcom_icc_node qnm_gemnoc_cnoc = {
&qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
&qns_snoc_cfg, &qxs_boot_imem,
&qxs_imem, &qxs_pimem,
- &xs_qdss_stm, &xs_sys_tcu_cfg },
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_node qnm_cnoc_dc_noc = {
.name = "qnm_cnoc_dc_noc",
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qhs_llcc, &qns_gemnoc },
+ .link_nodes = { &qhs_llcc, &qns_gemnoc, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_pcie_tcu = {
.name = "alm_pcie_tcu",
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
.channels = 4,
.buswidth = 32,
- .num_links = 3,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
- &qns_pcie },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_cmpnoc0 = {
.name = "qnm_cmpnoc0",
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_cmpnoc1 = {
.name = "qnm_cmpnoc1",
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 4,
- .link_nodes = (struct qcom_icc_node *[]) { &srvc_even_gemnoc, &srvc_odd_gemnoc,
- &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 },
+ .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc,
+ &srvc_sys_gemnoc, &srvc_sys_gemnoc_2, NULL },
};
static struct qcom_icc_node qnm_gpdsp_sail = {
.name = "qnm_gpdsp_sail",
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie },
+ .link_nodes = { &qns_llcc, &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
- &qns_pcie },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
- &qns_pcie },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qxm_dsp0 = {
.name = "qxm_dsp0",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc },
+ .link_nodes = { &qns_gp_dsp_sail_noc, NULL },
};
static struct qcom_icc_node qxm_dsp1 = {
.name = "qxm_dsp1",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc },
+ .link_nodes = { &qns_gp_dsp_sail_noc, NULL },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
.channels = 1,
.buswidth = 4,
- .num_links = 6,
- .link_nodes = (struct qcom_icc_node *[]) { &qhs_lpass_core, &qhs_lpass_lpi,
- &qhs_lpass_mpu, &qhs_lpass_top,
- &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
+ .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
+ &qhs_lpass_mpu, &qhs_lpass_top,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node qxm_lpass_dsp = {
.name = "qxm_lpass_dsp",
.channels = 1,
.buswidth = 8,
- .num_links = 4,
- .link_nodes = (struct qcom_icc_node *[]) { &qhs_lpass_top, &qns_sysnoc,
- &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
+ .link_nodes = { &qhs_lpass_top, &qns_sysnoc,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.channels = 8,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &ebi },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_mdp0_0 = {
.name = "qnm_mdp0_0",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mdp0_1 = {
.name = "qnm_mdp0_1",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mdp1_0 = {
.name = "qnm_mdp1_0",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mdp1_1 = {
.name = "qnm_mdp1_1",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf_cfg = {
.name = "qnm_mnoc_hf_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_hf },
+ .link_nodes = { &srvc_mnoc_hf, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf_cfg = {
.name = "qnm_mnoc_sf_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_sf },
+ .link_nodes = { &srvc_mnoc_sf, NULL },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video1 = {
.name = "qnm_video1",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &service_nsp_noc },
+ .link_nodes = { &service_nsp_noc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_hcp, &qns_nsp_gemnoc },
+ .link_nodes = { &qns_hcp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qhm_nspb_noc_config = {
.name = "qhm_nspb_noc_config",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &service_nspb_noc },
+ .link_nodes = { &service_nspb_noc, NULL },
};
static struct qcom_icc_node qxm_nspb = {
.name = "qxm_nspb",
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_nspb_hcp, &qns_nspb_gemnoc },
+ .link_nodes = { &qns_nspb_hcp, &qns_nspb_gemnoc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_lpass_noc = {
.name = "qnm_lpass_noc",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &srvc_snoc },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup3_core_slave = {
.name = "qup3_core_slave",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy2 = {
.name = "qhs_ahb2phy2",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy3 = {
.name = "qhs_ahb2phy3",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_anoc_throttle_cfg = {
.name = "qhs_anoc_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_boot_rom = {
.name = "qhs_boot_rom",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
.name = "qhs_camera_nrt_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
.name = "qhs_camera_rt_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute0_cfg = {
.name = "qhs_compute0_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qhm_nsp_noc_config },
+ .link_nodes = { &qhm_nsp_noc_config, NULL },
};
static struct qcom_icc_node qhs_compute1_cfg = {
.name = "qhs_compute1_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qhm_nspb_noc_config },
+ .link_nodes = { &qhm_nspb_noc_config, NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_nspcx = {
.name = "qhs_cpr_nspcx",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display0_cfg = {
.name = "qhs_display0_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
.name = "qhs_display0_rt_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display1_cfg = {
.name = "qhs_display1_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
.name = "qhs_display1_rt_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emac0_cfg = {
.name = "qhs_emac0_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emac1_cfg = {
.name = "qhs_emac1_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gp_dsp0_cfg = {
.name = "qhs_gp_dsp0_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gp_dsp1_cfg = {
.name = "qhs_gp_dsp1_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
.name = "qhs_gpdsp0_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
.name = "qhs_gpdsp1_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
.name = "qhs_gpu_tcu_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_hwkm = {
.name = "qhs_hwkm",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qhm_config_noc },
+ .link_nodes = { &qhm_config_noc, NULL },
};
static struct qcom_icc_node qhs_lpass_throttle_cfg = {
.name = "qhs_lpass_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mxc_rdpm = {
.name = "qhs_mxc_rdpm",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_rsc_cfg = {
.name = "qhs_pcie_rsc_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
.name = "qhs_pcie_tcu_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_throttle_cfg = {
.name = "qhs_pcie_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pke_wrapper_cfg = {
.name = "qhs_pke_wrapper_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qm_cfg = {
.name = "qhs_qm_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qm_mpu_cfg = {
.name = "qhs_qm_mpu_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup3 = {
.name = "qhs_qup3",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sail_throttle_cfg = {
.name = "qhs_sail_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_throttle_cfg = {
.name = "qhs_snoc_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tsc_cfg = {
.name = "qhs_tsc_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_card_cfg = {
.name = "qhs_ufs_card_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb2_0 = {
.name = "qhs_usb2_0",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_1 = {
.name = "qhs_usb3_1",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
.name = "qhs_venus_cvp_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
.name = "qhs_venus_v_cpu_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
.name = "qhs_venus_vcodec_throttle_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_cnoc_dc_noc },
+ .link_nodes = { &qnm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qns_gpdsp_noc_cfg = {
.name = "qns_gpdsp_noc_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mnoc_hf_cfg = {
.name = "qns_mnoc_hf_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf_cfg },
+ .link_nodes = { &qnm_mnoc_hf_cfg, NULL },
};
static struct qcom_icc_node qns_mnoc_sf_cfg = {
.name = "qns_mnoc_sf_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf_cfg },
+ .link_nodes = { &qnm_mnoc_sf_cfg, NULL },
};
static struct qcom_icc_node qns_pcie_anoc_cfg = {
.name = "qns_pcie_anoc_cfg",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_cfg },
+ .link_nodes = { &qnm_snoc_cfg, NULL },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
.channels = 1,
.buswidth = 16,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
.channels = 1,
.buswidth = 16,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cfg },
+ .link_nodes = { &qnm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.channels = 6,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &llcc_mc },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_sys_gemnoc_2 = {
.name = "srvc_sys_gemnoc_2",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gp_dsp_sail_noc = {
.name = "qns_gp_dsp_sail_noc",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_gpdsp_sail },
+ .link_nodes = { &qnm_gpdsp_sail, NULL },
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_sysnoc = {
.name = "qns_sysnoc",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_noc },
+ .link_nodes = { &qnm_lpass_noc, NULL },
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.channels = 8,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc_hf = {
.name = "srvc_mnoc_hf",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_mnoc_sf = {
.name = "srvc_mnoc_sf",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_hcp = {
.name = "qns_hcp",
.channels = 2,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_cmpnoc0 },
+ .link_nodes = { &qnm_cmpnoc0, NULL },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nspb_gemnoc = {
.name = "qns_nspb_gemnoc",
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_cmpnoc1 },
+ .link_nodes = { &qnm_cmpnoc1, NULL },
};
static struct qcom_icc_node qns_nspb_hcp = {
.name = "qns_nspb_hcp",
.channels = 2,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node service_nspb_noc = {
.name = "service_nspb_noc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_gc },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 05/28] interconnect: qcom: sc7280: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (3 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 04/28] interconnect: qcom: rpmh: make link_nodes " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 06/28] interconnect: qcom: sc8180x: " Dmitry Baryshkov
` (23 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sc7280.c | 771 +++++++++++++++++--------------------
drivers/interconnect/qcom/sc7280.h | 154 --------
2 files changed, 354 insertions(+), 571 deletions(-)
diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c
index 54e4ce9009bd498a840832e3f63dd9abfb86f837..c39e79d82b482ae3e35b292fe1a2d4cfc911d969 100644
--- a/drivers/interconnect/qcom/sc7280.c
+++ b/drivers/interconnect/qcom/sc7280.c
@@ -15,11 +15,152 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sc7280.h"
+
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qnm_a1noc_cfg;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb2;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qnm_a2noc_cfg;
+static struct qcom_icc_node qnm_cnoc_datapath;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qnm_cnoc3_cnoc2;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qnm_cnoc2_cnoc3;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qnm_cnoc_dc_noc;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_gemnoc_cfg;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qhm_config_noc;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_mnoc_cfg;
+static struct qcom_icc_node qnm_video0;
+static struct qcom_icc_node qnm_video_cpu;
+static struct qcom_icc_node qxm_camnoc_hf;
+static struct qcom_icc_node qxm_camnoc_icp;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qhm_nsp_noc_config;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_snoc_cfg;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_hwkm;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_pka_wrapper_cfg;
+static struct qcom_icc_node qhs_pmu_wrapper_cfg;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_security;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb2;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_a1_noc_cfg;
+static struct qcom_icc_node qns_a2_noc_cfg;
+static struct qcom_icc_node qns_cnoc2_cnoc3;
+static struct qcom_icc_node qns_mnoc_cfg;
+static struct qcom_icc_node qns_snoc_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc3_cnoc2;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qns_gemnoc;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qhs_modem_ms_mpu_cfg;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node srvc_even_gemnoc;
+static struct qcom_icc_node srvc_odd_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc;
+static struct qcom_icc_node qhs_lpass_core;
+static struct qcom_icc_node qhs_lpass_lpi;
+static struct qcom_icc_node qhs_lpass_mpu;
+static struct qcom_icc_node qhs_lpass_top;
+static struct qcom_icc_node srvc_niu_aml_noc;
+static struct qcom_icc_node srvc_niu_lpass_agnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node service_nsp_noc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node srvc_snoc;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SC7280_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -28,13 +169,11 @@ static struct qcom_icc_node qhm_qspi = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SC7280_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -43,13 +182,11 @@ static struct qcom_icc_node qhm_qup0 = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SC7280_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -58,22 +195,18 @@ static struct qcom_icc_node qhm_qup1 = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qnm_a1noc_cfg = {
.name = "qnm_a1noc_cfg",
- .id = SC7280_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = SC7280_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -82,13 +215,11 @@ static struct qcom_icc_node xm_sdc1 = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SC7280_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -97,13 +228,11 @@ static struct qcom_icc_node xm_sdc2 = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SC7280_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -112,13 +241,11 @@ static struct qcom_icc_node xm_sdc4 = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SC7280_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -127,22 +254,18 @@ static struct qcom_icc_node xm_ufs_mem = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb2 = {
.name = "xm_usb2",
- .id = SC7280_MASTER_USB2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SC7280_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -151,13 +274,11 @@ static struct qcom_icc_node xm_usb3_0 = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SC7280_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -166,22 +287,18 @@ static struct qcom_icc_node qhm_qdss_bam = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_a2noc_cfg = {
.name = "qnm_a2noc_cfg",
- .id = SC7280_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
- .id = SC7280_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -190,13 +307,11 @@ static struct qcom_icc_node qnm_cnoc_datapath = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SC7280_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -205,13 +320,11 @@ static struct qcom_icc_node qxm_crypto = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SC7280_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -220,31 +333,25 @@ static struct qcom_icc_node qxm_ipa = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SC7280_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SC7280_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SC7280_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -253,136 +360,118 @@ static struct qcom_icc_node xm_qdss_etr = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SC7280_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SC7280_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qnm_cnoc3_cnoc2 = {
.name = "qnm_cnoc3_cnoc2",
- .id = SC7280_MASTER_CNOC3_CNOC2,
.channels = 1,
.buswidth = 8,
- .num_links = 44,
- .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
- SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
- SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
- SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
- SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
- SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
- SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
- SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
- SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
- SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
- SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
- SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
- SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
- SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
- SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
- SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
- SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
- SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
- SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
- SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
- SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
- SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_compute_cfg, &qhs_cpr_cx,
+ &qhs_cpr_mx, &qhs_crypto0_cfg,
+ &qhs_cx_rdpm, &qhs_dcc_cfg,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_hwkm, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_lpass_cfg, &qhs_mss_cfg,
+ &qhs_mx_rdpm, &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg, &qhs_pdm,
+ &qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
+ &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc1,
+ &qhs_sdc2, &qhs_sdc4,
+ &qhs_security, &qhs_tcsr,
+ &qhs_tlmm, &qhs_ufs_mem_cfg,
+ &qhs_usb2, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qns_a1_noc_cfg, &qns_a2_noc_cfg,
+ &qns_mnoc_cfg, &qns_snoc_cfg, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SC7280_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 45,
- .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
- SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
- SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
- SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
- SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
- SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
- SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
- SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
- SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
- SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
- SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
- SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
- SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
- SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
- SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
- SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
- SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
- SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
- SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
- SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
- SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
- SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG,
- SC7280_SLAVE_SNOC_CFG },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_compute_cfg, &qhs_cpr_cx,
+ &qhs_cpr_mx, &qhs_crypto0_cfg,
+ &qhs_cx_rdpm, &qhs_dcc_cfg,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_hwkm, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_lpass_cfg, &qhs_mss_cfg,
+ &qhs_mx_rdpm, &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg, &qhs_pdm,
+ &qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
+ &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc1,
+ &qhs_sdc2, &qhs_sdc4,
+ &qhs_security, &qhs_tcsr,
+ &qhs_tlmm, &qhs_ufs_mem_cfg,
+ &qhs_usb2, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qns_a1_noc_cfg, &qns_a2_noc_cfg,
+ &qns_cnoc2_cnoc3, &qns_mnoc_cfg,
+ &qns_snoc_cfg, NULL },
};
static struct qcom_icc_node qnm_cnoc2_cnoc3 = {
.name = "qnm_cnoc2_cnoc3",
- .id = SC7280_MASTER_CNOC2_CNOC3,
.channels = 1,
.buswidth = 8,
- .num_links = 9,
- .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
- SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG,
- SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
- SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
- SC7280_SLAVE_TCU },
+ .link_nodes = { &qhs_aoss, &qhs_apss,
+ &qns_cnoc_a2noc, &qns_ddrss_cfg,
+ &qxs_boot_imem, &qxs_imem,
+ &qxs_pimem, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SC7280_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 9,
- .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
- SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG,
- SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
- SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
- SC7280_SLAVE_TCU },
+ .link_nodes = { &qhs_aoss, &qhs_apss,
+ &qns_cnoc3_cnoc2, &qns_ddrss_cfg,
+ &qxs_boot_imem, &qxs_imem,
+ &qxs_pimem, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_node qnm_cnoc_dc_noc = {
.name = "qnm_cnoc_dc_noc",
- .id = SC7280_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG },
+ .link_nodes = { &qhs_llcc, &qns_gemnoc, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SC7280_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -391,13 +480,11 @@ static struct qcom_icc_node alm_gpu_tcu = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SC7280_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -406,23 +493,19 @@ static struct qcom_icc_node alm_sys_tcu = {
.prio = 6,
.urg_fwd = 0,
},
- .num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SC7280_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 3,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
- SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SC7280_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -431,24 +514,20 @@ static struct qcom_icc_node qnm_cmpnoc = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
- .id = SC7280_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 5,
- .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG,
- SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2,
- SC7280_SLAVE_SERVICE_GEM_NOC },
+ .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &qhs_modem_ms_mpu_cfg,
+ &srvc_even_gemnoc, &srvc_odd_gemnoc,
+ &srvc_sys_gemnoc, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SC7280_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -457,13 +536,11 @@ static struct qcom_icc_node qnm_gpu = {
.prio = 0,
.urg_fwd = 0,
},
- .num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SC7280_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -472,13 +549,11 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SC7280_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -487,22 +562,18 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SC7280_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -511,13 +582,11 @@ static struct qcom_icc_node qnm_snoc_gc = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SC7280_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -526,43 +595,35 @@ static struct qcom_icc_node qnm_snoc_sf = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 3,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
- SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
- .id = SC7280_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 6,
- .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG,
- SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG,
- SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC },
+ .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
+ &qhs_lpass_mpu, &qhs_lpass_top,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SC7280_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_mnoc_cfg = {
.name = "qnm_mnoc_cfg",
- .id = SC7280_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
- .id = SC7280_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -571,13 +632,11 @@ static struct qcom_icc_node qnm_video0 = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cpu = {
.name = "qnm_video_cpu",
- .id = SC7280_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -586,13 +645,11 @@ static struct qcom_icc_node qnm_video_cpu = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf = {
.name = "qxm_camnoc_hf",
- .id = SC7280_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -601,13 +658,11 @@ static struct qcom_icc_node qxm_camnoc_hf = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_icp = {
.name = "qxm_camnoc_icp",
- .id = SC7280_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -616,13 +671,11 @@ static struct qcom_icc_node qxm_camnoc_icp = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SC7280_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -631,13 +684,11 @@ static struct qcom_icc_node qxm_camnoc_sf = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SC7280_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -646,58 +697,46 @@ static struct qcom_icc_node qxm_mdp0 = {
.prio = 0,
.urg_fwd = 1,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
- .id = SC7280_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_NSP_NOC },
+ .link_nodes = { &service_nsp_noc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SC7280_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7280_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SC7280_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SC7280_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
- .id = SC7280_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SC7280_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -706,13 +745,11 @@ static struct qcom_icc_node qxm_pimem = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SC7280_MASTER_GIC,
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
@@ -721,742 +758,630 @@ static struct qcom_icc_node xm_gic = {
.prio = 2,
.urg_fwd = 0,
},
- .num_links = 1,
- .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SC7280_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7280_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SC7280_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SC7280_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7280_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SC7280_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SC7280_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SC7280_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SC7280_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SC7280_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SC7280_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SC7280_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_cfg = {
.name = "qhs_compute_cfg",
- .id = SC7280_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_MASTER_CDSP_NOC_CFG },
+ .link_nodes = { &qhm_nsp_noc_config, NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SC7280_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SC7280_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SC7280_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SC7280_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SC7280_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SC7280_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SC7280_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_hwkm = {
.name = "qhs_hwkm",
- .id = SC7280_SLAVE_HWKM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SC7280_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SC7280_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SC7280_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = SC7280_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC },
+ .link_nodes = { &qhm_config_noc, NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SC7280_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SC7280_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SC7280_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SC7280_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SC7280_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SC7280_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pka_wrapper_cfg = {
.name = "qhs_pka_wrapper_cfg",
- .id = SC7280_SLAVE_PKA_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
.name = "qhs_pmu_wrapper_cfg",
- .id = SC7280_SLAVE_PMU_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SC7280_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SC7280_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SC7280_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SC7280_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = SC7280_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SC7280_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SC7280_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
- .id = SC7280_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SC7280_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SC7280_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SC7280_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb2 = {
.name = "qhs_usb2",
- .id = SC7280_SLAVE_USB2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SC7280_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SC7280_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SC7280_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a1_noc_cfg = {
.name = "qns_a1_noc_cfg",
- .id = SC7280_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_MASTER_A1NOC_CFG },
+ .link_nodes = { &qnm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qns_a2_noc_cfg = {
.name = "qns_a2_noc_cfg",
- .id = SC7280_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_MASTER_A2NOC_CFG },
+ .link_nodes = { &qnm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qns_cnoc2_cnoc3 = {
.name = "qns_cnoc2_cnoc3",
- .id = SC7280_SLAVE_CNOC2_CNOC3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7280_MASTER_CNOC2_CNOC3 },
+ .link_nodes = { &qnm_cnoc2_cnoc3, NULL },
};
static struct qcom_icc_node qns_mnoc_cfg = {
.name = "qns_mnoc_cfg",
- .id = SC7280_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qnm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
- .id = SC7280_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_MASTER_SNOC_CFG },
+ .link_nodes = { &qnm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SC7280_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SC7280_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc3_cnoc2 = {
.name = "qns_cnoc3_cnoc2",
- .id = SC7280_SLAVE_CNOC3_CNOC2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7280_MASTER_CNOC3_CNOC2 },
+ .link_nodes = { &qnm_cnoc3_cnoc2, NULL },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = SC7280_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7280_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc_datapath, NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = SC7280_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qnm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = SC7280_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SC7280_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SC7280_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SC7280_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SC7280_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SC7280_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SC7280_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SC7280_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
- .id = SC7280_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7280_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qnm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
.name = "qhs_modem_ms_mpu_cfg",
- .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SC7280_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7280_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SC7280_SLAVE_LLCC,
.channels = 2,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7280_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
- .id = SC7280_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
- .id = SC7280_SLAVE_SERVICE_GEM_NOC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
- .id = SC7280_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
- .id = SC7280_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
- .id = SC7280_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
- .id = SC7280_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
- .id = SC7280_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
- .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
- .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SC7280_SLAVE_EBI1,
.channels = 2,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SC7280_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7280_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SC7280_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7280_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SC7280_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SC7280_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7280_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
- .id = SC7280_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SC7280_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7280_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SC7280_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7280_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SC7280_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1660,6 +1585,7 @@ static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_aggre1_noc = {
+ .alloc_dyn_id = true,
.config = &sc7280_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
@@ -1692,6 +1618,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7280_aggre2_noc = {
+ .alloc_dyn_id = true,
.config = &sc7280_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
@@ -1713,6 +1640,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sc7280_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1783,6 +1711,7 @@ static const struct regmap_config sc7280_cnoc2_regmap_config = {
};
static const struct qcom_icc_desc sc7280_cnoc2 = {
+ .alloc_dyn_id = true,
.config = &sc7280_cnoc2_regmap_config,
.nodes = cnoc2_nodes,
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
@@ -1824,6 +1753,7 @@ static const struct regmap_config sc7280_cnoc3_regmap_config = {
};
static const struct qcom_icc_desc sc7280_cnoc3 = {
+ .alloc_dyn_id = true,
.config = &sc7280_cnoc3_regmap_config,
.nodes = cnoc3_nodes,
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
@@ -1849,6 +1779,7 @@ static const struct regmap_config sc7280_dc_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_dc_noc = {
+ .alloc_dyn_id = true,
.config = &sc7280_dc_noc_regmap_config,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
@@ -1894,6 +1825,7 @@ static const struct regmap_config sc7280_gem_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_gem_noc = {
+ .alloc_dyn_id = true,
.config = &sc7280_gem_noc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
@@ -1923,6 +1855,7 @@ static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.config = &sc7280_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
@@ -1949,6 +1882,7 @@ static const struct regmap_config sc7280_mc_virt_regmap_config = {
};
static const struct qcom_icc_desc sc7280_mc_virt = {
+ .alloc_dyn_id = true,
.config = &sc7280_mc_virt_regmap_config,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
@@ -1985,6 +1919,7 @@ static const struct regmap_config sc7280_mmss_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_mmss_noc = {
+ .alloc_dyn_id = true,
.config = &sc7280_mmss_noc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
@@ -2013,6 +1948,7 @@ static const struct regmap_config sc7280_nsp_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_nsp_noc = {
+ .alloc_dyn_id = true,
.config = &sc7280_nsp_noc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
@@ -2047,6 +1983,7 @@ static const struct regmap_config sc7280_system_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_system_noc = {
+ .alloc_dyn_id = true,
.config = &sc7280_system_noc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h
deleted file mode 100644
index 175e400305c513a5f0d08468da7f4c72eb1a04e6..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sc7280.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm #define SC7280 interconnect IDs
- *
- * Copyright (c) 2021, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7280_H
-#define __DRIVERS_INTERCONNECT_QCOM_SC7280_H
-
-#define SC7280_MASTER_GPU_TCU 0
-#define SC7280_MASTER_SYS_TCU 1
-#define SC7280_MASTER_APPSS_PROC 2
-#define SC7280_MASTER_LLCC 3
-#define SC7280_MASTER_CNOC_LPASS_AG_NOC 4
-#define SC7280_MASTER_CDSP_NOC_CFG 5
-#define SC7280_MASTER_QDSS_BAM 6
-#define SC7280_MASTER_QSPI_0 7
-#define SC7280_MASTER_QUP_0 8
-#define SC7280_MASTER_QUP_1 9
-#define SC7280_MASTER_A1NOC_CFG 10
-#define SC7280_MASTER_A2NOC_CFG 11
-#define SC7280_MASTER_A1NOC_SNOC 12
-#define SC7280_MASTER_A2NOC_SNOC 13
-#define SC7280_MASTER_COMPUTE_NOC 14
-#define SC7280_MASTER_CNOC2_CNOC3 15
-#define SC7280_MASTER_CNOC3_CNOC2 16
-#define SC7280_MASTER_CNOC_A2NOC 17
-#define SC7280_MASTER_CNOC_DC_NOC 18
-#define SC7280_MASTER_GEM_NOC_CFG 19
-#define SC7280_MASTER_GEM_NOC_CNOC 20
-#define SC7280_MASTER_GEM_NOC_PCIE_SNOC 21
-#define SC7280_MASTER_GFX3D 22
-#define SC7280_MASTER_CNOC_MNOC_CFG 23
-#define SC7280_MASTER_MNOC_HF_MEM_NOC 24
-#define SC7280_MASTER_MNOC_SF_MEM_NOC 25
-#define SC7280_MASTER_ANOC_PCIE_GEM_NOC 26
-#define SC7280_MASTER_SNOC_CFG 27
-#define SC7280_MASTER_SNOC_GC_MEM_NOC 28
-#define SC7280_MASTER_SNOC_SF_MEM_NOC 29
-#define SC7280_MASTER_VIDEO_P0 30
-#define SC7280_MASTER_VIDEO_PROC 31
-#define SC7280_MASTER_QUP_CORE_0 32
-#define SC7280_MASTER_QUP_CORE_1 33
-#define SC7280_MASTER_CAMNOC_HF 34
-#define SC7280_MASTER_CAMNOC_ICP 35
-#define SC7280_MASTER_CAMNOC_SF 36
-#define SC7280_MASTER_CRYPTO 37
-#define SC7280_MASTER_IPA 38
-#define SC7280_MASTER_MDP0 39
-#define SC7280_MASTER_CDSP_PROC 40
-#define SC7280_MASTER_PIMEM 41
-#define SC7280_MASTER_GIC 42
-#define SC7280_MASTER_PCIE_0 43
-#define SC7280_MASTER_PCIE_1 44
-#define SC7280_MASTER_QDSS_DAP 45
-#define SC7280_MASTER_QDSS_ETR 46
-#define SC7280_MASTER_SDCC_1 47
-#define SC7280_MASTER_SDCC_2 48
-#define SC7280_MASTER_SDCC_4 49
-#define SC7280_MASTER_UFS_MEM 50
-#define SC7280_MASTER_USB2 51
-#define SC7280_MASTER_USB3_0 52
-#define SC7280_SLAVE_EBI1 53
-#define SC7280_SLAVE_AHB2PHY_SOUTH 54
-#define SC7280_SLAVE_AHB2PHY_NORTH 55
-#define SC7280_SLAVE_AOSS 56
-#define SC7280_SLAVE_APPSS 57
-#define SC7280_SLAVE_CAMERA_CFG 58
-#define SC7280_SLAVE_CLK_CTL 59
-#define SC7280_SLAVE_CDSP_CFG 60
-#define SC7280_SLAVE_RBCPR_CX_CFG 61
-#define SC7280_SLAVE_RBCPR_MX_CFG 62
-#define SC7280_SLAVE_CRYPTO_0_CFG 63
-#define SC7280_SLAVE_CX_RDPM 64
-#define SC7280_SLAVE_DCC_CFG 65
-#define SC7280_SLAVE_DISPLAY_CFG 66
-#define SC7280_SLAVE_GFX3D_CFG 67
-#define SC7280_SLAVE_HWKM 68
-#define SC7280_SLAVE_IMEM_CFG 69
-#define SC7280_SLAVE_IPA_CFG 70
-#define SC7280_SLAVE_IPC_ROUTER_CFG 71
-#define SC7280_SLAVE_LLCC_CFG 72
-#define SC7280_SLAVE_LPASS 73
-#define SC7280_SLAVE_LPASS_CORE_CFG 74
-#define SC7280_SLAVE_LPASS_LPI_CFG 75
-#define SC7280_SLAVE_LPASS_MPU_CFG 76
-#define SC7280_SLAVE_LPASS_TOP_CFG 77
-#define SC7280_SLAVE_MSS_PROC_MS_MPU_CFG 78
-#define SC7280_SLAVE_MCDMA_MS_MPU_CFG 79
-#define SC7280_SLAVE_CNOC_MSS 80
-#define SC7280_SLAVE_MX_RDPM 81
-#define SC7280_SLAVE_PCIE_0_CFG 82
-#define SC7280_SLAVE_PCIE_1_CFG 83
-#define SC7280_SLAVE_PDM 84
-#define SC7280_SLAVE_PIMEM_CFG 85
-#define SC7280_SLAVE_PKA_WRAPPER_CFG 86
-#define SC7280_SLAVE_PMU_WRAPPER_CFG 87
-#define SC7280_SLAVE_QDSS_CFG 88
-#define SC7280_SLAVE_QSPI_0 89
-#define SC7280_SLAVE_QUP_0 90
-#define SC7280_SLAVE_QUP_1 91
-#define SC7280_SLAVE_SDCC_1 92
-#define SC7280_SLAVE_SDCC_2 93
-#define SC7280_SLAVE_SDCC_4 94
-#define SC7280_SLAVE_SECURITY 95
-#define SC7280_SLAVE_TCSR 96
-#define SC7280_SLAVE_TLMM 97
-#define SC7280_SLAVE_UFS_MEM_CFG 98
-#define SC7280_SLAVE_USB2 99
-#define SC7280_SLAVE_USB3_0 100
-#define SC7280_SLAVE_VENUS_CFG 101
-#define SC7280_SLAVE_VSENSE_CTRL_CFG 102
-#define SC7280_SLAVE_A1NOC_CFG 103
-#define SC7280_SLAVE_A1NOC_SNOC 104
-#define SC7280_SLAVE_A2NOC_CFG 105
-#define SC7280_SLAVE_A2NOC_SNOC 106
-#define SC7280_SLAVE_CNOC2_CNOC3 107
-#define SC7280_SLAVE_CNOC3_CNOC2 108
-#define SC7280_SLAVE_CNOC_A2NOC 109
-#define SC7280_SLAVE_DDRSS_CFG 110
-#define SC7280_SLAVE_GEM_NOC_CNOC 111
-#define SC7280_SLAVE_GEM_NOC_CFG 112
-#define SC7280_SLAVE_SNOC_GEM_NOC_GC 113
-#define SC7280_SLAVE_SNOC_GEM_NOC_SF 114
-#define SC7280_SLAVE_LLCC 115
-#define SC7280_SLAVE_MNOC_HF_MEM_NOC 116
-#define SC7280_SLAVE_MNOC_SF_MEM_NOC 117
-#define SC7280_SLAVE_CNOC_MNOC_CFG 118
-#define SC7280_SLAVE_CDSP_MEM_NOC 119
-#define SC7280_SLAVE_MEM_NOC_PCIE_SNOC 120
-#define SC7280_SLAVE_ANOC_PCIE_GEM_NOC 121
-#define SC7280_SLAVE_SNOC_CFG 122
-#define SC7280_SLAVE_QUP_CORE_0 123
-#define SC7280_SLAVE_QUP_CORE_1 124
-#define SC7280_SLAVE_BOOT_IMEM 125
-#define SC7280_SLAVE_IMEM 126
-#define SC7280_SLAVE_PIMEM 127
-#define SC7280_SLAVE_SERVICE_NSP_NOC 128
-#define SC7280_SLAVE_SERVICE_A1NOC 129
-#define SC7280_SLAVE_SERVICE_A2NOC 130
-#define SC7280_SLAVE_SERVICE_GEM_NOC_1 131
-#define SC7280_SLAVE_SERVICE_MNOC 132
-#define SC7280_SLAVE_SERVICES_LPASS_AML_NOC 133
-#define SC7280_SLAVE_SERVICE_LPASS_AG_NOC 134
-#define SC7280_SLAVE_SERVICE_GEM_NOC_2 135
-#define SC7280_SLAVE_SERVICE_SNOC 136
-#define SC7280_SLAVE_SERVICE_GEM_NOC 137
-#define SC7280_SLAVE_PCIE_0 138
-#define SC7280_SLAVE_PCIE_1 139
-#define SC7280_SLAVE_QDSS_STM 140
-#define SC7280_SLAVE_TCU 141
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 06/28] interconnect: qcom: sc8180x: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (4 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 05/28] interconnect: qcom: sc7280: convert to dynamic IDs Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 07/28] interconnect: qcom: sc8280xp: " Dmitry Baryshkov
` (22 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sc8180x.c | 961 ++++++++++++++++++------------------
drivers/interconnect/qcom/sc8180x.h | 179 -------
2 files changed, 483 insertions(+), 657 deletions(-)
diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c
index 0640ee55220d54fc977dc98f65644ecf7f50508f..e68bc35b691276375349585ac03b279e30568c68 100644
--- a/drivers/interconnect/qcom/sc8180x.c
+++ b/drivers/interconnect/qcom/sc8180x.c
@@ -14,1333 +14,1327 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sc8180x.h"
+
+static struct qcom_icc_node mas_qhm_a1noc_cfg;
+static struct qcom_icc_node mas_xm_ufs_card;
+static struct qcom_icc_node mas_xm_ufs_g4;
+static struct qcom_icc_node mas_xm_ufs_mem;
+static struct qcom_icc_node mas_xm_usb3_0;
+static struct qcom_icc_node mas_xm_usb3_1;
+static struct qcom_icc_node mas_xm_usb3_2;
+static struct qcom_icc_node mas_qhm_a2noc_cfg;
+static struct qcom_icc_node mas_qhm_qdss_bam;
+static struct qcom_icc_node mas_qhm_qspi;
+static struct qcom_icc_node mas_qhm_qspi1;
+static struct qcom_icc_node mas_qhm_qup0;
+static struct qcom_icc_node mas_qhm_qup1;
+static struct qcom_icc_node mas_qhm_qup2;
+static struct qcom_icc_node mas_qhm_sensorss_ahb;
+static struct qcom_icc_node mas_qxm_crypto;
+static struct qcom_icc_node mas_qxm_ipa;
+static struct qcom_icc_node mas_xm_emac;
+static struct qcom_icc_node mas_xm_pcie3_0;
+static struct qcom_icc_node mas_xm_pcie3_1;
+static struct qcom_icc_node mas_xm_pcie3_2;
+static struct qcom_icc_node mas_xm_pcie3_3;
+static struct qcom_icc_node mas_xm_qdss_etr;
+static struct qcom_icc_node mas_xm_sdc2;
+static struct qcom_icc_node mas_xm_sdc4;
+static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp;
+static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node mas_qnm_npu;
+static struct qcom_icc_node mas_qnm_snoc;
+static struct qcom_icc_node mas_qhm_cnoc_dc_noc;
+static struct qcom_icc_node mas_acm_apps;
+static struct qcom_icc_node mas_acm_gpu_tcu;
+static struct qcom_icc_node mas_acm_sys_tcu;
+static struct qcom_icc_node mas_qhm_gemnoc_cfg;
+static struct qcom_icc_node mas_qnm_cmpnoc;
+static struct qcom_icc_node mas_qnm_gpu;
+static struct qcom_icc_node mas_qnm_mnoc_hf;
+static struct qcom_icc_node mas_qnm_mnoc_sf;
+static struct qcom_icc_node mas_qnm_pcie;
+static struct qcom_icc_node mas_qnm_snoc_gc;
+static struct qcom_icc_node mas_qnm_snoc_sf;
+static struct qcom_icc_node mas_qxm_ecc;
+static struct qcom_icc_node mas_llcc_mc;
+static struct qcom_icc_node mas_qhm_mnoc_cfg;
+static struct qcom_icc_node mas_qxm_camnoc_hf0;
+static struct qcom_icc_node mas_qxm_camnoc_hf1;
+static struct qcom_icc_node mas_qxm_camnoc_sf;
+static struct qcom_icc_node mas_qxm_mdp0;
+static struct qcom_icc_node mas_qxm_mdp1;
+static struct qcom_icc_node mas_qxm_rot;
+static struct qcom_icc_node mas_qxm_venus0;
+static struct qcom_icc_node mas_qxm_venus1;
+static struct qcom_icc_node mas_qxm_venus_arm9;
+static struct qcom_icc_node mas_qhm_snoc_cfg;
+static struct qcom_icc_node mas_qnm_aggre1_noc;
+static struct qcom_icc_node mas_qnm_aggre2_noc;
+static struct qcom_icc_node mas_qnm_gemnoc;
+static struct qcom_icc_node mas_qxm_pimem;
+static struct qcom_icc_node mas_xm_gic;
+static struct qcom_icc_node mas_qup_core_0;
+static struct qcom_icc_node mas_qup_core_1;
+static struct qcom_icc_node mas_qup_core_2;
+static struct qcom_icc_node slv_qns_a1noc_snoc;
+static struct qcom_icc_node slv_srvc_aggre1_noc;
+static struct qcom_icc_node slv_qns_a2noc_snoc;
+static struct qcom_icc_node slv_qns_pcie_mem_noc;
+static struct qcom_icc_node slv_srvc_aggre2_noc;
+static struct qcom_icc_node slv_qns_camnoc_uncomp;
+static struct qcom_icc_node slv_qns_cdsp_mem_noc;
+static struct qcom_icc_node slv_qhs_a1_noc_cfg;
+static struct qcom_icc_node slv_qhs_a2_noc_cfg;
+static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center;
+static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east;
+static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west;
+static struct qcom_icc_node slv_qhs_ahb2phy_south;
+static struct qcom_icc_node slv_qhs_aop;
+static struct qcom_icc_node slv_qhs_aoss;
+static struct qcom_icc_node slv_qhs_camera_cfg;
+static struct qcom_icc_node slv_qhs_clk_ctl;
+static struct qcom_icc_node slv_qhs_compute_dsp;
+static struct qcom_icc_node slv_qhs_cpr_cx;
+static struct qcom_icc_node slv_qhs_cpr_mmcx;
+static struct qcom_icc_node slv_qhs_cpr_mx;
+static struct qcom_icc_node slv_qhs_crypto0_cfg;
+static struct qcom_icc_node slv_qhs_ddrss_cfg;
+static struct qcom_icc_node slv_qhs_display_cfg;
+static struct qcom_icc_node slv_qhs_emac_cfg;
+static struct qcom_icc_node slv_qhs_glm;
+static struct qcom_icc_node slv_qhs_gpuss_cfg;
+static struct qcom_icc_node slv_qhs_imem_cfg;
+static struct qcom_icc_node slv_qhs_ipa;
+static struct qcom_icc_node slv_qhs_mnoc_cfg;
+static struct qcom_icc_node slv_qhs_npu_cfg;
+static struct qcom_icc_node slv_qhs_pcie0_cfg;
+static struct qcom_icc_node slv_qhs_pcie1_cfg;
+static struct qcom_icc_node slv_qhs_pcie2_cfg;
+static struct qcom_icc_node slv_qhs_pcie3_cfg;
+static struct qcom_icc_node slv_qhs_pdm;
+static struct qcom_icc_node slv_qhs_pimem_cfg;
+static struct qcom_icc_node slv_qhs_prng;
+static struct qcom_icc_node slv_qhs_qdss_cfg;
+static struct qcom_icc_node slv_qhs_qspi_0;
+static struct qcom_icc_node slv_qhs_qspi_1;
+static struct qcom_icc_node slv_qhs_qupv3_east0;
+static struct qcom_icc_node slv_qhs_qupv3_east1;
+static struct qcom_icc_node slv_qhs_qupv3_west;
+static struct qcom_icc_node slv_qhs_sdc2;
+static struct qcom_icc_node slv_qhs_sdc4;
+static struct qcom_icc_node slv_qhs_security;
+static struct qcom_icc_node slv_qhs_snoc_cfg;
+static struct qcom_icc_node slv_qhs_spss_cfg;
+static struct qcom_icc_node slv_qhs_tcsr;
+static struct qcom_icc_node slv_qhs_tlmm_east;
+static struct qcom_icc_node slv_qhs_tlmm_south;
+static struct qcom_icc_node slv_qhs_tlmm_west;
+static struct qcom_icc_node slv_qhs_tsif;
+static struct qcom_icc_node slv_qhs_ufs_card_cfg;
+static struct qcom_icc_node slv_qhs_ufs_mem0_cfg;
+static struct qcom_icc_node slv_qhs_ufs_mem1_cfg;
+static struct qcom_icc_node slv_qhs_usb3_0;
+static struct qcom_icc_node slv_qhs_usb3_1;
+static struct qcom_icc_node slv_qhs_usb3_2;
+static struct qcom_icc_node slv_qhs_venus_cfg;
+static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node slv_srvc_cnoc;
+static struct qcom_icc_node slv_qhs_gemnoc;
+static struct qcom_icc_node slv_qhs_llcc;
+static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node slv_qns_ecc;
+static struct qcom_icc_node slv_qns_gem_noc_snoc;
+static struct qcom_icc_node slv_qns_llcc;
+static struct qcom_icc_node slv_srvc_gemnoc;
+static struct qcom_icc_node slv_srvc_gemnoc1;
+static struct qcom_icc_node slv_ebi;
+static struct qcom_icc_node slv_qns2_mem_noc;
+static struct qcom_icc_node slv_qns_mem_noc_hf;
+static struct qcom_icc_node slv_srvc_mnoc;
+static struct qcom_icc_node slv_qhs_apss;
+static struct qcom_icc_node slv_qns_cnoc;
+static struct qcom_icc_node slv_qns_gemnoc_gc;
+static struct qcom_icc_node slv_qns_gemnoc_sf;
+static struct qcom_icc_node slv_qxs_imem;
+static struct qcom_icc_node slv_qxs_pimem;
+static struct qcom_icc_node slv_srvc_snoc;
+static struct qcom_icc_node slv_xs_pcie_0;
+static struct qcom_icc_node slv_xs_pcie_1;
+static struct qcom_icc_node slv_xs_pcie_2;
+static struct qcom_icc_node slv_xs_pcie_3;
+static struct qcom_icc_node slv_xs_qdss_stm;
+static struct qcom_icc_node slv_xs_sys_tcu_cfg;
+static struct qcom_icc_node slv_qup_core_0;
+static struct qcom_icc_node slv_qup_core_1;
+static struct qcom_icc_node slv_qup_core_2;
static struct qcom_icc_node mas_qhm_a1noc_cfg = {
.name = "mas_qhm_a1noc_cfg",
- .id = SC8180X_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_SLAVE_SERVICE_A1NOC }
+ .link_nodes = { &slv_srvc_aggre1_noc, NULL }
};
static struct qcom_icc_node mas_xm_ufs_card = {
.name = "mas_xm_ufs_card",
- .id = SC8180X_MASTER_UFS_CARD,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A1NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a1noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_ufs_g4 = {
.name = "mas_xm_ufs_g4",
- .id = SC8180X_MASTER_UFS_GEN4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A1NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a1noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_ufs_mem = {
.name = "mas_xm_ufs_mem",
- .id = SC8180X_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A1NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a1noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_usb3_0 = {
.name = "mas_xm_usb3_0",
- .id = SC8180X_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A1NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a1noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_usb3_1 = {
.name = "mas_xm_usb3_1",
- .id = SC8180X_MASTER_USB3_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A1NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a1noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_usb3_2 = {
.name = "mas_xm_usb3_2",
- .id = SC8180X_MASTER_USB3_2,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8180X_A1NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a1noc_snoc, NULL }
};
static struct qcom_icc_node mas_qhm_a2noc_cfg = {
.name = "mas_qhm_a2noc_cfg",
- .id = SC8180X_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_SLAVE_SERVICE_A2NOC }
+ .link_nodes = { &slv_srvc_aggre2_noc, NULL }
};
static struct qcom_icc_node mas_qhm_qdss_bam = {
.name = "mas_qhm_qdss_bam",
- .id = SC8180X_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qhm_qspi = {
.name = "mas_qhm_qspi",
- .id = SC8180X_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qhm_qspi1 = {
.name = "mas_qhm_qspi1",
- .id = SC8180X_MASTER_QSPI_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qhm_qup0 = {
.name = "mas_qhm_qup0",
- .id = SC8180X_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qhm_qup1 = {
.name = "mas_qhm_qup1",
- .id = SC8180X_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qhm_qup2 = {
.name = "mas_qhm_qup2",
- .id = SC8180X_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qhm_sensorss_ahb = {
.name = "mas_qhm_sensorss_ahb",
- .id = SC8180X_MASTER_SENSORS_AHB,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qxm_crypto = {
.name = "mas_qxm_crypto",
- .id = SC8180X_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qxm_ipa = {
.name = "mas_qxm_ipa",
- .id = SC8180X_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_emac = {
.name = "mas_xm_emac",
- .id = SC8180X_MASTER_EMAC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_pcie3_0 = {
.name = "mas_xm_pcie3_0",
- .id = SC8180X_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
+ .link_nodes = { &slv_qns_pcie_mem_noc, NULL }
};
static struct qcom_icc_node mas_xm_pcie3_1 = {
.name = "mas_xm_pcie3_1",
- .id = SC8180X_MASTER_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
+ .link_nodes = { &slv_qns_pcie_mem_noc, NULL }
};
static struct qcom_icc_node mas_xm_pcie3_2 = {
.name = "mas_xm_pcie3_2",
- .id = SC8180X_MASTER_PCIE_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
+ .link_nodes = { &slv_qns_pcie_mem_noc, NULL }
};
static struct qcom_icc_node mas_xm_pcie3_3 = {
.name = "mas_xm_pcie3_3",
- .id = SC8180X_MASTER_PCIE_3,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
+ .link_nodes = { &slv_qns_pcie_mem_noc, NULL }
};
static struct qcom_icc_node mas_xm_qdss_etr = {
.name = "mas_xm_qdss_etr",
- .id = SC8180X_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_sdc2 = {
.name = "mas_xm_sdc2",
- .id = SC8180X_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_xm_sdc4 = {
.name = "mas_xm_sdc4",
- .id = SC8180X_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_SLV }
+ .link_nodes = { &slv_qns_a2noc_snoc, NULL }
};
static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = {
.name = "mas_qxm_camnoc_hf0_uncomp",
- .id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
+ .link_nodes = { &slv_qns_camnoc_uncomp, NULL }
};
static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = {
.name = "mas_qxm_camnoc_hf1_uncomp",
- .id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
+ .link_nodes = { &slv_qns_camnoc_uncomp, NULL }
};
static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = {
.name = "mas_qxm_camnoc_sf_uncomp",
- .id = SC8180X_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
+ .link_nodes = { &slv_qns_camnoc_uncomp, NULL }
};
static struct qcom_icc_node mas_qnm_npu = {
.name = "mas_qnm_npu",
- .id = SC8180X_MASTER_NPU,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_CDSP_MEM_NOC }
+ .link_nodes = { &slv_qns_cdsp_mem_noc, NULL }
};
static struct qcom_icc_node mas_qnm_snoc = {
.name = "mas_qnm_snoc",
- .id = SC8180X_SNOC_CNOC_MAS,
.channels = 1,
.buswidth = 8,
- .num_links = 56,
- .links = { SC8180X_SLAVE_TLMM_SOUTH,
- SC8180X_SLAVE_CDSP_CFG,
- SC8180X_SLAVE_SPSS_CFG,
- SC8180X_SLAVE_CAMERA_CFG,
- SC8180X_SLAVE_SDCC_4,
- SC8180X_SLAVE_AHB2PHY_CENTER,
- SC8180X_SLAVE_SDCC_2,
- SC8180X_SLAVE_PCIE_2_CFG,
- SC8180X_SLAVE_CNOC_MNOC_CFG,
- SC8180X_SLAVE_EMAC_CFG,
- SC8180X_SLAVE_QSPI_0,
- SC8180X_SLAVE_QSPI_1,
- SC8180X_SLAVE_TLMM_EAST,
- SC8180X_SLAVE_SNOC_CFG,
- SC8180X_SLAVE_AHB2PHY_EAST,
- SC8180X_SLAVE_GLM,
- SC8180X_SLAVE_PDM,
- SC8180X_SLAVE_PCIE_1_CFG,
- SC8180X_SLAVE_A2NOC_CFG,
- SC8180X_SLAVE_QDSS_CFG,
- SC8180X_SLAVE_DISPLAY_CFG,
- SC8180X_SLAVE_TCSR,
- SC8180X_SLAVE_UFS_MEM_0_CFG,
- SC8180X_SLAVE_CNOC_DDRSS,
- SC8180X_SLAVE_PCIE_0_CFG,
- SC8180X_SLAVE_QUP_1,
- SC8180X_SLAVE_QUP_2,
- SC8180X_SLAVE_NPU_CFG,
- SC8180X_SLAVE_CRYPTO_0_CFG,
- SC8180X_SLAVE_GRAPHICS_3D_CFG,
- SC8180X_SLAVE_VENUS_CFG,
- SC8180X_SLAVE_TSIF,
- SC8180X_SLAVE_IPA_CFG,
- SC8180X_SLAVE_CLK_CTL,
- SC8180X_SLAVE_SECURITY,
- SC8180X_SLAVE_AOP,
- SC8180X_SLAVE_AHB2PHY_WEST,
- SC8180X_SLAVE_AHB2PHY_SOUTH,
- SC8180X_SLAVE_SERVICE_CNOC,
- SC8180X_SLAVE_UFS_CARD_CFG,
- SC8180X_SLAVE_USB3_1,
- SC8180X_SLAVE_USB3_2,
- SC8180X_SLAVE_PCIE_3_CFG,
- SC8180X_SLAVE_RBCPR_CX_CFG,
- SC8180X_SLAVE_TLMM_WEST,
- SC8180X_SLAVE_A1NOC_CFG,
- SC8180X_SLAVE_AOSS,
- SC8180X_SLAVE_PRNG,
- SC8180X_SLAVE_VSENSE_CTRL_CFG,
- SC8180X_SLAVE_QUP_0,
- SC8180X_SLAVE_USB3,
- SC8180X_SLAVE_RBCPR_MMCX_CFG,
- SC8180X_SLAVE_PIMEM_CFG,
- SC8180X_SLAVE_UFS_MEM_1_CFG,
- SC8180X_SLAVE_RBCPR_MX_CFG,
- SC8180X_SLAVE_IMEM_CFG }
+ .link_nodes = { &slv_qhs_tlmm_south,
+ &slv_qhs_compute_dsp,
+ &slv_qhs_spss_cfg,
+ &slv_qhs_camera_cfg,
+ &slv_qhs_sdc4,
+ &slv_qhs_ahb2phy_refgen_center,
+ &slv_qhs_sdc2,
+ &slv_qhs_pcie2_cfg,
+ &slv_qhs_mnoc_cfg,
+ &slv_qhs_emac_cfg,
+ &slv_qhs_qspi_0,
+ &slv_qhs_qspi_1,
+ &slv_qhs_tlmm_east,
+ &slv_qhs_snoc_cfg,
+ &slv_qhs_ahb2phy_refgen_east,
+ &slv_qhs_glm,
+ &slv_qhs_pdm,
+ &slv_qhs_pcie1_cfg,
+ &slv_qhs_a2_noc_cfg,
+ &slv_qhs_qdss_cfg,
+ &slv_qhs_display_cfg,
+ &slv_qhs_tcsr,
+ &slv_qhs_ufs_mem0_cfg,
+ &slv_qhs_ddrss_cfg,
+ &slv_qhs_pcie0_cfg,
+ &slv_qhs_qupv3_east0,
+ &slv_qhs_qupv3_east1,
+ &slv_qhs_npu_cfg,
+ &slv_qhs_crypto0_cfg,
+ &slv_qhs_gpuss_cfg,
+ &slv_qhs_venus_cfg,
+ &slv_qhs_tsif,
+ &slv_qhs_ipa,
+ &slv_qhs_clk_ctl,
+ &slv_qhs_security,
+ &slv_qhs_aop,
+ &slv_qhs_ahb2phy_refgen_west,
+ &slv_qhs_ahb2phy_south,
+ &slv_srvc_cnoc,
+ &slv_qhs_ufs_card_cfg,
+ &slv_qhs_usb3_1,
+ &slv_qhs_usb3_2,
+ &slv_qhs_pcie3_cfg,
+ &slv_qhs_cpr_cx,
+ &slv_qhs_tlmm_west,
+ &slv_qhs_a1_noc_cfg,
+ &slv_qhs_aoss,
+ &slv_qhs_prng,
+ &slv_qhs_vsense_ctrl_cfg,
+ &slv_qhs_qupv3_west,
+ &slv_qhs_usb3_0,
+ &slv_qhs_cpr_mmcx,
+ &slv_qhs_pimem_cfg,
+ &slv_qhs_ufs_mem1_cfg,
+ &slv_qhs_cpr_mx,
+ &slv_qhs_imem_cfg, NULL }
};
static struct qcom_icc_node mas_qhm_cnoc_dc_noc = {
.name = "mas_qhm_cnoc_dc_noc",
- .id = SC8180X_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SC8180X_SLAVE_LLCC_CFG,
- SC8180X_SLAVE_GEM_NOC_CFG }
+ .link_nodes = { &slv_qhs_llcc,
+ &slv_qhs_gemnoc, NULL }
};
static struct qcom_icc_node mas_acm_apps = {
.name = "mas_acm_apps",
- .id = SC8180X_MASTER_AMPSS_M0,
.channels = 4,
.buswidth = 64,
- .num_links = 3,
- .links = { SC8180X_SLAVE_ECC,
- SC8180X_SLAVE_LLCC,
- SC8180X_SLAVE_GEM_NOC_SNOC }
+ .link_nodes = { &slv_qns_ecc,
+ &slv_qns_llcc,
+ &slv_qns_gem_noc_snoc, NULL }
};
static struct qcom_icc_node mas_acm_gpu_tcu = {
.name = "mas_acm_gpu_tcu",
- .id = SC8180X_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC8180X_SLAVE_LLCC,
- SC8180X_SLAVE_GEM_NOC_SNOC }
+ .link_nodes = { &slv_qns_llcc,
+ &slv_qns_gem_noc_snoc, NULL }
};
static struct qcom_icc_node mas_acm_sys_tcu = {
.name = "mas_acm_sys_tcu",
- .id = SC8180X_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC8180X_SLAVE_LLCC,
- SC8180X_SLAVE_GEM_NOC_SNOC }
+ .link_nodes = { &slv_qns_llcc,
+ &slv_qns_gem_noc_snoc, NULL }
};
static struct qcom_icc_node mas_qhm_gemnoc_cfg = {
.name = "mas_qhm_gemnoc_cfg",
- .id = SC8180X_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 3,
- .links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1,
- SC8180X_SLAVE_SERVICE_GEM_NOC,
- SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG }
+ .link_nodes = { &slv_srvc_gemnoc1,
+ &slv_srvc_gemnoc,
+ &slv_qhs_mdsp_ms_mpu_cfg, NULL }
};
static struct qcom_icc_node mas_qnm_cmpnoc = {
.name = "mas_qnm_cmpnoc",
- .id = SC8180X_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SC8180X_SLAVE_ECC,
- SC8180X_SLAVE_LLCC,
- SC8180X_SLAVE_GEM_NOC_SNOC }
+ .link_nodes = { &slv_qns_ecc,
+ &slv_qns_llcc,
+ &slv_qns_gem_noc_snoc, NULL }
};
static struct qcom_icc_node mas_qnm_gpu = {
.name = "mas_qnm_gpu",
- .id = SC8180X_MASTER_GRAPHICS_3D,
.channels = 4,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8180X_SLAVE_LLCC,
- SC8180X_SLAVE_GEM_NOC_SNOC }
+ .link_nodes = { &slv_qns_llcc,
+ &slv_qns_gem_noc_snoc, NULL }
};
static struct qcom_icc_node mas_qnm_mnoc_hf = {
.name = "mas_qnm_mnoc_hf",
- .id = SC8180X_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_LLCC }
+ .link_nodes = { &slv_qns_llcc, NULL }
};
static struct qcom_icc_node mas_qnm_mnoc_sf = {
.name = "mas_qnm_mnoc_sf",
- .id = SC8180X_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8180X_SLAVE_LLCC,
- SC8180X_SLAVE_GEM_NOC_SNOC }
+ .link_nodes = { &slv_qns_llcc,
+ &slv_qns_gem_noc_snoc, NULL }
};
static struct qcom_icc_node mas_qnm_pcie = {
.name = "mas_qnm_pcie",
- .id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8180X_SLAVE_LLCC,
- SC8180X_SLAVE_GEM_NOC_SNOC }
+ .link_nodes = { &slv_qns_llcc,
+ &slv_qns_gem_noc_snoc, NULL }
};
static struct qcom_icc_node mas_qnm_snoc_gc = {
.name = "mas_qnm_snoc_gc",
- .id = SC8180X_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_SLAVE_LLCC }
+ .link_nodes = { &slv_qns_llcc, NULL }
};
static struct qcom_icc_node mas_qnm_snoc_sf = {
.name = "mas_qnm_snoc_sf",
- .id = SC8180X_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_LLCC }
+ .link_nodes = { &slv_qns_llcc, NULL }
};
static struct qcom_icc_node mas_qxm_ecc = {
.name = "mas_qxm_ecc",
- .id = SC8180X_MASTER_ECC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_LLCC }
+ .link_nodes = { &slv_qns_llcc, NULL }
};
static struct qcom_icc_node mas_llcc_mc = {
.name = "mas_llcc_mc",
- .id = SC8180X_MASTER_LLCC,
.channels = 8,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_SLAVE_EBI_CH0 }
+ .link_nodes = { &slv_ebi, NULL }
};
static struct qcom_icc_node mas_qhm_mnoc_cfg = {
.name = "mas_qhm_mnoc_cfg",
- .id = SC8180X_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_SLAVE_SERVICE_MNOC }
+ .link_nodes = { &slv_srvc_mnoc, NULL }
};
static struct qcom_icc_node mas_qxm_camnoc_hf0 = {
.name = "mas_qxm_camnoc_hf0",
- .id = SC8180X_MASTER_CAMNOC_HF0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
+ .link_nodes = { &slv_qns_mem_noc_hf, NULL }
};
static struct qcom_icc_node mas_qxm_camnoc_hf1 = {
.name = "mas_qxm_camnoc_hf1",
- .id = SC8180X_MASTER_CAMNOC_HF1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
+ .link_nodes = { &slv_qns_mem_noc_hf, NULL }
};
static struct qcom_icc_node mas_qxm_camnoc_sf = {
.name = "mas_qxm_camnoc_sf",
- .id = SC8180X_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
+ .link_nodes = { &slv_qns2_mem_noc, NULL }
};
static struct qcom_icc_node mas_qxm_mdp0 = {
.name = "mas_qxm_mdp0",
- .id = SC8180X_MASTER_MDP_PORT0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
+ .link_nodes = { &slv_qns_mem_noc_hf, NULL }
};
static struct qcom_icc_node mas_qxm_mdp1 = {
.name = "mas_qxm_mdp1",
- .id = SC8180X_MASTER_MDP_PORT1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
+ .link_nodes = { &slv_qns_mem_noc_hf, NULL }
};
static struct qcom_icc_node mas_qxm_rot = {
.name = "mas_qxm_rot",
- .id = SC8180X_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
+ .link_nodes = { &slv_qns2_mem_noc, NULL }
};
static struct qcom_icc_node mas_qxm_venus0 = {
.name = "mas_qxm_venus0",
- .id = SC8180X_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
+ .link_nodes = { &slv_qns2_mem_noc, NULL }
};
static struct qcom_icc_node mas_qxm_venus1 = {
.name = "mas_qxm_venus1",
- .id = SC8180X_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
+ .link_nodes = { &slv_qns2_mem_noc, NULL }
};
static struct qcom_icc_node mas_qxm_venus_arm9 = {
.name = "mas_qxm_venus_arm9",
- .id = SC8180X_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
+ .link_nodes = { &slv_qns2_mem_noc, NULL }
};
static struct qcom_icc_node mas_qhm_snoc_cfg = {
.name = "mas_qhm_snoc_cfg",
- .id = SC8180X_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_SLAVE_SERVICE_SNOC }
+ .link_nodes = { &slv_srvc_snoc, NULL }
};
static struct qcom_icc_node mas_qnm_aggre1_noc = {
.name = "mas_qnm_aggre1_noc",
- .id = SC8180X_A1NOC_SNOC_MAS,
.channels = 1,
.buswidth = 32,
- .num_links = 6,
- .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF,
- SC8180X_SLAVE_PIMEM,
- SC8180X_SLAVE_OCIMEM,
- SC8180X_SLAVE_APPSS,
- SC8180X_SNOC_CNOC_SLV,
- SC8180X_SLAVE_QDSS_STM }
+ .link_nodes = { &slv_qns_gemnoc_sf,
+ &slv_qxs_pimem,
+ &slv_qxs_imem,
+ &slv_qhs_apss,
+ &slv_qns_cnoc,
+ &slv_xs_qdss_stm, NULL }
};
static struct qcom_icc_node mas_qnm_aggre2_noc = {
.name = "mas_qnm_aggre2_noc",
- .id = SC8180X_A2NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 11,
- .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF,
- SC8180X_SLAVE_PIMEM,
- SC8180X_SLAVE_PCIE_3,
- SC8180X_SLAVE_OCIMEM,
- SC8180X_SLAVE_APPSS,
- SC8180X_SLAVE_PCIE_2,
- SC8180X_SNOC_CNOC_SLV,
- SC8180X_SLAVE_PCIE_0,
- SC8180X_SLAVE_PCIE_1,
- SC8180X_SLAVE_TCU,
- SC8180X_SLAVE_QDSS_STM }
+ .link_nodes = { &slv_qns_gemnoc_sf,
+ &slv_qxs_pimem,
+ &slv_xs_pcie_3,
+ &slv_qxs_imem,
+ &slv_qhs_apss,
+ &slv_xs_pcie_2,
+ &slv_qns_cnoc,
+ &slv_xs_pcie_0,
+ &slv_xs_pcie_1,
+ &slv_xs_sys_tcu_cfg,
+ &slv_xs_qdss_stm, NULL }
};
static struct qcom_icc_node mas_qnm_gemnoc = {
.name = "mas_qnm_gemnoc",
- .id = SC8180X_MASTER_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 6,
- .links = { SC8180X_SLAVE_PIMEM,
- SC8180X_SLAVE_OCIMEM,
- SC8180X_SLAVE_APPSS,
- SC8180X_SNOC_CNOC_SLV,
- SC8180X_SLAVE_TCU,
- SC8180X_SLAVE_QDSS_STM }
+ .link_nodes = { &slv_qxs_pimem,
+ &slv_qxs_imem,
+ &slv_qhs_apss,
+ &slv_qns_cnoc,
+ &slv_xs_sys_tcu_cfg,
+ &slv_xs_qdss_stm, NULL }
};
static struct qcom_icc_node mas_qxm_pimem = {
.name = "mas_qxm_pimem",
- .id = SC8180X_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC,
- SC8180X_SLAVE_OCIMEM }
+ .link_nodes = { &slv_qns_gemnoc_gc,
+ &slv_qxs_imem, NULL }
};
static struct qcom_icc_node mas_xm_gic = {
.name = "mas_xm_gic",
- .id = SC8180X_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC,
- SC8180X_SLAVE_OCIMEM }
+ .link_nodes = { &slv_qns_gemnoc_gc,
+ &slv_qxs_imem, NULL }
};
static struct qcom_icc_node mas_qup_core_0 = {
.name = "mas_qup_core_0",
- .id = SC8180X_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_SLAVE_QUP_CORE_0 }
+ .link_nodes = { &slv_qup_core_0, NULL }
};
static struct qcom_icc_node mas_qup_core_1 = {
.name = "mas_qup_core_1",
- .id = SC8180X_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_SLAVE_QUP_CORE_1 }
+ .link_nodes = { &slv_qup_core_1, NULL }
};
static struct qcom_icc_node mas_qup_core_2 = {
.name = "mas_qup_core_2",
- .id = SC8180X_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_SLAVE_QUP_CORE_2 }
+ .link_nodes = { &slv_qup_core_2, NULL }
};
static struct qcom_icc_node slv_qns_a1noc_snoc = {
.name = "slv_qns_a1noc_snoc",
- .id = SC8180X_A1NOC_SNOC_SLV,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_A1NOC_SNOC_MAS }
+ .link_nodes = { &mas_qnm_aggre1_noc, NULL }
};
static struct qcom_icc_node slv_srvc_aggre1_noc = {
.name = "slv_srvc_aggre1_noc",
- .id = SC8180X_SLAVE_SERVICE_A1NOC,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qns_a2noc_snoc = {
.name = "slv_qns_a2noc_snoc",
- .id = SC8180X_A2NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8180X_A2NOC_SNOC_MAS }
+ .link_nodes = { &mas_qnm_aggre2_noc, NULL }
};
static struct qcom_icc_node slv_qns_pcie_mem_noc = {
.name = "slv_qns_pcie_mem_noc",
- .id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC }
+ .link_nodes = { &mas_qnm_pcie, NULL }
};
static struct qcom_icc_node slv_srvc_aggre2_noc = {
.name = "slv_srvc_aggre2_noc",
- .id = SC8180X_SLAVE_SERVICE_A2NOC,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qns_camnoc_uncomp = {
.name = "slv_qns_camnoc_uncomp",
- .id = SC8180X_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
- .buswidth = 32
+ .buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qns_cdsp_mem_noc = {
.name = "slv_qns_cdsp_mem_noc",
- .id = SC8180X_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_MASTER_COMPUTE_NOC }
+ .link_nodes = { &mas_qnm_cmpnoc, NULL }
};
static struct qcom_icc_node slv_qhs_a1_noc_cfg = {
.name = "slv_qhs_a1_noc_cfg",
- .id = SC8180X_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_MASTER_A1NOC_CFG }
+ .link_nodes = { &mas_qhm_a1noc_cfg, NULL }
};
static struct qcom_icc_node slv_qhs_a2_noc_cfg = {
.name = "slv_qhs_a2_noc_cfg",
- .id = SC8180X_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_MASTER_A2NOC_CFG }
+ .link_nodes = { &mas_qhm_a2noc_cfg, NULL }
};
static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = {
.name = "slv_qhs_ahb2phy_refgen_center",
- .id = SC8180X_SLAVE_AHB2PHY_CENTER,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = {
.name = "slv_qhs_ahb2phy_refgen_east",
- .id = SC8180X_SLAVE_AHB2PHY_EAST,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = {
.name = "slv_qhs_ahb2phy_refgen_west",
- .id = SC8180X_SLAVE_AHB2PHY_WEST,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_ahb2phy_south = {
.name = "slv_qhs_ahb2phy_south",
- .id = SC8180X_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_aop = {
.name = "slv_qhs_aop",
- .id = SC8180X_SLAVE_AOP,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_aoss = {
.name = "slv_qhs_aoss",
- .id = SC8180X_SLAVE_AOSS,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_camera_cfg = {
.name = "slv_qhs_camera_cfg",
- .id = SC8180X_SLAVE_CAMERA_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_clk_ctl = {
.name = "slv_qhs_clk_ctl",
- .id = SC8180X_SLAVE_CLK_CTL,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_compute_dsp = {
.name = "slv_qhs_compute_dsp",
- .id = SC8180X_SLAVE_CDSP_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_cpr_cx = {
.name = "slv_qhs_cpr_cx",
- .id = SC8180X_SLAVE_RBCPR_CX_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_cpr_mmcx = {
.name = "slv_qhs_cpr_mmcx",
- .id = SC8180X_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_cpr_mx = {
.name = "slv_qhs_cpr_mx",
- .id = SC8180X_SLAVE_RBCPR_MX_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_crypto0_cfg = {
.name = "slv_qhs_crypto0_cfg",
- .id = SC8180X_SLAVE_CRYPTO_0_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_ddrss_cfg = {
.name = "slv_qhs_ddrss_cfg",
- .id = SC8180X_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_MASTER_CNOC_DC_NOC }
+ .link_nodes = { &mas_qhm_cnoc_dc_noc, NULL }
};
static struct qcom_icc_node slv_qhs_display_cfg = {
.name = "slv_qhs_display_cfg",
- .id = SC8180X_SLAVE_DISPLAY_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_emac_cfg = {
.name = "slv_qhs_emac_cfg",
- .id = SC8180X_SLAVE_EMAC_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_glm = {
.name = "slv_qhs_glm",
- .id = SC8180X_SLAVE_GLM,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_gpuss_cfg = {
.name = "slv_qhs_gpuss_cfg",
- .id = SC8180X_SLAVE_GRAPHICS_3D_CFG,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_imem_cfg = {
.name = "slv_qhs_imem_cfg",
- .id = SC8180X_SLAVE_IMEM_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_ipa = {
.name = "slv_qhs_ipa",
- .id = SC8180X_SLAVE_IPA_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_mnoc_cfg = {
.name = "slv_qhs_mnoc_cfg",
- .id = SC8180X_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_MASTER_CNOC_MNOC_CFG }
+ .link_nodes = { &mas_qhm_mnoc_cfg, NULL }
};
static struct qcom_icc_node slv_qhs_npu_cfg = {
.name = "slv_qhs_npu_cfg",
- .id = SC8180X_SLAVE_NPU_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_pcie0_cfg = {
.name = "slv_qhs_pcie0_cfg",
- .id = SC8180X_SLAVE_PCIE_0_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_pcie1_cfg = {
.name = "slv_qhs_pcie1_cfg",
- .id = SC8180X_SLAVE_PCIE_1_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_pcie2_cfg = {
.name = "slv_qhs_pcie2_cfg",
- .id = SC8180X_SLAVE_PCIE_2_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_pcie3_cfg = {
.name = "slv_qhs_pcie3_cfg",
- .id = SC8180X_SLAVE_PCIE_3_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_pdm = {
.name = "slv_qhs_pdm",
- .id = SC8180X_SLAVE_PDM,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_pimem_cfg = {
.name = "slv_qhs_pimem_cfg",
- .id = SC8180X_SLAVE_PIMEM_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_prng = {
.name = "slv_qhs_prng",
- .id = SC8180X_SLAVE_PRNG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_qdss_cfg = {
.name = "slv_qhs_qdss_cfg",
- .id = SC8180X_SLAVE_QDSS_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_qspi_0 = {
.name = "slv_qhs_qspi_0",
- .id = SC8180X_SLAVE_QSPI_0,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_qspi_1 = {
.name = "slv_qhs_qspi_1",
- .id = SC8180X_SLAVE_QSPI_1,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_qupv3_east0 = {
.name = "slv_qhs_qupv3_east0",
- .id = SC8180X_SLAVE_QUP_1,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_qupv3_east1 = {
.name = "slv_qhs_qupv3_east1",
- .id = SC8180X_SLAVE_QUP_2,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_qupv3_west = {
.name = "slv_qhs_qupv3_west",
- .id = SC8180X_SLAVE_QUP_0,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_sdc2 = {
.name = "slv_qhs_sdc2",
- .id = SC8180X_SLAVE_SDCC_2,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_sdc4 = {
.name = "slv_qhs_sdc4",
- .id = SC8180X_SLAVE_SDCC_4,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_security = {
.name = "slv_qhs_security",
- .id = SC8180X_SLAVE_SECURITY,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_snoc_cfg = {
.name = "slv_qhs_snoc_cfg",
- .id = SC8180X_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_MASTER_SNOC_CFG }
+ .link_nodes = { &mas_qhm_snoc_cfg, NULL }
};
static struct qcom_icc_node slv_qhs_spss_cfg = {
.name = "slv_qhs_spss_cfg",
- .id = SC8180X_SLAVE_SPSS_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_tcsr = {
.name = "slv_qhs_tcsr",
- .id = SC8180X_SLAVE_TCSR,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_tlmm_east = {
.name = "slv_qhs_tlmm_east",
- .id = SC8180X_SLAVE_TLMM_EAST,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_tlmm_south = {
.name = "slv_qhs_tlmm_south",
- .id = SC8180X_SLAVE_TLMM_SOUTH,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_tlmm_west = {
.name = "slv_qhs_tlmm_west",
- .id = SC8180X_SLAVE_TLMM_WEST,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_tsif = {
.name = "slv_qhs_tsif",
- .id = SC8180X_SLAVE_TSIF,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_ufs_card_cfg = {
.name = "slv_qhs_ufs_card_cfg",
- .id = SC8180X_SLAVE_UFS_CARD_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = {
.name = "slv_qhs_ufs_mem0_cfg",
- .id = SC8180X_SLAVE_UFS_MEM_0_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = {
.name = "slv_qhs_ufs_mem1_cfg",
- .id = SC8180X_SLAVE_UFS_MEM_1_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_usb3_0 = {
.name = "slv_qhs_usb3_0",
- .id = SC8180X_SLAVE_USB3,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_usb3_1 = {
.name = "slv_qhs_usb3_1",
- .id = SC8180X_SLAVE_USB3_1,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_usb3_2 = {
.name = "slv_qhs_usb3_2",
- .id = SC8180X_SLAVE_USB3_2,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_venus_cfg = {
.name = "slv_qhs_venus_cfg",
- .id = SC8180X_SLAVE_VENUS_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = {
.name = "slv_qhs_vsense_ctrl_cfg",
- .id = SC8180X_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_srvc_cnoc = {
.name = "slv_srvc_cnoc",
- .id = SC8180X_SLAVE_SERVICE_CNOC,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_gemnoc = {
.name = "slv_qhs_gemnoc",
- .id = SC8180X_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8180X_MASTER_GEM_NOC_CFG }
+ .link_nodes = { &mas_qhm_gemnoc_cfg, NULL }
};
static struct qcom_icc_node slv_qhs_llcc = {
.name = "slv_qhs_llcc",
- .id = SC8180X_SLAVE_LLCC_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = {
.name = "slv_qhs_mdsp_ms_mpu_cfg",
- .id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qns_ecc = {
.name = "slv_qns_ecc",
- .id = SC8180X_SLAVE_ECC,
.channels = 1,
- .buswidth = 32
+ .buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qns_gem_noc_snoc = {
.name = "slv_qns_gem_noc_snoc",
- .id = SC8180X_SLAVE_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_MASTER_GEM_NOC_SNOC }
+ .link_nodes = { &mas_qnm_gemnoc, NULL }
};
static struct qcom_icc_node slv_qns_llcc = {
.name = "slv_qns_llcc",
- .id = SC8180X_SLAVE_LLCC,
.channels = 8,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8180X_MASTER_LLCC }
+ .link_nodes = { &mas_llcc_mc, NULL }
};
static struct qcom_icc_node slv_srvc_gemnoc = {
.name = "slv_srvc_gemnoc",
- .id = SC8180X_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_srvc_gemnoc1 = {
.name = "slv_srvc_gemnoc1",
- .id = SC8180X_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_ebi = {
.name = "slv_ebi",
- .id = SC8180X_SLAVE_EBI_CH0,
.channels = 8,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qns2_mem_noc = {
.name = "slv_qns2_mem_noc",
- .id = SC8180X_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_MASTER_MNOC_SF_MEM_NOC }
+ .link_nodes = { &mas_qnm_mnoc_sf, NULL }
};
static struct qcom_icc_node slv_qns_mem_noc_hf = {
.name = "slv_qns_mem_noc_hf",
- .id = SC8180X_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_MASTER_MNOC_HF_MEM_NOC }
+ .link_nodes = { &mas_qnm_mnoc_hf, NULL }
};
static struct qcom_icc_node slv_srvc_mnoc = {
.name = "slv_srvc_mnoc",
- .id = SC8180X_SLAVE_SERVICE_MNOC,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qhs_apss = {
.name = "slv_qhs_apss",
- .id = SC8180X_SLAVE_APPSS,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qns_cnoc = {
.name = "slv_qns_cnoc",
- .id = SC8180X_SNOC_CNOC_SLV,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_SNOC_CNOC_MAS }
+ .link_nodes = { &mas_qnm_snoc, NULL }
};
static struct qcom_icc_node slv_qns_gemnoc_gc = {
.name = "slv_qns_gemnoc_gc",
- .id = SC8180X_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8180X_MASTER_SNOC_GC_MEM_NOC }
+ .link_nodes = { &mas_qnm_snoc_gc, NULL }
};
static struct qcom_icc_node slv_qns_gemnoc_sf = {
.name = "slv_qns_gemnoc_sf",
- .id = SC8180X_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8180X_MASTER_SNOC_SF_MEM_NOC }
+ .link_nodes = { &mas_qnm_snoc_sf, NULL }
};
static struct qcom_icc_node slv_qxs_imem = {
.name = "slv_qxs_imem",
- .id = SC8180X_SLAVE_OCIMEM,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qxs_pimem = {
.name = "slv_qxs_pimem",
- .id = SC8180X_SLAVE_PIMEM,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_srvc_snoc = {
.name = "slv_srvc_snoc",
- .id = SC8180X_SLAVE_SERVICE_SNOC,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_xs_pcie_0 = {
.name = "slv_xs_pcie_0",
- .id = SC8180X_SLAVE_PCIE_0,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_xs_pcie_1 = {
.name = "slv_xs_pcie_1",
- .id = SC8180X_SLAVE_PCIE_1,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_xs_pcie_2 = {
.name = "slv_xs_pcie_2",
- .id = SC8180X_SLAVE_PCIE_2,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_xs_pcie_3 = {
.name = "slv_xs_pcie_3",
- .id = SC8180X_SLAVE_PCIE_3,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_xs_qdss_stm = {
.name = "slv_xs_qdss_stm",
- .id = SC8180X_SLAVE_QDSS_STM,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_xs_sys_tcu_cfg = {
.name = "slv_xs_sys_tcu_cfg",
- .id = SC8180X_SLAVE_TCU,
.channels = 1,
- .buswidth = 8
+ .buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qup_core_0 = {
.name = "slv_qup_core_0",
- .id = SC8180X_SLAVE_QUP_CORE_0,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qup_core_1 = {
.name = "slv_qup_core_1",
- .id = SC8180X_SLAVE_QUP_CORE_1,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node slv_qup_core_2 = {
.name = "slv_qup_core_2",
- .id = SC8180X_SLAVE_QUP_CORE_2,
.channels = 1,
- .buswidth = 4
+ .buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1767,6 +1761,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8180x_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1774,6 +1769,7 @@ static const struct qcom_icc_desc sc8180x_aggre1_noc = {
};
static const struct qcom_icc_desc sc8180x_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1781,6 +1777,7 @@ static const struct qcom_icc_desc sc8180x_aggre2_noc = {
};
static const struct qcom_icc_desc sc8180x_camnoc_virt = {
+ .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1788,6 +1785,7 @@ static const struct qcom_icc_desc sc8180x_camnoc_virt = {
};
static const struct qcom_icc_desc sc8180x_compute_noc = {
+ .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1795,6 +1793,7 @@ static const struct qcom_icc_desc sc8180x_compute_noc = {
};
static const struct qcom_icc_desc sc8180x_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1802,11 +1801,13 @@ static const struct qcom_icc_desc sc8180x_config_noc = {
};
static const struct qcom_icc_desc sc8180x_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
static const struct qcom_icc_desc sc8180x_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1814,6 +1815,7 @@ static const struct qcom_icc_desc sc8180x_gem_noc = {
};
static const struct qcom_icc_desc sc8180x_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1821,6 +1823,7 @@ static const struct qcom_icc_desc sc8180x_mc_virt = {
};
static const struct qcom_icc_desc sc8180x_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1828,6 +1831,7 @@ static const struct qcom_icc_desc sc8180x_mmss_noc = {
};
static const struct qcom_icc_desc sc8180x_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
@@ -1848,6 +1852,7 @@ static struct qcom_icc_node * const qup_virt_nodes[] = {
};
static const struct qcom_icc_desc sc8180x_qup_virt = {
+ .alloc_dyn_id = true,
.nodes = qup_virt_nodes,
.num_nodes = ARRAY_SIZE(qup_virt_nodes),
.bcms = qup_virt_bcms,
diff --git a/drivers/interconnect/qcom/sc8180x.h b/drivers/interconnect/qcom/sc8180x.h
deleted file mode 100644
index f8d90598335a1d334a6b783bfe8569ab3c46b4f2..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sc8180x.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm #define SC8180X interconnect IDs
- *
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8180X_H
-#define __DRIVERS_INTERCONNECT_QCOM_SC8180X_H
-
-#define SC8180X_MASTER_A1NOC_CFG 1
-#define SC8180X_MASTER_UFS_CARD 2
-#define SC8180X_MASTER_UFS_GEN4 3
-#define SC8180X_MASTER_UFS_MEM 4
-#define SC8180X_MASTER_USB3 5
-#define SC8180X_MASTER_USB3_1 6
-#define SC8180X_MASTER_USB3_2 7
-#define SC8180X_MASTER_A2NOC_CFG 8
-#define SC8180X_MASTER_QDSS_BAM 9
-#define SC8180X_MASTER_QSPI_0 10
-#define SC8180X_MASTER_QSPI_1 11
-#define SC8180X_MASTER_QUP_0 12
-#define SC8180X_MASTER_QUP_1 13
-#define SC8180X_MASTER_QUP_2 14
-#define SC8180X_MASTER_SENSORS_AHB 15
-#define SC8180X_MASTER_CRYPTO_CORE_0 16
-#define SC8180X_MASTER_IPA 17
-#define SC8180X_MASTER_EMAC 18
-#define SC8180X_MASTER_PCIE 19
-#define SC8180X_MASTER_PCIE_1 20
-#define SC8180X_MASTER_PCIE_2 21
-#define SC8180X_MASTER_PCIE_3 22
-#define SC8180X_MASTER_QDSS_ETR 23
-#define SC8180X_MASTER_SDCC_2 24
-#define SC8180X_MASTER_SDCC_4 25
-#define SC8180X_MASTER_CAMNOC_HF0_UNCOMP 26
-#define SC8180X_MASTER_CAMNOC_HF1_UNCOMP 27
-#define SC8180X_MASTER_CAMNOC_SF_UNCOMP 28
-#define SC8180X_MASTER_NPU 29
-#define SC8180X_SNOC_CNOC_MAS 30
-#define SC8180X_MASTER_CNOC_DC_NOC 31
-#define SC8180X_MASTER_AMPSS_M0 32
-#define SC8180X_MASTER_GPU_TCU 33
-#define SC8180X_MASTER_SYS_TCU 34
-#define SC8180X_MASTER_GEM_NOC_CFG 35
-#define SC8180X_MASTER_COMPUTE_NOC 36
-#define SC8180X_MASTER_GRAPHICS_3D 37
-#define SC8180X_MASTER_MNOC_HF_MEM_NOC 38
-#define SC8180X_MASTER_MNOC_SF_MEM_NOC 39
-#define SC8180X_MASTER_GEM_NOC_PCIE_SNOC 40
-#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
-#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
-#define SC8180X_MASTER_ECC 43
-/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */
-#define SC8180X_MASTER_LLCC 45
-#define SC8180X_MASTER_CNOC_MNOC_CFG 46
-#define SC8180X_MASTER_CAMNOC_HF0 47
-#define SC8180X_MASTER_CAMNOC_HF1 48
-#define SC8180X_MASTER_CAMNOC_SF 49
-#define SC8180X_MASTER_MDP_PORT0 50
-#define SC8180X_MASTER_MDP_PORT1 51
-#define SC8180X_MASTER_ROTATOR 52
-#define SC8180X_MASTER_VIDEO_P0 53
-#define SC8180X_MASTER_VIDEO_P1 54
-#define SC8180X_MASTER_VIDEO_PROC 55
-#define SC8180X_MASTER_SNOC_CFG 56
-#define SC8180X_A1NOC_SNOC_MAS 57
-#define SC8180X_A2NOC_SNOC_MAS 58
-#define SC8180X_MASTER_GEM_NOC_SNOC 59
-#define SC8180X_MASTER_PIMEM 60
-#define SC8180X_MASTER_GIC 61
-#define SC8180X_MASTER_MNOC_HF_MEM_NOC_DISPLAY 62
-#define SC8180X_MASTER_MNOC_SF_MEM_NOC_DISPLAY 63
-#define SC8180X_MASTER_LLCC_DISPLAY 64
-#define SC8180X_MASTER_MDP_PORT0_DISPLAY 65
-#define SC8180X_MASTER_MDP_PORT1_DISPLAY 66
-#define SC8180X_MASTER_ROTATOR_DISPLAY 67
-#define SC8180X_A1NOC_SNOC_SLV 68
-#define SC8180X_SLAVE_SERVICE_A1NOC 69
-#define SC8180X_A2NOC_SNOC_SLV 70
-#define SC8180X_SLAVE_ANOC_PCIE_GEM_NOC 71
-#define SC8180X_SLAVE_SERVICE_A2NOC 72
-#define SC8180X_SLAVE_CAMNOC_UNCOMP 73
-#define SC8180X_SLAVE_CDSP_MEM_NOC 74
-#define SC8180X_SLAVE_A1NOC_CFG 75
-#define SC8180X_SLAVE_A2NOC_CFG 76
-#define SC8180X_SLAVE_AHB2PHY_CENTER 77
-#define SC8180X_SLAVE_AHB2PHY_EAST 78
-#define SC8180X_SLAVE_AHB2PHY_WEST 79
-#define SC8180X_SLAVE_AHB2PHY_SOUTH 80
-#define SC8180X_SLAVE_AOP 81
-#define SC8180X_SLAVE_AOSS 82
-#define SC8180X_SLAVE_CAMERA_CFG 83
-#define SC8180X_SLAVE_CLK_CTL 84
-#define SC8180X_SLAVE_CDSP_CFG 85
-#define SC8180X_SLAVE_RBCPR_CX_CFG 86
-#define SC8180X_SLAVE_RBCPR_MMCX_CFG 87
-#define SC8180X_SLAVE_RBCPR_MX_CFG 88
-#define SC8180X_SLAVE_CRYPTO_0_CFG 89
-#define SC8180X_SLAVE_CNOC_DDRSS 90
-#define SC8180X_SLAVE_DISPLAY_CFG 91
-#define SC8180X_SLAVE_EMAC_CFG 92
-#define SC8180X_SLAVE_GLM 93
-#define SC8180X_SLAVE_GRAPHICS_3D_CFG 94
-#define SC8180X_SLAVE_IMEM_CFG 95
-#define SC8180X_SLAVE_IPA_CFG 96
-#define SC8180X_SLAVE_CNOC_MNOC_CFG 97
-#define SC8180X_SLAVE_NPU_CFG 98
-#define SC8180X_SLAVE_PCIE_0_CFG 99
-#define SC8180X_SLAVE_PCIE_1_CFG 100
-#define SC8180X_SLAVE_PCIE_2_CFG 101
-#define SC8180X_SLAVE_PCIE_3_CFG 102
-#define SC8180X_SLAVE_PDM 103
-#define SC8180X_SLAVE_PIMEM_CFG 104
-#define SC8180X_SLAVE_PRNG 105
-#define SC8180X_SLAVE_QDSS_CFG 106
-#define SC8180X_SLAVE_QSPI_0 107
-#define SC8180X_SLAVE_QSPI_1 108
-#define SC8180X_SLAVE_QUP_1 109
-#define SC8180X_SLAVE_QUP_2 110
-#define SC8180X_SLAVE_QUP_0 111
-#define SC8180X_SLAVE_SDCC_2 112
-#define SC8180X_SLAVE_SDCC_4 113
-#define SC8180X_SLAVE_SECURITY 114
-#define SC8180X_SLAVE_SNOC_CFG 115
-#define SC8180X_SLAVE_SPSS_CFG 116
-#define SC8180X_SLAVE_TCSR 117
-#define SC8180X_SLAVE_TLMM_EAST 118
-#define SC8180X_SLAVE_TLMM_SOUTH 119
-#define SC8180X_SLAVE_TLMM_WEST 120
-#define SC8180X_SLAVE_TSIF 121
-#define SC8180X_SLAVE_UFS_CARD_CFG 122
-#define SC8180X_SLAVE_UFS_MEM_0_CFG 123
-#define SC8180X_SLAVE_UFS_MEM_1_CFG 124
-#define SC8180X_SLAVE_USB3 125
-#define SC8180X_SLAVE_USB3_1 126
-#define SC8180X_SLAVE_USB3_2 127
-#define SC8180X_SLAVE_VENUS_CFG 128
-#define SC8180X_SLAVE_VSENSE_CTRL_CFG 129
-#define SC8180X_SLAVE_SERVICE_CNOC 130
-#define SC8180X_SLAVE_GEM_NOC_CFG 131
-#define SC8180X_SLAVE_LLCC_CFG 132
-#define SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG 133
-#define SC8180X_SLAVE_ECC 134
-#define SC8180X_SLAVE_GEM_NOC_SNOC 135
-#define SC8180X_SLAVE_LLCC 136
-#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
-#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
-/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
-#define SC8180X_SLAVE_EBI_CH0 140
-#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
-#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142
-#define SC8180X_SLAVE_SERVICE_MNOC 143
-#define SC8180X_SLAVE_APPSS 144
-#define SC8180X_SNOC_CNOC_SLV 145
-#define SC8180X_SLAVE_SNOC_GEM_NOC_GC 146
-#define SC8180X_SLAVE_SNOC_GEM_NOC_SF 147
-#define SC8180X_SLAVE_OCIMEM 148
-#define SC8180X_SLAVE_PIMEM 149
-#define SC8180X_SLAVE_SERVICE_SNOC 150
-#define SC8180X_SLAVE_PCIE_0 151
-#define SC8180X_SLAVE_PCIE_1 152
-#define SC8180X_SLAVE_PCIE_2 153
-#define SC8180X_SLAVE_PCIE_3 154
-#define SC8180X_SLAVE_QDSS_STM 155
-#define SC8180X_SLAVE_TCU 156
-#define SC8180X_SLAVE_LLCC_DISPLAY 157
-#define SC8180X_SLAVE_EBI_CH0_DISPLAY 158
-#define SC8180X_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 159
-#define SC8180X_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 160
-
-#define SC8180X_MASTER_QUP_CORE_0 163
-#define SC8180X_MASTER_QUP_CORE_1 164
-#define SC8180X_MASTER_QUP_CORE_2 165
-#define SC8180X_SLAVE_QUP_CORE_0 166
-#define SC8180X_SLAVE_QUP_CORE_1 167
-#define SC8180X_SLAVE_QUP_CORE_2 168
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 07/28] interconnect: qcom: sc8280xp: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (5 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 06/28] interconnect: qcom: sc8180x: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 08/28] interconnect: qcom: sdm845: " Dmitry Baryshkov
` (21 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sc8280xp.c | 1181 +++++++++++++++++-----------------
drivers/interconnect/qcom/sc8280xp.h | 209 ------
2 files changed, 587 insertions(+), 803 deletions(-)
diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c
index 1a9b97aa9e1c5bec0cda12cb4c5a8b14af970358..d9fd67ae6258d66ab3e78e06863a5a42da3ac131 100644
--- a/drivers/interconnect/qcom/sc8280xp.c
+++ b/drivers/interconnect/qcom/sc8280xp.c
@@ -14,1701 +14,1682 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sc8280xp.h"
+
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qnm_a1noc_cfg;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_emac_1;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node xm_usb3_1;
+static struct qcom_icc_node xm_usb3_mp;
+static struct qcom_icc_node xm_usb4_host0;
+static struct qcom_icc_node xm_usb4_host1;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qnm_a2noc_cfg;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_sensorss_q6;
+static struct qcom_icc_node qxm_sp;
+static struct qcom_icc_node xm_emac_0;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node xm_pcie3_2a;
+static struct qcom_icc_node xm_pcie3_2b;
+static struct qcom_icc_node xm_pcie3_3a;
+static struct qcom_icc_node xm_pcie3_3b;
+static struct qcom_icc_node xm_pcie3_4;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_ufs_card;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qnm_cnoc_dc_noc;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_pcie_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_cmpnoc0;
+static struct qcom_icc_node qnm_cmpnoc1;
+static struct qcom_icc_node qnm_gemnoc_cfg;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qhm_config_noc;
+static struct qcom_icc_node qxm_lpass_dsp;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_mdp0_0;
+static struct qcom_icc_node qnm_mdp0_1;
+static struct qcom_icc_node qnm_mdp1_0;
+static struct qcom_icc_node qnm_mdp1_1;
+static struct qcom_icc_node qnm_mnoc_cfg;
+static struct qcom_icc_node qnm_rot_0;
+static struct qcom_icc_node qnm_rot_1;
+static struct qcom_icc_node qnm_video0;
+static struct qcom_icc_node qnm_video1;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qxm_camnoc_icp;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qhm_nsp_noc_config;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qhm_nspb_noc_config;
+static struct qcom_icc_node qxm_nspb;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_aggre_usb_noc;
+static struct qcom_icc_node qnm_lpass_noc;
+static struct qcom_icc_node qnm_snoc_cfg;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_aggre_usb_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_gem_noc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_ahb2phy2;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute0_cfg;
+static struct qcom_icc_node qhs_compute1_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_cpr_nspcx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_display0_cfg;
+static struct qcom_icc_node qhs_display1_cfg;
+static struct qcom_icc_node qhs_emac0_cfg;
+static struct qcom_icc_node qhs_emac1_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_hwkm;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_mxc_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pcie2a_cfg;
+static struct qcom_icc_node qhs_pcie2b_cfg;
+static struct qcom_icc_node qhs_pcie3a_cfg;
+static struct qcom_icc_node qhs_pcie3b_cfg;
+static struct qcom_icc_node qhs_pcie4_cfg;
+static struct qcom_icc_node qhs_pcie_rsc_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_pka_wrapper_cfg;
+static struct qcom_icc_node qhs_pmu_wrapper_cfg;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_security;
+static struct qcom_icc_node qhs_smmuv3_cfg;
+static struct qcom_icc_node qhs_smss_cfg;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_card_cfg;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_usb3_1;
+static struct qcom_icc_node qhs_usb3_mp;
+static struct qcom_icc_node qhs_usb4_host_0;
+static struct qcom_icc_node qhs_usb4_host_1;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_r_cfg;
+static struct qcom_icc_node qns_a1_noc_cfg;
+static struct qcom_icc_node qns_a2_noc_cfg;
+static struct qcom_icc_node qns_anoc_pcie_bridge_cfg;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qns_mnoc_cfg;
+static struct qcom_icc_node qns_snoc_cfg;
+static struct qcom_icc_node qns_snoc_sf_bridge_cfg;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_pcie_2a;
+static struct qcom_icc_node xs_pcie_2b;
+static struct qcom_icc_node xs_pcie_3a;
+static struct qcom_icc_node xs_pcie_3b;
+static struct qcom_icc_node xs_pcie_4;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_smss;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qns_gemnoc;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node srvc_even_gemnoc;
+static struct qcom_icc_node srvc_odd_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc;
+static struct qcom_icc_node qhs_lpass_core;
+static struct qcom_icc_node qhs_lpass_lpi;
+static struct qcom_icc_node qhs_lpass_mpu;
+static struct qcom_icc_node qhs_lpass_top;
+static struct qcom_icc_node qns_sysnoc;
+static struct qcom_icc_node srvc_niu_aml_noc;
+static struct qcom_icc_node srvc_niu_lpass_agnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node qxs_nsp_xfr;
+static struct qcom_icc_node service_nsp_noc;
+static struct qcom_icc_node qns_nspb_gemnoc;
+static struct qcom_icc_node qxs_nspb_xfr;
+static struct qcom_icc_node service_nspb_noc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node srvc_snoc;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SC8280XP_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SC8280XP_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SC8280XP_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qnm_a1noc_cfg = {
.name = "qnm_a1noc_cfg",
- .id = SC8280XP_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SC8280XP_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emac_1 = {
.name = "xm_emac_1",
- .id = SC8280XP_MASTER_EMAC_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SC8280XP_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SC8280XP_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SC8280XP_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
+ .link_nodes = { &qns_aggre_usb_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
- .id = SC8280XP_MASTER_USB3_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
+ .link_nodes = { &qns_aggre_usb_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_mp = {
.name = "xm_usb3_mp",
- .id = SC8280XP_MASTER_USB3_MP,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
+ .link_nodes = { &qns_aggre_usb_snoc, NULL },
};
static struct qcom_icc_node xm_usb4_host0 = {
.name = "xm_usb4_host0",
- .id = SC8280XP_MASTER_USB4_0,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
+ .link_nodes = { &qns_aggre_usb_snoc, NULL },
};
static struct qcom_icc_node xm_usb4_host1 = {
.name = "xm_usb4_host1",
- .id = SC8280XP_MASTER_USB4_1,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
+ .link_nodes = { &qns_aggre_usb_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SC8280XP_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SC8280XP_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_a2noc_cfg = {
.name = "qnm_a2noc_cfg",
- .id = SC8280XP_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SC8280XP_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sensorss_q6 = {
.name = "qxm_sensorss_q6",
- .id = SC8280XP_MASTER_SENSORS_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sp = {
.name = "qxm_sp",
- .id = SC8280XP_MASTER_SP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
- .id = SC8280XP_MASTER_EMAC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SC8280XP_MASTER_PCIE_0,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SC8280XP_MASTER_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_2a = {
.name = "xm_pcie3_2a",
- .id = SC8280XP_MASTER_PCIE_2A,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_2b = {
.name = "xm_pcie3_2b",
- .id = SC8280XP_MASTER_PCIE_2B,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_3a = {
.name = "xm_pcie3_3a",
- .id = SC8280XP_MASTER_PCIE_3A,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_3b = {
.name = "xm_pcie3_3b",
- .id = SC8280XP_MASTER_PCIE_3B,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_4 = {
.name = "xm_pcie3_4",
- .id = SC8280XP_MASTER_PCIE_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gem_noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SC8280XP_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SC8280XP_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_card = {
.name = "xm_ufs_card",
- .id = SC8280XP_MASTER_UFS_CARD,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SC8280XP_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SC8280XP_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = SC8280XP_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_QUP_CORE_2 },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SC8280XP_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 76,
- .links = { SC8280XP_SLAVE_AHB2PHY_0,
- SC8280XP_SLAVE_AHB2PHY_1,
- SC8280XP_SLAVE_AHB2PHY_2,
- SC8280XP_SLAVE_AOSS,
- SC8280XP_SLAVE_APPSS,
- SC8280XP_SLAVE_CAMERA_CFG,
- SC8280XP_SLAVE_CLK_CTL,
- SC8280XP_SLAVE_CDSP_CFG,
- SC8280XP_SLAVE_CDSP1_CFG,
- SC8280XP_SLAVE_RBCPR_CX_CFG,
- SC8280XP_SLAVE_RBCPR_MMCX_CFG,
- SC8280XP_SLAVE_RBCPR_MX_CFG,
- SC8280XP_SLAVE_CPR_NSPCX,
- SC8280XP_SLAVE_CRYPTO_0_CFG,
- SC8280XP_SLAVE_CX_RDPM,
- SC8280XP_SLAVE_DCC_CFG,
- SC8280XP_SLAVE_DISPLAY_CFG,
- SC8280XP_SLAVE_DISPLAY1_CFG,
- SC8280XP_SLAVE_EMAC_CFG,
- SC8280XP_SLAVE_EMAC1_CFG,
- SC8280XP_SLAVE_GFX3D_CFG,
- SC8280XP_SLAVE_HWKM,
- SC8280XP_SLAVE_IMEM_CFG,
- SC8280XP_SLAVE_IPA_CFG,
- SC8280XP_SLAVE_IPC_ROUTER_CFG,
- SC8280XP_SLAVE_LPASS,
- SC8280XP_SLAVE_MX_RDPM,
- SC8280XP_SLAVE_MXC_RDPM,
- SC8280XP_SLAVE_PCIE_0_CFG,
- SC8280XP_SLAVE_PCIE_1_CFG,
- SC8280XP_SLAVE_PCIE_2A_CFG,
- SC8280XP_SLAVE_PCIE_2B_CFG,
- SC8280XP_SLAVE_PCIE_3A_CFG,
- SC8280XP_SLAVE_PCIE_3B_CFG,
- SC8280XP_SLAVE_PCIE_4_CFG,
- SC8280XP_SLAVE_PCIE_RSC_CFG,
- SC8280XP_SLAVE_PDM,
- SC8280XP_SLAVE_PIMEM_CFG,
- SC8280XP_SLAVE_PKA_WRAPPER_CFG,
- SC8280XP_SLAVE_PMU_WRAPPER_CFG,
- SC8280XP_SLAVE_QDSS_CFG,
- SC8280XP_SLAVE_QSPI_0,
- SC8280XP_SLAVE_QUP_0,
- SC8280XP_SLAVE_QUP_1,
- SC8280XP_SLAVE_QUP_2,
- SC8280XP_SLAVE_SDCC_2,
- SC8280XP_SLAVE_SDCC_4,
- SC8280XP_SLAVE_SECURITY,
- SC8280XP_SLAVE_SMMUV3_CFG,
- SC8280XP_SLAVE_SMSS_CFG,
- SC8280XP_SLAVE_SPSS_CFG,
- SC8280XP_SLAVE_TCSR,
- SC8280XP_SLAVE_TLMM,
- SC8280XP_SLAVE_UFS_CARD_CFG,
- SC8280XP_SLAVE_UFS_MEM_CFG,
- SC8280XP_SLAVE_USB3_0,
- SC8280XP_SLAVE_USB3_1,
- SC8280XP_SLAVE_USB3_MP,
- SC8280XP_SLAVE_USB4_0,
- SC8280XP_SLAVE_USB4_1,
- SC8280XP_SLAVE_VENUS_CFG,
- SC8280XP_SLAVE_VSENSE_CTRL_CFG,
- SC8280XP_SLAVE_VSENSE_CTRL_R_CFG,
- SC8280XP_SLAVE_A1NOC_CFG,
- SC8280XP_SLAVE_A2NOC_CFG,
- SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG,
- SC8280XP_SLAVE_DDRSS_CFG,
- SC8280XP_SLAVE_CNOC_MNOC_CFG,
- SC8280XP_SLAVE_SNOC_CFG,
- SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG,
- SC8280XP_SLAVE_IMEM,
- SC8280XP_SLAVE_PIMEM,
- SC8280XP_SLAVE_SERVICE_CNOC,
- SC8280XP_SLAVE_QDSS_STM,
- SC8280XP_SLAVE_SMSS,
- SC8280XP_SLAVE_TCU
- },
+ .link_nodes = { &qhs_ahb2phy0,
+ &qhs_ahb2phy1,
+ &qhs_ahb2phy2,
+ &qhs_aoss,
+ &qhs_apss,
+ &qhs_camera_cfg,
+ &qhs_clk_ctl,
+ &qhs_compute0_cfg,
+ &qhs_compute1_cfg,
+ &qhs_cpr_cx,
+ &qhs_cpr_mmcx,
+ &qhs_cpr_mx,
+ &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg,
+ &qhs_cx_rdpm,
+ &qhs_dcc_cfg,
+ &qhs_display0_cfg,
+ &qhs_display1_cfg,
+ &qhs_emac0_cfg,
+ &qhs_emac1_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_hwkm,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_ipc_router,
+ &qhs_lpass_cfg,
+ &qhs_mx_rdpm,
+ &qhs_mxc_rdpm,
+ &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg,
+ &qhs_pcie2a_cfg,
+ &qhs_pcie2b_cfg,
+ &qhs_pcie3a_cfg,
+ &qhs_pcie3b_cfg,
+ &qhs_pcie4_cfg,
+ &qhs_pcie_rsc_cfg,
+ &qhs_pdm,
+ &qhs_pimem_cfg,
+ &qhs_pka_wrapper_cfg,
+ &qhs_pmu_wrapper_cfg,
+ &qhs_qdss_cfg,
+ &qhs_qspi,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_qup2,
+ &qhs_sdc2,
+ &qhs_sdc4,
+ &qhs_security,
+ &qhs_smmuv3_cfg,
+ &qhs_smss_cfg,
+ &qhs_spss_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_ufs_card_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3_0,
+ &qhs_usb3_1,
+ &qhs_usb3_mp,
+ &qhs_usb4_host_0,
+ &qhs_usb4_host_1,
+ &qhs_venus_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_vsense_ctrl_r_cfg,
+ &qns_a1_noc_cfg,
+ &qns_a2_noc_cfg,
+ &qns_anoc_pcie_bridge_cfg,
+ &qns_ddrss_cfg,
+ &qns_mnoc_cfg,
+ &qns_snoc_cfg,
+ &qns_snoc_sf_bridge_cfg,
+ &qxs_imem,
+ &qxs_pimem,
+ &srvc_cnoc,
+ &xs_qdss_stm,
+ &xs_smss,
+ &xs_sys_tcu_cfg,
+ NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SC8280XP_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 7,
- .links = { SC8280XP_SLAVE_PCIE_0,
- SC8280XP_SLAVE_PCIE_1,
- SC8280XP_SLAVE_PCIE_2A,
- SC8280XP_SLAVE_PCIE_2B,
- SC8280XP_SLAVE_PCIE_3A,
- SC8280XP_SLAVE_PCIE_3B,
- SC8280XP_SLAVE_PCIE_4
- },
+ .link_nodes = { &xs_pcie_0,
+ &xs_pcie_1,
+ &xs_pcie_2a,
+ &xs_pcie_2b,
+ &xs_pcie_3a,
+ &xs_pcie_3b,
+ &xs_pcie_4, NULL },
};
static struct qcom_icc_node qnm_cnoc_dc_noc = {
.name = "qnm_cnoc_dc_noc",
- .id = SC8280XP_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_LLCC_CFG,
- SC8280XP_SLAVE_GEM_NOC_CFG
- },
+ .link_nodes = { &qhs_llcc,
+ &qns_gemnoc, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SC8280XP_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node alm_pcie_tcu = {
.name = "alm_pcie_tcu",
- .id = SC8280XP_MASTER_PCIE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SC8280XP_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SC8280XP_MASTER_APPSS_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC,
- SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_cmpnoc0 = {
.name = "qnm_cmpnoc0",
- .id = SC8280XP_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_cmpnoc1 = {
.name = "qnm_cmpnoc1",
- .id = SC8280XP_MASTER_COMPUTE_NOC_1,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
- .id = SC8280XP_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 3,
- .links = { SC8280XP_SLAVE_SERVICE_GEM_NOC_1,
- SC8280XP_SLAVE_SERVICE_GEM_NOC_2,
- SC8280XP_SLAVE_SERVICE_GEM_NOC
- },
+ .link_nodes = { &srvc_even_gemnoc,
+ &srvc_odd_gemnoc,
+ &srvc_sys_gemnoc, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SC8280XP_MASTER_GFX3D,
.channels = 4,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SC8280XP_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_LLCC,
- SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SC8280XP_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SC8280XP_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SC8280XP_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SC8280XP_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
- SC8280XP_SLAVE_LLCC,
- SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
- .id = SC8280XP_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 6,
- .links = { SC8280XP_SLAVE_LPASS_CORE_CFG,
- SC8280XP_SLAVE_LPASS_LPI_CFG,
- SC8280XP_SLAVE_LPASS_MPU_CFG,
- SC8280XP_SLAVE_LPASS_TOP_CFG,
- SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
- SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC
- },
+ .link_nodes = { &qhs_lpass_core,
+ &qhs_lpass_lpi,
+ &qhs_lpass_mpu,
+ &qhs_lpass_top,
+ &srvc_niu_aml_noc,
+ &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node qxm_lpass_dsp = {
.name = "qxm_lpass_dsp",
- .id = SC8280XP_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 4,
- .links = { SC8280XP_SLAVE_LPASS_TOP_CFG,
- SC8280XP_SLAVE_LPASS_SNOC,
- SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
- SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC
- },
+ .link_nodes = { &qhs_lpass_top,
+ &qns_sysnoc,
+ &srvc_niu_aml_noc,
+ &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SC8280XP_MASTER_LLCC,
.channels = 8,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SC8280XP_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mdp0_0 = {
.name = "qnm_mdp0_0",
- .id = SC8280XP_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mdp0_1 = {
.name = "qnm_mdp0_1",
- .id = SC8280XP_MASTER_MDP1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mdp1_0 = {
.name = "qnm_mdp1_0",
- .id = SC8280XP_MASTER_MDP_CORE1_0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mdp1_1 = {
.name = "qnm_mdp1_1",
- .id = SC8280XP_MASTER_MDP_CORE1_1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mnoc_cfg = {
.name = "qnm_mnoc_cfg",
- .id = SC8280XP_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qnm_rot_0 = {
.name = "qnm_rot_0",
- .id = SC8280XP_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_rot_1 = {
.name = "qnm_rot_1",
- .id = SC8280XP_MASTER_ROTATOR_1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
- .id = SC8280XP_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video1 = {
.name = "qnm_video1",
- .id = SC8280XP_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SC8280XP_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_camnoc_icp = {
.name = "qxm_camnoc_icp",
- .id = SC8280XP_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SC8280XP_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
- .id = SC8280XP_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SERVICE_NSP_NOC },
+ .link_nodes = { &service_nsp_noc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SC8280XP_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_CDSP_MEM_NOC,
- SC8280XP_SLAVE_NSP_XFR
- },
+ .link_nodes = { &qns_nsp_gemnoc,
+ &qxs_nsp_xfr, NULL },
};
static struct qcom_icc_node qhm_nspb_noc_config = {
.name = "qhm_nspb_noc_config",
- .id = SC8280XP_MASTER_CDSPB_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SERVICE_NSPB_NOC },
+ .link_nodes = { &service_nspb_noc, NULL },
};
static struct qcom_icc_node qxm_nspb = {
.name = "qxm_nspb",
- .id = SC8280XP_MASTER_CDSP_PROC_B,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SC8280XP_SLAVE_CDSPB_MEM_NOC,
- SC8280XP_SLAVE_NSPB_XFR
- },
+ .link_nodes = { &qns_nspb_gemnoc,
+ &qxs_nspb_xfr, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SC8280XP_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SC8280XP_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre_usb_noc = {
.name = "qnm_aggre_usb_noc",
- .id = SC8280XP_MASTER_USB_NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_lpass_noc = {
.name = "qnm_lpass_noc",
- .id = SC8280XP_MASTER_LPASS_ANOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
- .id = SC8280XP_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SC8280XP_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SC8280XP_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SC8280XP_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_aggre_usb_snoc = {
.name = "qns_aggre_usb_snoc",
- .id = SC8280XP_SLAVE_USB_NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_MASTER_USB_NOC_SNOC },
+ .link_nodes = { &qnm_aggre_usb_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SC8280XP_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SC8280XP_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qns_pcie_gem_noc = {
.name = "qns_pcie_gem_noc",
- .id = SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SC8280XP_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SC8280XP_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SC8280XP_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = SC8280XP_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SC8280XP_SLAVE_AHB2PHY_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SC8280XP_SLAVE_AHB2PHY_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy2 = {
.name = "qhs_ahb2phy2",
- .id = SC8280XP_SLAVE_AHB2PHY_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SC8280XP_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SC8280XP_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SC8280XP_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SC8280XP_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute0_cfg = {
.name = "qhs_compute0_cfg",
- .id = SC8280XP_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_CDSP_NOC_CFG },
+ .link_nodes = { &qhm_nsp_noc_config, NULL },
};
static struct qcom_icc_node qhs_compute1_cfg = {
.name = "qhs_compute1_cfg",
- .id = SC8280XP_SLAVE_CDSP1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_CDSPB_NOC_CFG },
+ .link_nodes = { &qhm_nspb_noc_config, NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SC8280XP_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SC8280XP_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SC8280XP_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_nspcx = {
.name = "qhs_cpr_nspcx",
- .id = SC8280XP_SLAVE_CPR_NSPCX,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SC8280XP_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SC8280XP_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SC8280XP_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display0_cfg = {
.name = "qhs_display0_cfg",
- .id = SC8280XP_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display1_cfg = {
.name = "qhs_display1_cfg",
- .id = SC8280XP_SLAVE_DISPLAY1_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emac0_cfg = {
.name = "qhs_emac0_cfg",
- .id = SC8280XP_SLAVE_EMAC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emac1_cfg = {
.name = "qhs_emac1_cfg",
- .id = SC8280XP_SLAVE_EMAC1_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SC8280XP_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_hwkm = {
.name = "qhs_hwkm",
- .id = SC8280XP_SLAVE_HWKM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SC8280XP_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SC8280XP_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SC8280XP_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = SC8280XP_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_CNOC_LPASS_AG_NOC },
+ .link_nodes = { &qhm_config_noc, NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SC8280XP_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mxc_rdpm = {
.name = "qhs_mxc_rdpm",
- .id = SC8280XP_SLAVE_MXC_RDPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SC8280XP_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SC8280XP_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie2a_cfg = {
.name = "qhs_pcie2a_cfg",
- .id = SC8280XP_SLAVE_PCIE_2A_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie2b_cfg = {
.name = "qhs_pcie2b_cfg",
- .id = SC8280XP_SLAVE_PCIE_2B_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie3a_cfg = {
.name = "qhs_pcie3a_cfg",
- .id = SC8280XP_SLAVE_PCIE_3A_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie3b_cfg = {
.name = "qhs_pcie3b_cfg",
- .id = SC8280XP_SLAVE_PCIE_3B_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie4_cfg = {
.name = "qhs_pcie4_cfg",
- .id = SC8280XP_SLAVE_PCIE_4_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_rsc_cfg = {
.name = "qhs_pcie_rsc_cfg",
- .id = SC8280XP_SLAVE_PCIE_RSC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SC8280XP_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SC8280XP_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pka_wrapper_cfg = {
.name = "qhs_pka_wrapper_cfg",
- .id = SC8280XP_SLAVE_PKA_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
.name = "qhs_pmu_wrapper_cfg",
- .id = SC8280XP_SLAVE_PMU_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SC8280XP_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SC8280XP_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SC8280XP_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SC8280XP_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SC8280XP_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SC8280XP_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SC8280XP_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
- .id = SC8280XP_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_smmuv3_cfg = {
.name = "qhs_smmuv3_cfg",
- .id = SC8280XP_SLAVE_SMMUV3_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_smss_cfg = {
.name = "qhs_smss_cfg",
- .id = SC8280XP_SLAVE_SMSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SC8280XP_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SC8280XP_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SC8280XP_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_card_cfg = {
.name = "qhs_ufs_card_cfg",
- .id = SC8280XP_SLAVE_UFS_CARD_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SC8280XP_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SC8280XP_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_1 = {
.name = "qhs_usb3_1",
- .id = SC8280XP_SLAVE_USB3_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_mp = {
.name = "qhs_usb3_mp",
- .id = SC8280XP_SLAVE_USB3_MP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb4_host_0 = {
.name = "qhs_usb4_host_0",
- .id = SC8280XP_SLAVE_USB4_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb4_host_1 = {
.name = "qhs_usb4_host_1",
- .id = SC8280XP_SLAVE_USB4_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SC8280XP_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SC8280XP_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = {
.name = "qhs_vsense_ctrl_r_cfg",
- .id = SC8280XP_SLAVE_VSENSE_CTRL_R_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a1_noc_cfg = {
.name = "qns_a1_noc_cfg",
- .id = SC8280XP_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_A1NOC_CFG },
+ .link_nodes = { &qnm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qns_a2_noc_cfg = {
.name = "qns_a2_noc_cfg",
- .id = SC8280XP_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_A2NOC_CFG },
+ .link_nodes = { &qnm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = {
.name = "qns_anoc_pcie_bridge_cfg",
- .id = SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = SC8280XP_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qnm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qns_mnoc_cfg = {
.name = "qns_mnoc_cfg",
- .id = SC8280XP_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qnm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
- .id = SC8280XP_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_SNOC_CFG },
+ .link_nodes = { &qnm_snoc_cfg, NULL },
};
static struct qcom_icc_node qns_snoc_sf_bridge_cfg = {
.name = "qns_snoc_sf_bridge_cfg",
- .id = SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SC8280XP_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SC8280XP_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SC8280XP_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SC8280XP_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 16,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SC8280XP_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 16,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_2a = {
.name = "xs_pcie_2a",
- .id = SC8280XP_SLAVE_PCIE_2A,
.channels = 1,
.buswidth = 16,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_2b = {
.name = "xs_pcie_2b",
- .id = SC8280XP_SLAVE_PCIE_2B,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_3a = {
.name = "xs_pcie_3a",
- .id = SC8280XP_SLAVE_PCIE_3A,
.channels = 1,
.buswidth = 16,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_3b = {
.name = "xs_pcie_3b",
- .id = SC8280XP_SLAVE_PCIE_3B,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_4 = {
.name = "xs_pcie_4",
- .id = SC8280XP_SLAVE_PCIE_4,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SC8280XP_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_smss = {
.name = "xs_smss",
- .id = SC8280XP_SLAVE_SMSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SC8280XP_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SC8280XP_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
- .id = SC8280XP_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC8280XP_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qnm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SC8280XP_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SC8280XP_SLAVE_LLCC,
.channels = 8,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
- .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
- .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
- .id = SC8280XP_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
- .id = SC8280XP_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
- .id = SC8280XP_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
- .id = SC8280XP_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
- .id = SC8280XP_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_sysnoc = {
.name = "qns_sysnoc",
- .id = SC8280XP_SLAVE_LPASS_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_MASTER_LPASS_ANOC },
+ .link_nodes = { &qnm_lpass_noc, NULL },
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
- .id = SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
- .id = SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SC8280XP_SLAVE_EBI1,
.channels = 8,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SC8280XP_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SC8280XP_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SC8280XP_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SC8280XP_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc0, NULL },
};
static struct qcom_icc_node qxs_nsp_xfr = {
.name = "qxs_nsp_xfr",
- .id = SC8280XP_SLAVE_NSP_XFR,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
- .id = SC8280XP_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nspb_gemnoc = {
.name = "qns_nspb_gemnoc",
- .id = SC8280XP_SLAVE_CDSPB_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC8280XP_MASTER_COMPUTE_NOC_1 },
+ .link_nodes = { &qnm_cmpnoc1, NULL },
};
static struct qcom_icc_node qxs_nspb_xfr = {
.name = "qxs_nspb_xfr",
- .id = SC8280XP_SLAVE_NSPB_XFR,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node service_nspb_noc = {
.name = "service_nspb_noc",
- .id = SC8280XP_SLAVE_SERVICE_NSPB_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SC8280XP_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC8280XP_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SC8280XP_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC8280XP_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SC8280XP_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1726,85 +1707,85 @@ static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
.nodes = { &qnm_gemnoc_cnoc,
- &qnm_gemnoc_pcie,
- &xs_pcie_0,
- &xs_pcie_1,
- &xs_pcie_2a,
- &xs_pcie_2b,
- &xs_pcie_3a,
- &xs_pcie_3b,
- &xs_pcie_4, NULL },
+ &qnm_gemnoc_pcie,
+ &xs_pcie_0,
+ &xs_pcie_1,
+ &xs_pcie_2a,
+ &xs_pcie_2b,
+ &xs_pcie_3a,
+ &xs_pcie_3b,
+ &xs_pcie_4, NULL },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
.nodes = { &qhs_ahb2phy0,
- &qhs_ahb2phy1,
- &qhs_ahb2phy2,
- &qhs_aoss,
- &qhs_apss,
- &qhs_camera_cfg,
- &qhs_clk_ctl,
- &qhs_compute0_cfg,
- &qhs_compute1_cfg,
- &qhs_cpr_cx,
- &qhs_cpr_mmcx,
- &qhs_cpr_mx,
- &qhs_cpr_nspcx,
- &qhs_crypto0_cfg,
- &qhs_cx_rdpm,
- &qhs_dcc_cfg,
- &qhs_display0_cfg,
- &qhs_display1_cfg,
- &qhs_emac0_cfg,
- &qhs_emac1_cfg,
- &qhs_gpuss_cfg,
- &qhs_hwkm,
- &qhs_imem_cfg,
- &qhs_ipa,
- &qhs_ipc_router,
- &qhs_lpass_cfg,
- &qhs_mx_rdpm,
- &qhs_mxc_rdpm,
- &qhs_pcie0_cfg,
- &qhs_pcie1_cfg,
- &qhs_pcie2a_cfg,
- &qhs_pcie2b_cfg,
- &qhs_pcie3a_cfg,
- &qhs_pcie3b_cfg,
- &qhs_pcie4_cfg,
- &qhs_pcie_rsc_cfg,
- &qhs_pdm,
- &qhs_pimem_cfg,
- &qhs_pka_wrapper_cfg,
- &qhs_pmu_wrapper_cfg,
- &qhs_qdss_cfg,
- &qhs_sdc2,
- &qhs_sdc4,
- &qhs_security,
- &qhs_smmuv3_cfg,
- &qhs_smss_cfg,
- &qhs_spss_cfg,
- &qhs_tcsr,
- &qhs_tlmm,
- &qhs_ufs_card_cfg,
- &qhs_ufs_mem_cfg,
- &qhs_usb3_0,
- &qhs_usb3_1,
- &qhs_usb3_mp,
- &qhs_usb4_host_0,
- &qhs_usb4_host_1,
- &qhs_venus_cfg,
- &qhs_vsense_ctrl_cfg,
- &qhs_vsense_ctrl_r_cfg,
- &qns_a1_noc_cfg,
- &qns_a2_noc_cfg,
- &qns_anoc_pcie_bridge_cfg,
- &qns_ddrss_cfg,
- &qns_mnoc_cfg,
- &qns_snoc_cfg,
- &qns_snoc_sf_bridge_cfg,
- &srvc_cnoc, NULL },
+ &qhs_ahb2phy1,
+ &qhs_ahb2phy2,
+ &qhs_aoss,
+ &qhs_apss,
+ &qhs_camera_cfg,
+ &qhs_clk_ctl,
+ &qhs_compute0_cfg,
+ &qhs_compute1_cfg,
+ &qhs_cpr_cx,
+ &qhs_cpr_mmcx,
+ &qhs_cpr_mx,
+ &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg,
+ &qhs_cx_rdpm,
+ &qhs_dcc_cfg,
+ &qhs_display0_cfg,
+ &qhs_display1_cfg,
+ &qhs_emac0_cfg,
+ &qhs_emac1_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_hwkm,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_ipc_router,
+ &qhs_lpass_cfg,
+ &qhs_mx_rdpm,
+ &qhs_mxc_rdpm,
+ &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg,
+ &qhs_pcie2a_cfg,
+ &qhs_pcie2b_cfg,
+ &qhs_pcie3a_cfg,
+ &qhs_pcie3b_cfg,
+ &qhs_pcie4_cfg,
+ &qhs_pcie_rsc_cfg,
+ &qhs_pdm,
+ &qhs_pimem_cfg,
+ &qhs_pka_wrapper_cfg,
+ &qhs_pmu_wrapper_cfg,
+ &qhs_qdss_cfg,
+ &qhs_sdc2,
+ &qhs_sdc4,
+ &qhs_security,
+ &qhs_smmuv3_cfg,
+ &qhs_smss_cfg,
+ &qhs_spss_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_ufs_card_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3_0,
+ &qhs_usb3_1,
+ &qhs_usb3_mp,
+ &qhs_usb4_host_0,
+ &qhs_usb4_host_1,
+ &qhs_venus_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_vsense_ctrl_r_cfg,
+ &qns_a1_noc_cfg,
+ &qns_a2_noc_cfg,
+ &qns_anoc_pcie_bridge_cfg,
+ &qns_ddrss_cfg,
+ &qns_mnoc_cfg,
+ &qns_snoc_cfg,
+ &qns_snoc_sf_bridge_cfg,
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_bcm bcm_cn2 = {
@@ -1976,6 +1957,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -2012,6 +1994,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -2034,6 +2017,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -2138,6 +2122,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -2154,6 +2139,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -2188,6 +2174,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -2211,6 +2198,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -2228,6 +2216,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -2259,6 +2248,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -2279,6 +2269,7 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_nspa_noc = {
+ .alloc_dyn_id = true,
.nodes = nspa_noc_nodes,
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
@@ -2299,6 +2290,7 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_nspb_noc = {
+ .alloc_dyn_id = true,
.nodes = nspb_noc_nodes,
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
.bcms = nspb_noc_bcms,
@@ -2328,6 +2320,7 @@ static struct qcom_icc_node * const system_noc_main_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_system_noc_main = {
+ .alloc_dyn_id = true,
.nodes = system_noc_main_nodes,
.num_nodes = ARRAY_SIZE(system_noc_main_nodes),
.bcms = system_noc_main_bcms,
diff --git a/drivers/interconnect/qcom/sc8280xp.h b/drivers/interconnect/qcom/sc8280xp.h
deleted file mode 100644
index c5c410fd5ec3c4d1bd0660091e1c4948fc019347..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sc8280xp.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2021, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H
-#define __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H
-
-#define SC8280XP_MASTER_GPU_TCU 0
-#define SC8280XP_MASTER_PCIE_TCU 1
-#define SC8280XP_MASTER_SYS_TCU 2
-#define SC8280XP_MASTER_APPSS_PROC 3
-/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
-#define SC8280XP_MASTER_LLCC 5
-#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6
-#define SC8280XP_MASTER_CDSP_NOC_CFG 7
-#define SC8280XP_MASTER_CDSPB_NOC_CFG 8
-#define SC8280XP_MASTER_QDSS_BAM 9
-#define SC8280XP_MASTER_QSPI_0 10
-#define SC8280XP_MASTER_QUP_0 11
-#define SC8280XP_MASTER_QUP_1 12
-#define SC8280XP_MASTER_QUP_2 13
-#define SC8280XP_MASTER_A1NOC_CFG 14
-#define SC8280XP_MASTER_A2NOC_CFG 15
-#define SC8280XP_MASTER_A1NOC_SNOC 16
-#define SC8280XP_MASTER_A2NOC_SNOC 17
-#define SC8280XP_MASTER_USB_NOC_SNOC 18
-#define SC8280XP_MASTER_CAMNOC_HF 19
-#define SC8280XP_MASTER_COMPUTE_NOC 20
-#define SC8280XP_MASTER_COMPUTE_NOC_1 21
-#define SC8280XP_MASTER_CNOC_DC_NOC 22
-#define SC8280XP_MASTER_GEM_NOC_CFG 23
-#define SC8280XP_MASTER_GEM_NOC_CNOC 24
-#define SC8280XP_MASTER_GEM_NOC_PCIE_SNOC 25
-#define SC8280XP_MASTER_GFX3D 26
-#define SC8280XP_MASTER_LPASS_ANOC 27
-#define SC8280XP_MASTER_MDP0 28
-#define SC8280XP_MASTER_MDP1 29
-#define SC8280XP_MASTER_MDP_CORE1_0 30
-#define SC8280XP_MASTER_MDP_CORE1_1 31
-#define SC8280XP_MASTER_CNOC_MNOC_CFG 32
-#define SC8280XP_MASTER_MNOC_HF_MEM_NOC 33
-#define SC8280XP_MASTER_MNOC_SF_MEM_NOC 34
-#define SC8280XP_MASTER_ANOC_PCIE_GEM_NOC 35
-#define SC8280XP_MASTER_ROTATOR 36
-#define SC8280XP_MASTER_ROTATOR_1 37
-#define SC8280XP_MASTER_SNOC_CFG 38
-#define SC8280XP_MASTER_SNOC_GC_MEM_NOC 39
-#define SC8280XP_MASTER_SNOC_SF_MEM_NOC 40
-#define SC8280XP_MASTER_VIDEO_P0 41
-#define SC8280XP_MASTER_VIDEO_P1 42
-#define SC8280XP_MASTER_VIDEO_PROC 43
-#define SC8280XP_MASTER_QUP_CORE_0 44
-#define SC8280XP_MASTER_QUP_CORE_1 45
-#define SC8280XP_MASTER_QUP_CORE_2 46
-#define SC8280XP_MASTER_CAMNOC_ICP 47
-#define SC8280XP_MASTER_CAMNOC_SF 48
-#define SC8280XP_MASTER_CRYPTO 49
-#define SC8280XP_MASTER_IPA 50
-#define SC8280XP_MASTER_LPASS_PROC 51
-#define SC8280XP_MASTER_CDSP_PROC 52
-#define SC8280XP_MASTER_CDSP_PROC_B 53
-#define SC8280XP_MASTER_PIMEM 54
-#define SC8280XP_MASTER_SENSORS_PROC 55
-#define SC8280XP_MASTER_SP 56
-#define SC8280XP_MASTER_EMAC 57
-#define SC8280XP_MASTER_EMAC_1 58
-#define SC8280XP_MASTER_GIC 59
-#define SC8280XP_MASTER_PCIE_0 60
-#define SC8280XP_MASTER_PCIE_1 61
-#define SC8280XP_MASTER_PCIE_2A 62
-#define SC8280XP_MASTER_PCIE_2B 63
-#define SC8280XP_MASTER_PCIE_3A 64
-#define SC8280XP_MASTER_PCIE_3B 65
-#define SC8280XP_MASTER_PCIE_4 66
-#define SC8280XP_MASTER_QDSS_ETR 67
-#define SC8280XP_MASTER_SDCC_2 68
-#define SC8280XP_MASTER_SDCC_4 69
-#define SC8280XP_MASTER_UFS_CARD 70
-#define SC8280XP_MASTER_UFS_MEM 71
-#define SC8280XP_MASTER_USB3_0 72
-#define SC8280XP_MASTER_USB3_1 73
-#define SC8280XP_MASTER_USB3_MP 74
-#define SC8280XP_MASTER_USB4_0 75
-#define SC8280XP_MASTER_USB4_1 76
-#define SC8280XP_SLAVE_EBI1 512
-/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
-#define SC8280XP_SLAVE_AHB2PHY_0 514
-#define SC8280XP_SLAVE_AHB2PHY_1 515
-#define SC8280XP_SLAVE_AHB2PHY_2 516
-#define SC8280XP_SLAVE_AOSS 517
-#define SC8280XP_SLAVE_APPSS 518
-#define SC8280XP_SLAVE_CAMERA_CFG 519
-#define SC8280XP_SLAVE_CLK_CTL 520
-#define SC8280XP_SLAVE_CDSP_CFG 521
-#define SC8280XP_SLAVE_CDSP1_CFG 522
-#define SC8280XP_SLAVE_RBCPR_CX_CFG 523
-#define SC8280XP_SLAVE_RBCPR_MMCX_CFG 524
-#define SC8280XP_SLAVE_RBCPR_MX_CFG 525
-#define SC8280XP_SLAVE_CPR_NSPCX 526
-#define SC8280XP_SLAVE_CRYPTO_0_CFG 527
-#define SC8280XP_SLAVE_CX_RDPM 528
-#define SC8280XP_SLAVE_DCC_CFG 529
-#define SC8280XP_SLAVE_DISPLAY_CFG 530
-#define SC8280XP_SLAVE_DISPLAY1_CFG 531
-#define SC8280XP_SLAVE_EMAC_CFG 532
-#define SC8280XP_SLAVE_EMAC1_CFG 533
-#define SC8280XP_SLAVE_GFX3D_CFG 534
-#define SC8280XP_SLAVE_HWKM 535
-#define SC8280XP_SLAVE_IMEM_CFG 536
-#define SC8280XP_SLAVE_IPA_CFG 537
-#define SC8280XP_SLAVE_IPC_ROUTER_CFG 538
-#define SC8280XP_SLAVE_LLCC_CFG 539
-#define SC8280XP_SLAVE_LPASS 540
-#define SC8280XP_SLAVE_LPASS_CORE_CFG 541
-#define SC8280XP_SLAVE_LPASS_LPI_CFG 542
-#define SC8280XP_SLAVE_LPASS_MPU_CFG 543
-#define SC8280XP_SLAVE_LPASS_TOP_CFG 544
-#define SC8280XP_SLAVE_MX_RDPM 545
-#define SC8280XP_SLAVE_MXC_RDPM 546
-#define SC8280XP_SLAVE_PCIE_0_CFG 547
-#define SC8280XP_SLAVE_PCIE_1_CFG 548
-#define SC8280XP_SLAVE_PCIE_2A_CFG 549
-#define SC8280XP_SLAVE_PCIE_2B_CFG 550
-#define SC8280XP_SLAVE_PCIE_3A_CFG 551
-#define SC8280XP_SLAVE_PCIE_3B_CFG 552
-#define SC8280XP_SLAVE_PCIE_4_CFG 553
-#define SC8280XP_SLAVE_PCIE_RSC_CFG 554
-#define SC8280XP_SLAVE_PDM 555
-#define SC8280XP_SLAVE_PIMEM_CFG 556
-#define SC8280XP_SLAVE_PKA_WRAPPER_CFG 557
-#define SC8280XP_SLAVE_PMU_WRAPPER_CFG 558
-#define SC8280XP_SLAVE_QDSS_CFG 559
-#define SC8280XP_SLAVE_QSPI_0 560
-#define SC8280XP_SLAVE_QUP_0 561
-#define SC8280XP_SLAVE_QUP_1 562
-#define SC8280XP_SLAVE_QUP_2 563
-#define SC8280XP_SLAVE_SDCC_2 564
-#define SC8280XP_SLAVE_SDCC_4 565
-#define SC8280XP_SLAVE_SECURITY 566
-#define SC8280XP_SLAVE_SMMUV3_CFG 567
-#define SC8280XP_SLAVE_SMSS_CFG 568
-#define SC8280XP_SLAVE_SPSS_CFG 569
-#define SC8280XP_SLAVE_TCSR 570
-#define SC8280XP_SLAVE_TLMM 571
-#define SC8280XP_SLAVE_UFS_CARD_CFG 572
-#define SC8280XP_SLAVE_UFS_MEM_CFG 573
-#define SC8280XP_SLAVE_USB3_0 574
-#define SC8280XP_SLAVE_USB3_1 575
-#define SC8280XP_SLAVE_USB3_MP 576
-#define SC8280XP_SLAVE_USB4_0 577
-#define SC8280XP_SLAVE_USB4_1 578
-#define SC8280XP_SLAVE_VENUS_CFG 579
-#define SC8280XP_SLAVE_VSENSE_CTRL_CFG 580
-#define SC8280XP_SLAVE_VSENSE_CTRL_R_CFG 581
-#define SC8280XP_SLAVE_A1NOC_CFG 582
-#define SC8280XP_SLAVE_A1NOC_SNOC 583
-#define SC8280XP_SLAVE_A2NOC_CFG 584
-#define SC8280XP_SLAVE_A2NOC_SNOC 585
-#define SC8280XP_SLAVE_USB_NOC_SNOC 586
-#define SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG 587
-#define SC8280XP_SLAVE_DDRSS_CFG 588
-#define SC8280XP_SLAVE_GEM_NOC_CNOC 589
-#define SC8280XP_SLAVE_GEM_NOC_CFG 590
-#define SC8280XP_SLAVE_SNOC_GEM_NOC_GC 591
-#define SC8280XP_SLAVE_SNOC_GEM_NOC_SF 592
-#define SC8280XP_SLAVE_LLCC 593
-#define SC8280XP_SLAVE_MNOC_HF_MEM_NOC 594
-#define SC8280XP_SLAVE_MNOC_SF_MEM_NOC 595
-#define SC8280XP_SLAVE_CNOC_MNOC_CFG 596
-#define SC8280XP_SLAVE_CDSP_MEM_NOC 597
-#define SC8280XP_SLAVE_CDSPB_MEM_NOC 598
-#define SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 599
-#define SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC 600
-#define SC8280XP_SLAVE_SNOC_CFG 601
-#define SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG 602
-#define SC8280XP_SLAVE_LPASS_SNOC 603
-#define SC8280XP_SLAVE_QUP_CORE_0 604
-#define SC8280XP_SLAVE_QUP_CORE_1 605
-#define SC8280XP_SLAVE_QUP_CORE_2 606
-#define SC8280XP_SLAVE_IMEM 607
-#define SC8280XP_SLAVE_NSP_XFR 608
-#define SC8280XP_SLAVE_NSPB_XFR 609
-#define SC8280XP_SLAVE_PIMEM 610
-#define SC8280XP_SLAVE_SERVICE_NSP_NOC 611
-#define SC8280XP_SLAVE_SERVICE_NSPB_NOC 612
-#define SC8280XP_SLAVE_SERVICE_A1NOC 613
-#define SC8280XP_SLAVE_SERVICE_A2NOC 614
-#define SC8280XP_SLAVE_SERVICE_CNOC 615
-#define SC8280XP_SLAVE_SERVICE_GEM_NOC_1 616
-#define SC8280XP_SLAVE_SERVICE_MNOC 617
-#define SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC 618
-#define SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC 619
-#define SC8280XP_SLAVE_SERVICE_GEM_NOC_2 620
-#define SC8280XP_SLAVE_SERVICE_SNOC 621
-#define SC8280XP_SLAVE_SERVICE_GEM_NOC 622
-#define SC8280XP_SLAVE_PCIE_0 623
-#define SC8280XP_SLAVE_PCIE_1 624
-#define SC8280XP_SLAVE_PCIE_2A 625
-#define SC8280XP_SLAVE_PCIE_2B 626
-#define SC8280XP_SLAVE_PCIE_3A 627
-#define SC8280XP_SLAVE_PCIE_3B 628
-#define SC8280XP_SLAVE_PCIE_4 629
-#define SC8280XP_SLAVE_QDSS_STM 630
-#define SC8280XP_SLAVE_SMSS 631
-#define SC8280XP_SLAVE_TCU 632
-
-#endif
-
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 08/28] interconnect: qcom: sdm845: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (6 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 07/28] interconnect: qcom: sc8280xp: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 09/28] interconnect: qcom: sm8250: " Dmitry Baryshkov
` (20 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sdm845.c | 908 ++++++++++++++++++-------------------
drivers/interconnect/qcom/sdm845.h | 140 ------
2 files changed, 438 insertions(+), 610 deletions(-)
diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c
index 9d5bd2c9943b620b41d70e9c56f8ddc32c75d5a7..b37de30a9e8f309510818e2619aab2c451f50fe0 100644
--- a/drivers/interconnect/qcom/sdm845.c
+++ b/drivers/interconnect/qcom/sdm845.c
@@ -14,1253 +14,1213 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sdm845.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qhm_tsif;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_card;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_pcie_0;
+static struct qcom_icc_node qhm_a2noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qnm_cnoc;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node xm_usb3_1;
+static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node qxm_camnoc_hf1_uncomp;
+static struct qcom_icc_node qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node qhm_spdm;
+static struct qcom_icc_node qhm_tic;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qhm_cnoc;
+static struct qcom_icc_node acm_l3;
+static struct qcom_icc_node pm_gnoc_cfg;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node acm_tcu;
+static struct qcom_icc_node qhm_memnoc_cfg;
+static struct qcom_icc_node qnm_apps;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_gpu;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qxm_camnoc_hf0;
+static struct qcom_icc_node qxm_camnoc_hf1;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_mdp1;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node qxm_venus0;
+static struct qcom_icc_node qxm_venus1;
+static struct qcom_icc_node qxm_venus_arm9;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gladiator_sodv;
+static struct qcom_icc_node qnm_memnoc;
+static struct qcom_icc_node qnm_pcie_anoc;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_pcie_a1noc_snoc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_snoc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_camnoc_uncomp;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_a2_noc_cfg;
+static struct qcom_icc_node qhs_aop;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_dsp_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_glm;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie_gen3_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_phy_refgen_south;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qupv3_north;
+static struct qcom_icc_node qhs_qupv3_south;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_spdm;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm_north;
+static struct qcom_icc_node qhs_tlmm_south;
+static struct qcom_icc_node qhs_tsif;
+static struct qcom_icc_node qhs_ufs_card_cfg;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_usb3_1;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_memnoc;
+static struct qcom_icc_node qns_gladiator_sodv;
+static struct qcom_icc_node qns_gnoc_memnoc;
+static struct qcom_icc_node srvc_gnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qns_apps_io;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_memnoc_snoc;
+static struct qcom_icc_node srvc_memnoc;
+static struct qcom_icc_node qns2_mem_noc;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_memnoc_gc;
+static struct qcom_icc_node qns_memnoc_sf;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pcie;
+static struct qcom_icc_node qxs_pcie_gen3;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qhm_a1noc_cfg = {
.name = "qhm_a1noc_cfg",
- .id = SDM845_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SDM845_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_tsif = {
.name = "qhm_tsif",
- .id = SDM845_MASTER_TSIF,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SDM845_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SDM845_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_card = {
.name = "xm_ufs_card",
- .id = SDM845_MASTER_UFS_CARD,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SDM845_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie_0 = {
.name = "xm_pcie_0",
- .id = SDM845_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC },
+ .link_nodes = { &qns_pcie_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_a2noc_cfg = {
.name = "qhm_a2noc_cfg",
- .id = SDM845_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SDM845_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SDM845_MASTER_BLSP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
- .id = SDM845_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SDM845_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SDM845_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SDM845_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_ANOC_PCIE_SNOC },
+ .link_nodes = { &qns_pcie_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SDM845_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SDM845_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
- .id = SDM845_MASTER_USB3_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
.name = "qxm_camnoc_hf0_uncomp",
- .id = SDM845_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
.name = "qxm_camnoc_hf1_uncomp",
- .id = SDM845_MASTER_CAMNOC_HF1_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
.name = "qxm_camnoc_sf_uncomp",
- .id = SDM845_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qhm_spdm = {
.name = "qhm_spdm",
- .id = SDM845_MASTER_SPDM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_CNOC_A2NOC },
+ .link_nodes = { &qns_cnoc_a2noc, NULL },
};
static struct qcom_icc_node qhm_tic = {
.name = "qhm_tic",
- .id = SDM845_MASTER_TIC,
- .channels = 1,
- .buswidth = 4,
- .num_links = 43,
- .links = { SDM845_SLAVE_A1NOC_CFG,
- SDM845_SLAVE_A2NOC_CFG,
- SDM845_SLAVE_AOP,
- SDM845_SLAVE_AOSS,
- SDM845_SLAVE_CAMERA_CFG,
- SDM845_SLAVE_CLK_CTL,
- SDM845_SLAVE_CDSP_CFG,
- SDM845_SLAVE_RBCPR_CX_CFG,
- SDM845_SLAVE_CRYPTO_0_CFG,
- SDM845_SLAVE_DCC_CFG,
- SDM845_SLAVE_CNOC_DDRSS,
- SDM845_SLAVE_DISPLAY_CFG,
- SDM845_SLAVE_GLM,
- SDM845_SLAVE_GFX3D_CFG,
- SDM845_SLAVE_IMEM_CFG,
- SDM845_SLAVE_IPA_CFG,
- SDM845_SLAVE_CNOC_MNOC_CFG,
- SDM845_SLAVE_PCIE_0_CFG,
- SDM845_SLAVE_PCIE_1_CFG,
- SDM845_SLAVE_PDM,
- SDM845_SLAVE_SOUTH_PHY_CFG,
- SDM845_SLAVE_PIMEM_CFG,
- SDM845_SLAVE_PRNG,
- SDM845_SLAVE_QDSS_CFG,
- SDM845_SLAVE_BLSP_2,
- SDM845_SLAVE_BLSP_1,
- SDM845_SLAVE_SDCC_2,
- SDM845_SLAVE_SDCC_4,
- SDM845_SLAVE_SNOC_CFG,
- SDM845_SLAVE_SPDM_WRAPPER,
- SDM845_SLAVE_SPSS_CFG,
- SDM845_SLAVE_TCSR,
- SDM845_SLAVE_TLMM_NORTH,
- SDM845_SLAVE_TLMM_SOUTH,
- SDM845_SLAVE_TSIF,
- SDM845_SLAVE_UFS_CARD_CFG,
- SDM845_SLAVE_UFS_MEM_CFG,
- SDM845_SLAVE_USB3_0,
- SDM845_SLAVE_USB3_1,
- SDM845_SLAVE_VENUS_CFG,
- SDM845_SLAVE_VSENSE_CTRL_CFG,
- SDM845_SLAVE_CNOC_A2NOC,
- SDM845_SLAVE_SERVICE_CNOC
- },
+ .channels = 1,
+ .buswidth = 4,
+ .link_nodes = { &qhs_a1_noc_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_aop,
+ &qhs_aoss,
+ &qhs_camera_cfg,
+ &qhs_clk_ctl,
+ &qhs_compute_dsp_cfg,
+ &qhs_cpr_cx,
+ &qhs_crypto0_cfg,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_display_cfg,
+ &qhs_glm,
+ &qhs_gpuss_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mnoc_cfg,
+ &qhs_pcie0_cfg,
+ &qhs_pcie_gen3_cfg,
+ &qhs_pdm,
+ &qhs_phy_refgen_south,
+ &qhs_pimem_cfg,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qupv3_north,
+ &qhs_qupv3_south,
+ &qhs_sdc2,
+ &qhs_sdc4,
+ &qhs_snoc_cfg,
+ &qhs_spdm,
+ &qhs_spss_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm_north,
+ &qhs_tlmm_south,
+ &qhs_tsif,
+ &qhs_ufs_card_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3_0,
+ &qhs_usb3_1,
+ &qhs_venus_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &qns_cnoc_a2noc,
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = SDM845_MASTER_SNOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 42,
- .links = { SDM845_SLAVE_A1NOC_CFG,
- SDM845_SLAVE_A2NOC_CFG,
- SDM845_SLAVE_AOP,
- SDM845_SLAVE_AOSS,
- SDM845_SLAVE_CAMERA_CFG,
- SDM845_SLAVE_CLK_CTL,
- SDM845_SLAVE_CDSP_CFG,
- SDM845_SLAVE_RBCPR_CX_CFG,
- SDM845_SLAVE_CRYPTO_0_CFG,
- SDM845_SLAVE_DCC_CFG,
- SDM845_SLAVE_CNOC_DDRSS,
- SDM845_SLAVE_DISPLAY_CFG,
- SDM845_SLAVE_GLM,
- SDM845_SLAVE_GFX3D_CFG,
- SDM845_SLAVE_IMEM_CFG,
- SDM845_SLAVE_IPA_CFG,
- SDM845_SLAVE_CNOC_MNOC_CFG,
- SDM845_SLAVE_PCIE_0_CFG,
- SDM845_SLAVE_PCIE_1_CFG,
- SDM845_SLAVE_PDM,
- SDM845_SLAVE_SOUTH_PHY_CFG,
- SDM845_SLAVE_PIMEM_CFG,
- SDM845_SLAVE_PRNG,
- SDM845_SLAVE_QDSS_CFG,
- SDM845_SLAVE_BLSP_2,
- SDM845_SLAVE_BLSP_1,
- SDM845_SLAVE_SDCC_2,
- SDM845_SLAVE_SDCC_4,
- SDM845_SLAVE_SNOC_CFG,
- SDM845_SLAVE_SPDM_WRAPPER,
- SDM845_SLAVE_SPSS_CFG,
- SDM845_SLAVE_TCSR,
- SDM845_SLAVE_TLMM_NORTH,
- SDM845_SLAVE_TLMM_SOUTH,
- SDM845_SLAVE_TSIF,
- SDM845_SLAVE_UFS_CARD_CFG,
- SDM845_SLAVE_UFS_MEM_CFG,
- SDM845_SLAVE_USB3_0,
- SDM845_SLAVE_USB3_1,
- SDM845_SLAVE_VENUS_CFG,
- SDM845_SLAVE_VSENSE_CTRL_CFG,
- SDM845_SLAVE_SERVICE_CNOC
- },
+ .link_nodes = { &qhs_a1_noc_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_aop,
+ &qhs_aoss,
+ &qhs_camera_cfg,
+ &qhs_clk_ctl,
+ &qhs_compute_dsp_cfg,
+ &qhs_cpr_cx,
+ &qhs_crypto0_cfg,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_display_cfg,
+ &qhs_glm,
+ &qhs_gpuss_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mnoc_cfg,
+ &qhs_pcie0_cfg,
+ &qhs_pcie_gen3_cfg,
+ &qhs_pdm,
+ &qhs_phy_refgen_south,
+ &qhs_pimem_cfg,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qupv3_north,
+ &qhs_qupv3_south,
+ &qhs_sdc2,
+ &qhs_sdc4,
+ &qhs_snoc_cfg,
+ &qhs_spdm,
+ &qhs_spss_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm_north,
+ &qhs_tlmm_south,
+ &qhs_tsif,
+ &qhs_ufs_card_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3_0,
+ &qhs_usb3_1,
+ &qhs_venus_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SDM845_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 43,
- .links = { SDM845_SLAVE_A1NOC_CFG,
- SDM845_SLAVE_A2NOC_CFG,
- SDM845_SLAVE_AOP,
- SDM845_SLAVE_AOSS,
- SDM845_SLAVE_CAMERA_CFG,
- SDM845_SLAVE_CLK_CTL,
- SDM845_SLAVE_CDSP_CFG,
- SDM845_SLAVE_RBCPR_CX_CFG,
- SDM845_SLAVE_CRYPTO_0_CFG,
- SDM845_SLAVE_DCC_CFG,
- SDM845_SLAVE_CNOC_DDRSS,
- SDM845_SLAVE_DISPLAY_CFG,
- SDM845_SLAVE_GLM,
- SDM845_SLAVE_GFX3D_CFG,
- SDM845_SLAVE_IMEM_CFG,
- SDM845_SLAVE_IPA_CFG,
- SDM845_SLAVE_CNOC_MNOC_CFG,
- SDM845_SLAVE_PCIE_0_CFG,
- SDM845_SLAVE_PCIE_1_CFG,
- SDM845_SLAVE_PDM,
- SDM845_SLAVE_SOUTH_PHY_CFG,
- SDM845_SLAVE_PIMEM_CFG,
- SDM845_SLAVE_PRNG,
- SDM845_SLAVE_QDSS_CFG,
- SDM845_SLAVE_BLSP_2,
- SDM845_SLAVE_BLSP_1,
- SDM845_SLAVE_SDCC_2,
- SDM845_SLAVE_SDCC_4,
- SDM845_SLAVE_SNOC_CFG,
- SDM845_SLAVE_SPDM_WRAPPER,
- SDM845_SLAVE_SPSS_CFG,
- SDM845_SLAVE_TCSR,
- SDM845_SLAVE_TLMM_NORTH,
- SDM845_SLAVE_TLMM_SOUTH,
- SDM845_SLAVE_TSIF,
- SDM845_SLAVE_UFS_CARD_CFG,
- SDM845_SLAVE_UFS_MEM_CFG,
- SDM845_SLAVE_USB3_0,
- SDM845_SLAVE_USB3_1,
- SDM845_SLAVE_VENUS_CFG,
- SDM845_SLAVE_VSENSE_CTRL_CFG,
- SDM845_SLAVE_CNOC_A2NOC,
- SDM845_SLAVE_SERVICE_CNOC
- },
+ .link_nodes = { &qhs_a1_noc_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_aop,
+ &qhs_aoss,
+ &qhs_camera_cfg,
+ &qhs_clk_ctl,
+ &qhs_compute_dsp_cfg,
+ &qhs_cpr_cx,
+ &qhs_crypto0_cfg,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_display_cfg,
+ &qhs_glm,
+ &qhs_gpuss_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mnoc_cfg,
+ &qhs_pcie0_cfg,
+ &qhs_pcie_gen3_cfg,
+ &qhs_pdm,
+ &qhs_phy_refgen_south,
+ &qhs_pimem_cfg,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qupv3_north,
+ &qhs_qupv3_south,
+ &qhs_sdc2,
+ &qhs_sdc4,
+ &qhs_snoc_cfg,
+ &qhs_spdm,
+ &qhs_spss_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm_north,
+ &qhs_tlmm_south,
+ &qhs_tsif,
+ &qhs_ufs_card_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3_0,
+ &qhs_usb3_1,
+ &qhs_venus_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &qns_cnoc_a2noc,
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_node qhm_cnoc = {
.name = "qhm_cnoc",
- .id = SDM845_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SDM845_SLAVE_LLCC_CFG,
- SDM845_SLAVE_MEM_NOC_CFG
- },
+ .link_nodes = { &qhs_llcc,
+ &qhs_memnoc, NULL },
};
static struct qcom_icc_node acm_l3 = {
.name = "acm_l3",
- .id = SDM845_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SDM845_SLAVE_GNOC_SNOC,
- SDM845_SLAVE_GNOC_MEM_NOC,
- SDM845_SLAVE_SERVICE_GNOC
- },
+ .link_nodes = { &qns_gladiator_sodv,
+ &qns_gnoc_memnoc,
+ &srvc_gnoc, NULL },
};
static struct qcom_icc_node pm_gnoc_cfg = {
.name = "pm_gnoc_cfg",
- .id = SDM845_MASTER_GNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_SERVICE_GNOC },
+ .link_nodes = { &srvc_gnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SDM845_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
- .id = SDM845_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
- .num_links = 3,
- .links = { SDM845_SLAVE_MEM_NOC_GNOC,
- SDM845_SLAVE_LLCC,
- SDM845_SLAVE_MEM_NOC_SNOC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc,
+ &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_node qhm_memnoc_cfg = {
.name = "qhm_memnoc_cfg",
- .id = SDM845_MASTER_MEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
- SDM845_SLAVE_SERVICE_MEM_NOC
- },
+ .link_nodes = { &qhs_mdsp_ms_mpu_cfg,
+ &srvc_memnoc, NULL },
};
static struct qcom_icc_node qnm_apps = {
.name = "qnm_apps",
- .id = SDM845_MASTER_GNOC_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SDM845_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SDM845_SLAVE_MEM_NOC_GNOC,
- SDM845_SLAVE_LLCC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SDM845_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 3,
- .links = { SDM845_SLAVE_MEM_NOC_GNOC,
- SDM845_SLAVE_LLCC,
- SDM845_SLAVE_MEM_NOC_SNOC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc,
+ &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SDM845_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SDM845_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SDM845_SLAVE_MEM_NOC_GNOC,
- SDM845_SLAVE_LLCC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qxm_gpu = {
.name = "qxm_gpu",
- .id = SDM845_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SDM845_SLAVE_MEM_NOC_GNOC,
- SDM845_SLAVE_LLCC,
- SDM845_SLAVE_MEM_NOC_SNOC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc,
+ &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = SDM845_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0 = {
.name = "qxm_camnoc_hf0",
- .id = SDM845_MASTER_CAMNOC_HF0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1 = {
.name = "qxm_camnoc_hf1",
- .id = SDM845_MASTER_CAMNOC_HF1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SDM845_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SDM845_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_mdp1 = {
.name = "qxm_mdp1",
- .id = SDM845_MASTER_MDP1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = SDM845_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus0 = {
.name = "qxm_venus0",
- .id = SDM845_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus1 = {
.name = "qxm_venus1",
- .id = SDM845_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus_arm9 = {
.name = "qxm_venus_arm9",
- .id = SDM845_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SDM845_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SDM845_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SDM845_SLAVE_APPSS,
- SDM845_SLAVE_SNOC_CNOC,
- SDM845_SLAVE_SNOC_MEM_NOC_SF,
- SDM845_SLAVE_IMEM,
- SDM845_SLAVE_PIMEM,
- SDM845_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qhs_apss,
+ &qns_cnoc,
+ &qns_memnoc_sf,
+ &qxs_imem,
+ &qxs_pimem,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SDM845_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 9,
- .links = { SDM845_SLAVE_APPSS,
- SDM845_SLAVE_SNOC_CNOC,
- SDM845_SLAVE_SNOC_MEM_NOC_SF,
- SDM845_SLAVE_IMEM,
- SDM845_SLAVE_PCIE_0,
- SDM845_SLAVE_PCIE_1,
- SDM845_SLAVE_PIMEM,
- SDM845_SLAVE_QDSS_STM,
- SDM845_SLAVE_TCU
- },
+ .link_nodes = { &qhs_apss,
+ &qns_cnoc,
+ &qns_memnoc_sf,
+ &qxs_imem,
+ &qxs_pcie,
+ &qxs_pcie_gen3,
+ &qxs_pimem,
+ &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gladiator_sodv = {
.name = "qnm_gladiator_sodv",
- .id = SDM845_MASTER_GNOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 8,
- .links = { SDM845_SLAVE_APPSS,
- SDM845_SLAVE_SNOC_CNOC,
- SDM845_SLAVE_IMEM,
- SDM845_SLAVE_PCIE_0,
- SDM845_SLAVE_PCIE_1,
- SDM845_SLAVE_PIMEM,
- SDM845_SLAVE_QDSS_STM,
- SDM845_SLAVE_TCU
- },
+ .link_nodes = { &qhs_apss,
+ &qns_cnoc,
+ &qxs_imem,
+ &qxs_pcie,
+ &qxs_pcie_gen3,
+ &qxs_pimem,
+ &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_memnoc = {
.name = "qnm_memnoc",
- .id = SDM845_MASTER_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 5,
- .links = { SDM845_SLAVE_APPSS,
- SDM845_SLAVE_SNOC_CNOC,
- SDM845_SLAVE_IMEM,
- SDM845_SLAVE_PIMEM,
- SDM845_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qhs_apss,
+ &qns_cnoc,
+ &qxs_imem,
+ &qxs_pimem,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_pcie_anoc = {
.name = "qnm_pcie_anoc",
- .id = SDM845_MASTER_ANOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 5,
- .links = { SDM845_SLAVE_APPSS,
- SDM845_SLAVE_SNOC_CNOC,
- SDM845_SLAVE_SNOC_MEM_NOC_SF,
- SDM845_SLAVE_IMEM,
- SDM845_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qhs_apss,
+ &qns_cnoc,
+ &qns_memnoc_sf,
+ &qxs_imem,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SDM845_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC,
- SDM845_SLAVE_IMEM
- },
+ .link_nodes = { &qns_memnoc_gc,
+ &qxs_imem, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SDM845_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC,
- SDM845_SLAVE_IMEM
- },
+ .link_nodes = { &qns_memnoc_gc,
+ &qxs_imem, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SDM845_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM845_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SDM845_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { 0 },
+ .link_nodes = { 0, NULL },
};
static struct qcom_icc_node qns_pcie_a1noc_snoc = {
.name = "qns_pcie_a1noc_snoc",
- .id = SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM845_MASTER_ANOC_PCIE_SNOC },
+ .link_nodes = { &qnm_pcie_anoc, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SDM845_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM845_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qns_pcie_snoc = {
.name = "qns_pcie_snoc",
- .id = SDM845_SLAVE_ANOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM845_MASTER_ANOC_PCIE_SNOC },
+ .link_nodes = { &qnm_pcie_anoc, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SDM845_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_camnoc_uncomp = {
.name = "qns_camnoc_uncomp",
- .id = SDM845_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = SDM845_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qhs_a2_noc_cfg = {
.name = "qhs_a2_noc_cfg",
- .id = SDM845_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_MASTER_A2NOC_CFG },
+ .link_nodes = { &qhm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
- .id = SDM845_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SDM845_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SDM845_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SDM845_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_dsp_cfg = {
.name = "qhs_compute_dsp_cfg",
- .id = SDM845_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SDM845_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SDM845_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SDM845_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc, NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SDM845_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SDM845_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_glm = {
.name = "qhs_glm",
- .id = SDM845_SLAVE_GLM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SDM845_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SDM845_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SDM845_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = SDM845_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SDM845_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_gen3_cfg = {
.name = "qhs_pcie_gen3_cfg",
- .id = SDM845_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SDM845_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_phy_refgen_south = {
.name = "qhs_phy_refgen_south",
- .id = SDM845_SLAVE_SOUTH_PHY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SDM845_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SDM845_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SDM845_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_north = {
.name = "qhs_qupv3_north",
- .id = SDM845_SLAVE_BLSP_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_south = {
.name = "qhs_qupv3_south",
- .id = SDM845_SLAVE_BLSP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SDM845_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SDM845_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SDM845_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_spdm = {
.name = "qhs_spdm",
- .id = SDM845_SLAVE_SPDM_WRAPPER,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SDM845_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SDM845_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_north = {
.name = "qhs_tlmm_north",
- .id = SDM845_SLAVE_TLMM_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_south = {
.name = "qhs_tlmm_south",
- .id = SDM845_SLAVE_TLMM_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tsif = {
.name = "qhs_tsif",
- .id = SDM845_SLAVE_TSIF,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_card_cfg = {
.name = "qhs_ufs_card_cfg",
- .id = SDM845_SLAVE_UFS_CARD_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SDM845_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SDM845_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_1 = {
.name = "qhs_usb3_1",
- .id = SDM845_SLAVE_USB3_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SDM845_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SDM845_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = SDM845_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc, NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SDM845_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SDM845_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_memnoc = {
.name = "qhs_memnoc",
- .id = SDM845_SLAVE_MEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM845_MASTER_MEM_NOC_CFG },
+ .link_nodes = { &qhm_memnoc_cfg, NULL },
};
static struct qcom_icc_node qns_gladiator_sodv = {
.name = "qns_gladiator_sodv",
- .id = SDM845_SLAVE_GNOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_MASTER_GNOC_SNOC },
+ .link_nodes = { &qnm_gladiator_sodv, NULL },
};
static struct qcom_icc_node qns_gnoc_memnoc = {
.name = "qns_gnoc_memnoc",
- .id = SDM845_SLAVE_GNOC_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_MASTER_GNOC_MEM_NOC },
+ .link_nodes = { &qnm_apps, NULL },
};
static struct qcom_icc_node srvc_gnoc = {
.name = "srvc_gnoc",
- .id = SDM845_SLAVE_SERVICE_GNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SDM845_SLAVE_EBI1,
.channels = 4,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_apps_io = {
.name = "qns_apps_io",
- .id = SDM845_SLAVE_MEM_NOC_GNOC,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SDM845_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM845_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_memnoc_snoc = {
.name = "qns_memnoc_snoc",
- .id = SDM845_SLAVE_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_MASTER_MEM_NOC_SNOC },
+ .link_nodes = { &qnm_memnoc, NULL },
};
static struct qcom_icc_node srvc_memnoc = {
.name = "srvc_memnoc",
- .id = SDM845_SLAVE_SERVICE_MEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns2_mem_noc = {
.name = "qns2_mem_noc",
- .id = SDM845_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SDM845_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM845_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SDM845_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SDM845_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = SDM845_SLAVE_SNOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_MASTER_SNOC_CNOC },
+ .link_nodes = { &qnm_snoc, NULL },
};
static struct qcom_icc_node qns_memnoc_gc = {
.name = "qns_memnoc_gc",
- .id = SDM845_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM845_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_memnoc_sf = {
.name = "qns_memnoc_sf",
- .id = SDM845_SLAVE_SNOC_MEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM845_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SDM845_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pcie = {
.name = "qxs_pcie",
- .id = SDM845_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pcie_gen3 = {
.name = "qxs_pcie_gen3",
- .id = SDM845_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SDM845_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SDM845_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SDM845_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SDM845_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1504,6 +1464,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1533,6 +1494,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1594,6 +1556,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1610,6 +1573,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1628,6 +1592,7 @@ static struct qcom_icc_node * const gladiator_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_gladiator_noc = {
+ .alloc_dyn_id = true,
.nodes = gladiator_noc_nodes,
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
.bcms = gladiator_noc_bcms,
@@ -1663,6 +1628,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_mem_noc = {
+ .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
@@ -1697,6 +1663,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1743,6 +1710,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom/sdm845.h
deleted file mode 100644
index bc7e425ce9852288da16c49345e77f6374267365..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sdm845.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
-#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
-
-#define SDM845_MASTER_A1NOC_CFG 1
-#define SDM845_MASTER_BLSP_1 2
-#define SDM845_MASTER_TSIF 3
-#define SDM845_MASTER_SDCC_2 4
-#define SDM845_MASTER_SDCC_4 5
-#define SDM845_MASTER_UFS_CARD 6
-#define SDM845_MASTER_UFS_MEM 7
-#define SDM845_MASTER_PCIE_0 8
-#define SDM845_MASTER_A2NOC_CFG 9
-#define SDM845_MASTER_QDSS_BAM 10
-#define SDM845_MASTER_BLSP_2 11
-#define SDM845_MASTER_CNOC_A2NOC 12
-#define SDM845_MASTER_CRYPTO 13
-#define SDM845_MASTER_IPA 14
-#define SDM845_MASTER_PCIE_1 15
-#define SDM845_MASTER_QDSS_ETR 16
-#define SDM845_MASTER_USB3_0 17
-#define SDM845_MASTER_USB3_1 18
-#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19
-#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20
-#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21
-#define SDM845_MASTER_SPDM 22
-#define SDM845_MASTER_TIC 23
-#define SDM845_MASTER_SNOC_CNOC 24
-#define SDM845_MASTER_QDSS_DAP 25
-#define SDM845_MASTER_CNOC_DC_NOC 26
-#define SDM845_MASTER_APPSS_PROC 27
-#define SDM845_MASTER_GNOC_CFG 28
-#define SDM845_MASTER_LLCC 29
-#define SDM845_MASTER_TCU_0 30
-#define SDM845_MASTER_MEM_NOC_CFG 31
-#define SDM845_MASTER_GNOC_MEM_NOC 32
-#define SDM845_MASTER_MNOC_HF_MEM_NOC 33
-#define SDM845_MASTER_MNOC_SF_MEM_NOC 34
-#define SDM845_MASTER_SNOC_GC_MEM_NOC 35
-#define SDM845_MASTER_SNOC_SF_MEM_NOC 36
-#define SDM845_MASTER_GFX3D 37
-#define SDM845_MASTER_CNOC_MNOC_CFG 38
-#define SDM845_MASTER_CAMNOC_HF0 39
-#define SDM845_MASTER_CAMNOC_HF1 40
-#define SDM845_MASTER_CAMNOC_SF 41
-#define SDM845_MASTER_MDP0 42
-#define SDM845_MASTER_MDP1 43
-#define SDM845_MASTER_ROTATOR 44
-#define SDM845_MASTER_VIDEO_P0 45
-#define SDM845_MASTER_VIDEO_P1 46
-#define SDM845_MASTER_VIDEO_PROC 47
-#define SDM845_MASTER_SNOC_CFG 48
-#define SDM845_MASTER_A1NOC_SNOC 49
-#define SDM845_MASTER_A2NOC_SNOC 50
-#define SDM845_MASTER_GNOC_SNOC 51
-#define SDM845_MASTER_MEM_NOC_SNOC 52
-#define SDM845_MASTER_ANOC_PCIE_SNOC 53
-#define SDM845_MASTER_PIMEM 54
-#define SDM845_MASTER_GIC 55
-#define SDM845_SLAVE_A1NOC_SNOC 56
-#define SDM845_SLAVE_SERVICE_A1NOC 57
-#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58
-#define SDM845_SLAVE_A2NOC_SNOC 59
-#define SDM845_SLAVE_ANOC_PCIE_SNOC 60
-#define SDM845_SLAVE_SERVICE_A2NOC 61
-#define SDM845_SLAVE_CAMNOC_UNCOMP 62
-#define SDM845_SLAVE_A1NOC_CFG 63
-#define SDM845_SLAVE_A2NOC_CFG 64
-#define SDM845_SLAVE_AOP 65
-#define SDM845_SLAVE_AOSS 66
-#define SDM845_SLAVE_CAMERA_CFG 67
-#define SDM845_SLAVE_CLK_CTL 68
-#define SDM845_SLAVE_CDSP_CFG 69
-#define SDM845_SLAVE_RBCPR_CX_CFG 70
-#define SDM845_SLAVE_CRYPTO_0_CFG 71
-#define SDM845_SLAVE_DCC_CFG 72
-#define SDM845_SLAVE_CNOC_DDRSS 73
-#define SDM845_SLAVE_DISPLAY_CFG 74
-#define SDM845_SLAVE_GLM 75
-#define SDM845_SLAVE_GFX3D_CFG 76
-#define SDM845_SLAVE_IMEM_CFG 77
-#define SDM845_SLAVE_IPA_CFG 78
-#define SDM845_SLAVE_CNOC_MNOC_CFG 79
-#define SDM845_SLAVE_PCIE_0_CFG 80
-#define SDM845_SLAVE_PCIE_1_CFG 81
-#define SDM845_SLAVE_PDM 82
-#define SDM845_SLAVE_SOUTH_PHY_CFG 83
-#define SDM845_SLAVE_PIMEM_CFG 84
-#define SDM845_SLAVE_PRNG 85
-#define SDM845_SLAVE_QDSS_CFG 86
-#define SDM845_SLAVE_BLSP_2 87
-#define SDM845_SLAVE_BLSP_1 88
-#define SDM845_SLAVE_SDCC_2 89
-#define SDM845_SLAVE_SDCC_4 90
-#define SDM845_SLAVE_SNOC_CFG 91
-#define SDM845_SLAVE_SPDM_WRAPPER 92
-#define SDM845_SLAVE_SPSS_CFG 93
-#define SDM845_SLAVE_TCSR 94
-#define SDM845_SLAVE_TLMM_NORTH 95
-#define SDM845_SLAVE_TLMM_SOUTH 96
-#define SDM845_SLAVE_TSIF 97
-#define SDM845_SLAVE_UFS_CARD_CFG 98
-#define SDM845_SLAVE_UFS_MEM_CFG 99
-#define SDM845_SLAVE_USB3_0 100
-#define SDM845_SLAVE_USB3_1 101
-#define SDM845_SLAVE_VENUS_CFG 102
-#define SDM845_SLAVE_VSENSE_CTRL_CFG 103
-#define SDM845_SLAVE_CNOC_A2NOC 104
-#define SDM845_SLAVE_SERVICE_CNOC 105
-#define SDM845_SLAVE_LLCC_CFG 106
-#define SDM845_SLAVE_MEM_NOC_CFG 107
-#define SDM845_SLAVE_GNOC_SNOC 108
-#define SDM845_SLAVE_GNOC_MEM_NOC 109
-#define SDM845_SLAVE_SERVICE_GNOC 110
-#define SDM845_SLAVE_EBI1 111
-#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112
-#define SDM845_SLAVE_MEM_NOC_GNOC 113
-#define SDM845_SLAVE_LLCC 114
-#define SDM845_SLAVE_MEM_NOC_SNOC 115
-#define SDM845_SLAVE_SERVICE_MEM_NOC 116
-#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117
-#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118
-#define SDM845_SLAVE_SERVICE_MNOC 119
-#define SDM845_SLAVE_APPSS 120
-#define SDM845_SLAVE_SNOC_CNOC 121
-#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122
-#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123
-#define SDM845_SLAVE_IMEM 124
-#define SDM845_SLAVE_PCIE_0 125
-#define SDM845_SLAVE_PCIE_1 126
-#define SDM845_SLAVE_PIMEM 127
-#define SDM845_SLAVE_SERVICE_SNOC 128
-#define SDM845_SLAVE_QDSS_STM 129
-#define SDM845_SLAVE_TCU 130
-
-#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 09/28] interconnect: qcom: sm8250: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (7 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 08/28] interconnect: qcom: sdm845: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 10/28] interconnect: qcom: x1e80100: " Dmitry Baryshkov
` (19 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm8250.c | 894 ++++++++++++++++++-------------------
drivers/interconnect/qcom/sm8250.h | 168 -------
2 files changed, 436 insertions(+), 626 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c
index cd7a37ecb9b55e40e9a90a9b649ae8cced1d1bb3..d75b2c717f07f90a3dad7424d77dcb7c6598b7d3 100644
--- a/drivers/interconnect/qcom/sm8250.c
+++ b/drivers/interconnect/qcom/sm8250.c
@@ -14,1385 +14,1363 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sm8250.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qhm_tsif;
+static struct qcom_icc_node xm_pcie3_modem;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node xm_usb3_1;
+static struct qcom_icc_node qhm_a2noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qnm_cnoc;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_ufs_card;
+static struct qcom_icc_node qnm_npu;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qhm_cnoc_dc_noc;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qhm_gemnoc_cfg;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_video0;
+static struct qcom_icc_node qnm_video1;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_mdp1;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node amm_npu_sys;
+static struct qcom_icc_node amm_npu_sys_cdp_w;
+static struct qcom_icc_node qhm_cfg;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gemnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_pcie_modem_mem_noc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_cdsp_mem_noc;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_a2_noc_cfg;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_dsp;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_npu_cfg;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pcie_modem_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm0;
+static struct qcom_icc_node qhs_tlmm1;
+static struct qcom_icc_node qhs_tlmm2;
+static struct qcom_icc_node qhs_tsif;
+static struct qcom_icc_node qhs_ufs_card_cfg;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_usb3_1;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_memnoc;
+static struct qcom_icc_node qns_gem_noc_snoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_sys_pcie;
+static struct qcom_icc_node srvc_even_gemnoc;
+static struct qcom_icc_node srvc_odd_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_cal_dp0;
+static struct qcom_icc_node qhs_cal_dp1;
+static struct qcom_icc_node qhs_cp;
+static struct qcom_icc_node qhs_dma_bwmon;
+static struct qcom_icc_node qhs_dpm;
+static struct qcom_icc_node qhs_isense;
+static struct qcom_icc_node qhs_llm;
+static struct qcom_icc_node qhs_tcm;
+static struct qcom_icc_node qns_npu_sys;
+static struct qcom_icc_node srvc_noc;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_pcie_modem;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
static struct qcom_icc_node qhm_a1noc_cfg = {
.name = "qhm_a1noc_cfg",
- .id = SM8250_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SM8250_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SM8250_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SM8250_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_tsif = {
.name = "qhm_tsif",
- .id = SM8250_MASTER_TSIF,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie3_modem = {
.name = "xm_pcie3_modem",
- .id = SM8250_MASTER_PCIE_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 },
+ .link_nodes = { &qns_pcie_modem_mem_noc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM8250_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM8250_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM8250_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
- .id = SM8250_MASTER_USB3_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_a2noc_cfg = {
.name = "qhm_a2noc_cfg",
- .id = SM8250_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM8250_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SM8250_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
- .id = SM8250_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM8250_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM8250_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM8250_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SM8250_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SM8250_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM8250_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_card = {
.name = "xm_ufs_card",
- .id = SM8250_MASTER_UFS_CARD,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_npu = {
.name = "qnm_npu",
- .id = SM8250_MASTER_NPU,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_cdsp_mem_noc, NULL },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = SM8250_SNOC_CNOC_MAS,
.channels = 1,
.buswidth = 8,
- .num_links = 49,
- .links = { SM8250_SLAVE_CDSP_CFG,
- SM8250_SLAVE_CAMERA_CFG,
- SM8250_SLAVE_TLMM_SOUTH,
- SM8250_SLAVE_TLMM_NORTH,
- SM8250_SLAVE_SDCC_4,
- SM8250_SLAVE_TLMM_WEST,
- SM8250_SLAVE_SDCC_2,
- SM8250_SLAVE_CNOC_MNOC_CFG,
- SM8250_SLAVE_UFS_MEM_CFG,
- SM8250_SLAVE_SNOC_CFG,
- SM8250_SLAVE_PDM,
- SM8250_SLAVE_CX_RDPM,
- SM8250_SLAVE_PCIE_1_CFG,
- SM8250_SLAVE_A2NOC_CFG,
- SM8250_SLAVE_QDSS_CFG,
- SM8250_SLAVE_DISPLAY_CFG,
- SM8250_SLAVE_PCIE_2_CFG,
- SM8250_SLAVE_TCSR,
- SM8250_SLAVE_DCC_CFG,
- SM8250_SLAVE_CNOC_DDRSS,
- SM8250_SLAVE_IPC_ROUTER_CFG,
- SM8250_SLAVE_PCIE_0_CFG,
- SM8250_SLAVE_RBCPR_MMCX_CFG,
- SM8250_SLAVE_NPU_CFG,
- SM8250_SLAVE_AHB2PHY_SOUTH,
- SM8250_SLAVE_AHB2PHY_NORTH,
- SM8250_SLAVE_GRAPHICS_3D_CFG,
- SM8250_SLAVE_VENUS_CFG,
- SM8250_SLAVE_TSIF,
- SM8250_SLAVE_IPA_CFG,
- SM8250_SLAVE_IMEM_CFG,
- SM8250_SLAVE_USB3,
- SM8250_SLAVE_SERVICE_CNOC,
- SM8250_SLAVE_UFS_CARD_CFG,
- SM8250_SLAVE_USB3_1,
- SM8250_SLAVE_LPASS,
- SM8250_SLAVE_RBCPR_CX_CFG,
- SM8250_SLAVE_A1NOC_CFG,
- SM8250_SLAVE_AOSS,
- SM8250_SLAVE_PRNG,
- SM8250_SLAVE_VSENSE_CTRL_CFG,
- SM8250_SLAVE_QSPI_0,
- SM8250_SLAVE_CRYPTO_0_CFG,
- SM8250_SLAVE_PIMEM_CFG,
- SM8250_SLAVE_RBCPR_MX_CFG,
- SM8250_SLAVE_QUP_0,
- SM8250_SLAVE_QUP_1,
- SM8250_SLAVE_QUP_2,
- SM8250_SLAVE_CLK_CTL
- },
+ .link_nodes = { &qhs_compute_dsp,
+ &qhs_camera_cfg,
+ &qhs_tlmm1,
+ &qhs_tlmm0,
+ &qhs_sdc4,
+ &qhs_tlmm2,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_snoc_cfg,
+ &qhs_pdm,
+ &qhs_cx_rdpm,
+ &qhs_pcie1_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_display_cfg,
+ &qhs_pcie_modem_cfg,
+ &qhs_tcsr,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ipc_router,
+ &qhs_pcie0_cfg,
+ &qhs_cpr_mmcx,
+ &qhs_npu_cfg,
+ &qhs_ahb2phy0,
+ &qhs_ahb2phy1,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_ipa,
+ &qhs_imem_cfg,
+ &qhs_usb3_0,
+ &srvc_cnoc,
+ &qhs_ufs_card_cfg,
+ &qhs_usb3_1,
+ &qhs_lpass_cfg,
+ &qhs_cpr_cx,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_qspi,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_cpr_mx,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_qup2,
+ &qhs_clk_ctl, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SM8250_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 50,
- .links = { SM8250_SLAVE_CDSP_CFG,
- SM8250_SLAVE_CAMERA_CFG,
- SM8250_SLAVE_TLMM_SOUTH,
- SM8250_SLAVE_TLMM_NORTH,
- SM8250_SLAVE_SDCC_4,
- SM8250_SLAVE_TLMM_WEST,
- SM8250_SLAVE_SDCC_2,
- SM8250_SLAVE_CNOC_MNOC_CFG,
- SM8250_SLAVE_UFS_MEM_CFG,
- SM8250_SLAVE_SNOC_CFG,
- SM8250_SLAVE_PDM,
- SM8250_SLAVE_CX_RDPM,
- SM8250_SLAVE_PCIE_1_CFG,
- SM8250_SLAVE_A2NOC_CFG,
- SM8250_SLAVE_QDSS_CFG,
- SM8250_SLAVE_DISPLAY_CFG,
- SM8250_SLAVE_PCIE_2_CFG,
- SM8250_SLAVE_TCSR,
- SM8250_SLAVE_DCC_CFG,
- SM8250_SLAVE_CNOC_DDRSS,
- SM8250_SLAVE_IPC_ROUTER_CFG,
- SM8250_SLAVE_CNOC_A2NOC,
- SM8250_SLAVE_PCIE_0_CFG,
- SM8250_SLAVE_RBCPR_MMCX_CFG,
- SM8250_SLAVE_NPU_CFG,
- SM8250_SLAVE_AHB2PHY_SOUTH,
- SM8250_SLAVE_AHB2PHY_NORTH,
- SM8250_SLAVE_GRAPHICS_3D_CFG,
- SM8250_SLAVE_VENUS_CFG,
- SM8250_SLAVE_TSIF,
- SM8250_SLAVE_IPA_CFG,
- SM8250_SLAVE_IMEM_CFG,
- SM8250_SLAVE_USB3,
- SM8250_SLAVE_SERVICE_CNOC,
- SM8250_SLAVE_UFS_CARD_CFG,
- SM8250_SLAVE_USB3_1,
- SM8250_SLAVE_LPASS,
- SM8250_SLAVE_RBCPR_CX_CFG,
- SM8250_SLAVE_A1NOC_CFG,
- SM8250_SLAVE_AOSS,
- SM8250_SLAVE_PRNG,
- SM8250_SLAVE_VSENSE_CTRL_CFG,
- SM8250_SLAVE_QSPI_0,
- SM8250_SLAVE_CRYPTO_0_CFG,
- SM8250_SLAVE_PIMEM_CFG,
- SM8250_SLAVE_RBCPR_MX_CFG,
- SM8250_SLAVE_QUP_0,
- SM8250_SLAVE_QUP_1,
- SM8250_SLAVE_QUP_2,
- SM8250_SLAVE_CLK_CTL
- },
+ .link_nodes = { &qhs_compute_dsp,
+ &qhs_camera_cfg,
+ &qhs_tlmm1,
+ &qhs_tlmm0,
+ &qhs_sdc4,
+ &qhs_tlmm2,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_snoc_cfg,
+ &qhs_pdm,
+ &qhs_cx_rdpm,
+ &qhs_pcie1_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_display_cfg,
+ &qhs_pcie_modem_cfg,
+ &qhs_tcsr,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ipc_router,
+ &qns_cnoc_a2noc,
+ &qhs_pcie0_cfg,
+ &qhs_cpr_mmcx,
+ &qhs_npu_cfg,
+ &qhs_ahb2phy0,
+ &qhs_ahb2phy1,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_ipa,
+ &qhs_imem_cfg,
+ &qhs_usb3_0,
+ &srvc_cnoc,
+ &qhs_ufs_card_cfg,
+ &qhs_usb3_1,
+ &qhs_lpass_cfg,
+ &qhs_cpr_cx,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_qspi,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_cpr_mx,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_qup2,
+ &qhs_clk_ctl, NULL },
};
static struct qcom_icc_node qhm_cnoc_dc_noc = {
.name = "qhm_cnoc_dc_noc",
- .id = SM8250_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SM8250_SLAVE_GEM_NOC_CFG,
- SM8250_SLAVE_LLCC_CFG
- },
+ .link_nodes = { &qhs_memnoc,
+ &qhs_llcc, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SM8250_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8250_SLAVE_LLCC,
- SM8250_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SM8250_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8250_SLAVE_LLCC,
- SM8250_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SM8250_MASTER_AMPSS_M0,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8250_SLAVE_LLCC,
- SM8250_SLAVE_GEM_NOC_SNOC,
- SM8250_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc,
+ &qns_sys_pcie, NULL },
};
static struct qcom_icc_node qhm_gemnoc_cfg = {
.name = "qhm_gemnoc_cfg",
- .id = SM8250_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 3,
- .links = { SM8250_SLAVE_SERVICE_GEM_NOC_2,
- SM8250_SLAVE_SERVICE_GEM_NOC_1,
- SM8250_SLAVE_SERVICE_GEM_NOC
- },
+ .link_nodes = { &srvc_odd_gemnoc,
+ &srvc_even_gemnoc,
+ &srvc_sys_gemnoc, NULL },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SM8250_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8250_SLAVE_LLCC,
- SM8250_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SM8250_MASTER_GRAPHICS_3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8250_SLAVE_LLCC,
- SM8250_SLAVE_GEM_NOC_SNOC },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM8250_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM8250_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8250_SLAVE_LLCC,
- SM8250_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM8250_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM8250_SLAVE_LLCC,
- SM8250_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM8250_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM8250_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8250_SLAVE_LLCC,
- SM8250_SLAVE_GEM_NOC_SNOC,
- SM8250_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc,
+ &qns_sys_pcie, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM8250_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_SLAVE_EBI_CH0 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = SM8250_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SM8250_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = SM8250_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SM8250_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
- .id = SM8250_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video1 = {
.name = "qnm_video1",
- .id = SM8250_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SM8250_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SM8250_MASTER_MDP_PORT0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_mdp1 = {
.name = "qxm_mdp1",
- .id = SM8250_MASTER_MDP_PORT1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = SM8250_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node amm_npu_sys = {
.name = "amm_npu_sys",
- .id = SM8250_MASTER_NPU_SYS,
.channels = 4,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_SLAVE_NPU_COMPUTE_NOC },
+ .link_nodes = { &qns_npu_sys, NULL },
};
static struct qcom_icc_node amm_npu_sys_cdp_w = {
.name = "amm_npu_sys_cdp_w",
- .id = SM8250_MASTER_NPU_CDP,
.channels = 2,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_SLAVE_NPU_COMPUTE_NOC },
+ .link_nodes = { &qns_npu_sys, NULL },
};
static struct qcom_icc_node qhm_cfg = {
.name = "qhm_cfg",
- .id = SM8250_MASTER_NPU_NOC_CFG,
- .channels = 1,
- .buswidth = 4,
- .num_links = 9,
- .links = { SM8250_SLAVE_SERVICE_NPU_NOC,
- SM8250_SLAVE_ISENSE_CFG,
- SM8250_SLAVE_NPU_LLM_CFG,
- SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG,
- SM8250_SLAVE_NPU_CP,
- SM8250_SLAVE_NPU_TCM,
- SM8250_SLAVE_NPU_CAL_DP0,
- SM8250_SLAVE_NPU_CAL_DP1,
- SM8250_SLAVE_NPU_DPM
- },
+ .channels = 1,
+ .buswidth = 4,
+ .link_nodes = { &srvc_noc,
+ &qhs_isense,
+ &qhs_llm,
+ &qhs_dma_bwmon,
+ &qhs_cp,
+ &qhs_tcm,
+ &qhs_cal_dp0,
+ &qhs_cal_dp1,
+ &qhs_dpm, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SM8250_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM8250_A1NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM8250_A2NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_gemnoc = {
.name = "qnm_gemnoc",
- .id = SM8250_MASTER_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SM8250_SLAVE_PIMEM,
- SM8250_SLAVE_OCIMEM,
- SM8250_SLAVE_APPSS,
- SM8250_SNOC_CNOC_SLV,
- SM8250_SLAVE_TCU,
- SM8250_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SM8250_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 3,
- .links = { SM8250_SLAVE_PCIE_2,
- SM8250_SLAVE_PCIE_0,
- SM8250_SLAVE_PCIE_1
- },
+ .link_nodes = { &xs_pcie_modem,
+ &xs_pcie_0,
+ &xs_pcie_1, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SM8250_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM8250_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM8250_A1NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_A1NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_pcie_modem_mem_noc = {
.name = "qns_pcie_modem_mem_noc",
- .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SM8250_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM8250_A2NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_A2NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SM8250_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cdsp_mem_noc = {
.name = "qns_cdsp_mem_noc",
- .id = SM8250_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = SM8250_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qhs_a2_noc_cfg = {
.name = "qhs_a2_noc_cfg",
- .id = SM8250_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_MASTER_A2NOC_CFG },
+ .link_nodes = { &qhm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SM8250_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SM8250_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM8250_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM8250_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM8250_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_dsp = {
.name = "qhs_compute_dsp",
- .id = SM8250_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM8250_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SM8250_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SM8250_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM8250_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SM8250_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SM8250_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SM8250_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM8250_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM8250_SLAVE_GRAPHICS_3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM8250_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM8250_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SM8250_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = SM8250_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = SM8250_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_npu_cfg = {
.name = "qhs_npu_cfg",
- .id = SM8250_SLAVE_NPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_MASTER_NPU_NOC_CFG },
+ .link_nodes = { &qhm_cfg, NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SM8250_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SM8250_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_modem_cfg = {
.name = "qhs_pcie_modem_cfg",
- .id = SM8250_SLAVE_PCIE_2_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM8250_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM8250_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM8250_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM8250_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SM8250_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SM8250_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SM8250_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SM8250_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM8250_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM8250_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SM8250_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM8250_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm0 = {
.name = "qhs_tlmm0",
- .id = SM8250_SLAVE_TLMM_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm1 = {
.name = "qhs_tlmm1",
- .id = SM8250_SLAVE_TLMM_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm2 = {
.name = "qhs_tlmm2",
- .id = SM8250_SLAVE_TLMM_WEST,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tsif = {
.name = "qhs_tsif",
- .id = SM8250_SLAVE_TSIF,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_card_cfg = {
.name = "qhs_ufs_card_cfg",
- .id = SM8250_SLAVE_UFS_CARD_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM8250_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM8250_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_1 = {
.name = "qhs_usb3_1",
- .id = SM8250_SLAVE_USB3_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM8250_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM8250_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = SM8250_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc, NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SM8250_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SM8250_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_memnoc = {
.name = "qhs_memnoc",
- .id = SM8250_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qhm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qns_gem_noc_snoc = {
.name = "qns_gem_noc_snoc",
- .id = SM8250_SLAVE_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_MASTER_GEM_NOC_SNOC },
+ .link_nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM8250_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_sys_pcie = {
.name = "qns_sys_pcie",
- .id = SM8250_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
- .id = SM8250_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
- .id = SM8250_SLAVE_SERVICE_GEM_NOC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
- .id = SM8250_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM8250_SLAVE_EBI_CH0,
.channels = 4,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM8250_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SM8250_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8250_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM8250_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cal_dp0 = {
.name = "qhs_cal_dp0",
- .id = SM8250_SLAVE_NPU_CAL_DP0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cal_dp1 = {
.name = "qhs_cal_dp1",
- .id = SM8250_SLAVE_NPU_CAL_DP1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cp = {
.name = "qhs_cp",
- .id = SM8250_SLAVE_NPU_CP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dma_bwmon = {
.name = "qhs_dma_bwmon",
- .id = SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dpm = {
.name = "qhs_dpm",
- .id = SM8250_SLAVE_NPU_DPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_isense = {
.name = "qhs_isense",
- .id = SM8250_SLAVE_ISENSE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llm = {
.name = "qhs_llm",
- .id = SM8250_SLAVE_NPU_LLM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcm = {
.name = "qhs_tcm",
- .id = SM8250_SLAVE_NPU_TCM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_npu_sys = {
.name = "qns_npu_sys",
- .id = SM8250_SLAVE_NPU_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_noc = {
.name = "srvc_noc",
- .id = SM8250_SLAVE_SERVICE_NPU_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SM8250_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = SM8250_SNOC_CNOC_SLV,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_SNOC_CNOC_MAS },
+ .link_nodes = { &qnm_snoc, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM8250_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8250_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM8250_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8250_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM8250_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SM8250_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SM8250_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SM8250_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SM8250_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_modem = {
.name = "xs_pcie_modem",
- .id = SM8250_SLAVE_PCIE_2,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM8250_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM8250_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SM8250_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SM8250_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = SM8250_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8250_SLAVE_QUP_CORE_2 },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SM8250_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SM8250_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = SM8250_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h
deleted file mode 100644
index 032665093c5bfe83e9dc6b444fc07fcf790e9993..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm8250.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm #define SM8250 interconnect IDs
- *
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H
-
-#define SM8250_A1NOC_SNOC_MAS 0
-#define SM8250_A1NOC_SNOC_SLV 1
-#define SM8250_A2NOC_SNOC_MAS 2
-#define SM8250_A2NOC_SNOC_SLV 3
-#define SM8250_MASTER_A1NOC_CFG 4
-#define SM8250_MASTER_A2NOC_CFG 5
-#define SM8250_MASTER_AMPSS_M0 6
-#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7
-#define SM8250_MASTER_CAMNOC_HF 8
-#define SM8250_MASTER_CAMNOC_ICP 9
-#define SM8250_MASTER_CAMNOC_SF 10
-#define SM8250_MASTER_CNOC_A2NOC 11
-#define SM8250_MASTER_CNOC_DC_NOC 12
-#define SM8250_MASTER_CNOC_MNOC_CFG 13
-#define SM8250_MASTER_COMPUTE_NOC 14
-#define SM8250_MASTER_CRYPTO_CORE_0 15
-#define SM8250_MASTER_GEM_NOC_CFG 16
-#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17
-#define SM8250_MASTER_GEM_NOC_SNOC 18
-#define SM8250_MASTER_GIC 19
-#define SM8250_MASTER_GPU_TCU 20
-#define SM8250_MASTER_GRAPHICS_3D 21
-#define SM8250_MASTER_IPA 22
-/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */
-#define SM8250_MASTER_LLCC 24
-#define SM8250_MASTER_MDP_PORT0 25
-#define SM8250_MASTER_MDP_PORT1 26
-#define SM8250_MASTER_MNOC_HF_MEM_NOC 27
-#define SM8250_MASTER_MNOC_SF_MEM_NOC 28
-#define SM8250_MASTER_NPU 29
-#define SM8250_MASTER_NPU_CDP 30
-#define SM8250_MASTER_NPU_NOC_CFG 31
-#define SM8250_MASTER_NPU_SYS 32
-#define SM8250_MASTER_PCIE 33
-#define SM8250_MASTER_PCIE_1 34
-#define SM8250_MASTER_PCIE_2 35
-#define SM8250_MASTER_PIMEM 36
-#define SM8250_MASTER_QDSS_BAM 37
-#define SM8250_MASTER_QDSS_DAP 38
-#define SM8250_MASTER_QDSS_ETR 39
-#define SM8250_MASTER_QSPI_0 40
-#define SM8250_MASTER_QUP_0 41
-#define SM8250_MASTER_QUP_1 42
-#define SM8250_MASTER_QUP_2 43
-#define SM8250_MASTER_ROTATOR 44
-#define SM8250_MASTER_SDCC_2 45
-#define SM8250_MASTER_SDCC_4 46
-#define SM8250_MASTER_SNOC_CFG 47
-#define SM8250_MASTER_SNOC_GC_MEM_NOC 48
-#define SM8250_MASTER_SNOC_SF_MEM_NOC 49
-#define SM8250_MASTER_SYS_TCU 50
-#define SM8250_MASTER_TSIF 51
-#define SM8250_MASTER_UFS_CARD 52
-#define SM8250_MASTER_UFS_MEM 53
-#define SM8250_MASTER_USB3 54
-#define SM8250_MASTER_USB3_1 55
-#define SM8250_MASTER_VIDEO_P0 56
-#define SM8250_MASTER_VIDEO_P1 57
-#define SM8250_MASTER_VIDEO_PROC 58
-#define SM8250_SLAVE_A1NOC_CFG 59
-#define SM8250_SLAVE_A2NOC_CFG 60
-#define SM8250_SLAVE_AHB2PHY_NORTH 61
-#define SM8250_SLAVE_AHB2PHY_SOUTH 62
-#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63
-#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64
-#define SM8250_SLAVE_AOSS 65
-#define SM8250_SLAVE_APPSS 66
-#define SM8250_SLAVE_CAMERA_CFG 67
-#define SM8250_SLAVE_CDSP_CFG 68
-#define SM8250_SLAVE_CDSP_MEM_NOC 69
-#define SM8250_SLAVE_CLK_CTL 70
-#define SM8250_SLAVE_CNOC_A2NOC 71
-#define SM8250_SLAVE_CNOC_DDRSS 72
-#define SM8250_SLAVE_CNOC_MNOC_CFG 73
-#define SM8250_SLAVE_CRYPTO_0_CFG 74
-#define SM8250_SLAVE_CX_RDPM 75
-#define SM8250_SLAVE_DCC_CFG 76
-#define SM8250_SLAVE_DISPLAY_CFG 77
-#define SM8250_SLAVE_EBI_CH0 78
-#define SM8250_SLAVE_GEM_NOC_CFG 79
-#define SM8250_SLAVE_GEM_NOC_SNOC 80
-#define SM8250_SLAVE_GRAPHICS_3D_CFG 81
-#define SM8250_SLAVE_IMEM_CFG 82
-#define SM8250_SLAVE_IPA_CFG 83
-/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
-#define SM8250_SLAVE_IPC_ROUTER_CFG 85
-#define SM8250_SLAVE_ISENSE_CFG 86
-#define SM8250_SLAVE_LLCC 87
-#define SM8250_SLAVE_LLCC_CFG 88
-#define SM8250_SLAVE_LPASS 89
-#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90
-#define SM8250_SLAVE_MNOC_HF_MEM_NOC 91
-#define SM8250_SLAVE_MNOC_SF_MEM_NOC 92
-#define SM8250_SLAVE_NPU_CAL_DP0 93
-#define SM8250_SLAVE_NPU_CAL_DP1 94
-#define SM8250_SLAVE_NPU_CFG 95
-#define SM8250_SLAVE_NPU_COMPUTE_NOC 96
-#define SM8250_SLAVE_NPU_CP 97
-#define SM8250_SLAVE_NPU_DPM 98
-#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99
-#define SM8250_SLAVE_NPU_LLM_CFG 100
-#define SM8250_SLAVE_NPU_TCM 101
-#define SM8250_SLAVE_OCIMEM 102
-#define SM8250_SLAVE_PCIE_0 103
-#define SM8250_SLAVE_PCIE_0_CFG 104
-#define SM8250_SLAVE_PCIE_1 105
-#define SM8250_SLAVE_PCIE_1_CFG 106
-#define SM8250_SLAVE_PCIE_2 107
-#define SM8250_SLAVE_PCIE_2_CFG 108
-#define SM8250_SLAVE_PDM 109
-#define SM8250_SLAVE_PIMEM 110
-#define SM8250_SLAVE_PIMEM_CFG 111
-#define SM8250_SLAVE_PRNG 112
-#define SM8250_SLAVE_QDSS_CFG 113
-#define SM8250_SLAVE_QDSS_STM 114
-#define SM8250_SLAVE_QSPI_0 115
-#define SM8250_SLAVE_QUP_0 116
-#define SM8250_SLAVE_QUP_1 117
-#define SM8250_SLAVE_QUP_2 118
-#define SM8250_SLAVE_RBCPR_CX_CFG 119
-#define SM8250_SLAVE_RBCPR_MMCX_CFG 120
-#define SM8250_SLAVE_RBCPR_MX_CFG 121
-#define SM8250_SLAVE_SDCC_2 122
-#define SM8250_SLAVE_SDCC_4 123
-#define SM8250_SLAVE_SERVICE_A1NOC 124
-#define SM8250_SLAVE_SERVICE_A2NOC 125
-#define SM8250_SLAVE_SERVICE_CNOC 126
-#define SM8250_SLAVE_SERVICE_GEM_NOC 127
-#define SM8250_SLAVE_SERVICE_GEM_NOC_1 128
-#define SM8250_SLAVE_SERVICE_GEM_NOC_2 129
-#define SM8250_SLAVE_SERVICE_MNOC 130
-#define SM8250_SLAVE_SERVICE_NPU_NOC 131
-#define SM8250_SLAVE_SERVICE_SNOC 132
-#define SM8250_SLAVE_SNOC_CFG 133
-#define SM8250_SLAVE_SNOC_GEM_NOC_GC 134
-#define SM8250_SLAVE_SNOC_GEM_NOC_SF 135
-#define SM8250_SLAVE_TCSR 136
-#define SM8250_SLAVE_TCU 137
-#define SM8250_SLAVE_TLMM_NORTH 138
-#define SM8250_SLAVE_TLMM_SOUTH 139
-#define SM8250_SLAVE_TLMM_WEST 140
-#define SM8250_SLAVE_TSIF 141
-#define SM8250_SLAVE_UFS_CARD_CFG 142
-#define SM8250_SLAVE_UFS_MEM_CFG 143
-#define SM8250_SLAVE_USB3 144
-#define SM8250_SLAVE_USB3_1 145
-#define SM8250_SLAVE_VENUS_CFG 146
-#define SM8250_SLAVE_VSENSE_CTRL_CFG 147
-#define SM8250_SNOC_CNOC_MAS 148
-#define SM8250_SNOC_CNOC_SLV 149
-#define SM8250_MASTER_QUP_CORE_0 150
-#define SM8250_MASTER_QUP_CORE_1 151
-#define SM8250_MASTER_QUP_CORE_2 152
-#define SM8250_SLAVE_QUP_CORE_0 153
-#define SM8250_SLAVE_QUP_CORE_1 154
-#define SM8250_SLAVE_QUP_CORE_2 155
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 10/28] interconnect: qcom: x1e80100: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (8 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 09/28] interconnect: qcom: sm8250: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 11/28] interconnect: qcom: qcs615: " Dmitry Baryshkov
` (18 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/x1e80100.c | 781 ++++++++++++++++-------------------
drivers/interconnect/qcom/x1e80100.h | 192 ---------
2 files changed, 356 insertions(+), 617 deletions(-)
diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
index f83a881b2becba9f7806bcc8f945e970596554b2..8f2a912f403a48826a9ee89df57933f746e4bed6 100644
--- a/drivers/interconnect/qcom/x1e80100.c
+++ b/drivers/interconnect/qcom/x1e80100.c
@@ -15,1342 +15,1254 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
-#include "x1e80100.h"
+
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_sp;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qsm_cfg;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_pcie_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_lpass;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_nsp_noc;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qnm_lpiaon_noc;
+static struct qcom_icc_node qnm_lpass_lpinoc;
+static struct qcom_icc_node qxm_lpinoc_dsp_axim;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_av1_enc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_eva;
+static struct qcom_icc_node qnm_mdp;
+static struct qcom_icc_node qnm_video;
+static struct qcom_icc_node qnm_video_cv_cpu;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qsm_mnoc_cfg;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qnm_pcie_north_gem_noc;
+static struct qcom_icc_node qnm_pcie_south_gem_noc;
+static struct qcom_icc_node xm_pcie_3;
+static struct qcom_icc_node xm_pcie_4;
+static struct qcom_icc_node xm_pcie_5;
+static struct qcom_icc_node xm_pcie_0;
+static struct qcom_icc_node xm_pcie_1;
+static struct qcom_icc_node xm_pcie_2;
+static struct qcom_icc_node xm_pcie_6a;
+static struct qcom_icc_node xm_pcie_6b;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gic;
+static struct qcom_icc_node qnm_usb_anoc;
+static struct qcom_icc_node qnm_aggre_usb_north_snoc;
+static struct qcom_icc_node qnm_aggre_usb_south_snoc;
+static struct qcom_icc_node xm_usb2_0;
+static struct qcom_icc_node xm_usb3_mp;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node xm_usb3_1;
+static struct qcom_icc_node xm_usb3_2;
+static struct qcom_icc_node xm_usb4_0;
+static struct qcom_icc_node xm_usb4_1;
+static struct qcom_icc_node xm_usb4_2;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_ahb2phy2;
+static struct qcom_icc_node qhs_av1_enc_cfg;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pcie2_cfg;
+static struct qcom_icc_node qhs_pcie3_cfg;
+static struct qcom_icc_node qhs_pcie4_cfg;
+static struct qcom_icc_node qhs_pcie5_cfg;
+static struct qcom_icc_node qhs_pcie6a_cfg;
+static struct qcom_icc_node qhs_pcie6b_cfg;
+static struct qcom_icc_node qhs_pcie_rsc_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_smmuv3_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb2_0_cfg;
+static struct qcom_icc_node qhs_usb3_0_cfg;
+static struct qcom_icc_node qhs_usb3_1_cfg;
+static struct qcom_icc_node qhs_usb3_2_cfg;
+static struct qcom_icc_node qhs_usb3_mp_cfg;
+static struct qcom_icc_node qhs_usb4_0_cfg;
+static struct qcom_icc_node qhs_usb4_1_cfg;
+static struct qcom_icc_node qhs_usb4_2_cfg;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qss_lpass_qtb_cfg;
+static struct qcom_icc_node qss_mnoc_cfg;
+static struct qcom_icc_node qss_nsp_qtb_cfg;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_tme_cfg;
+static struct qcom_icc_node qns_apss;
+static struct qcom_icc_node qss_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_pcie_2;
+static struct qcom_icc_node xs_pcie_3;
+static struct qcom_icc_node xs_pcie_4;
+static struct qcom_icc_node xs_pcie_5;
+static struct qcom_icc_node xs_pcie_6a;
+static struct qcom_icc_node xs_pcie_6b;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
+static struct qcom_icc_node qns_lpass_aggnoc;
+static struct qcom_icc_node qns_lpi_aon_noc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node qns_pcie_north_gem_noc;
+static struct qcom_icc_node qns_pcie_south_gem_noc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qns_aggre_usb_snoc;
+static struct qcom_icc_node qns_aggre_usb_north_snoc;
+static struct qcom_icc_node qns_aggre_usb_south_snoc;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = X1E80100_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = X1E80100_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = X1E80100_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = X1E80100_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = X1E80100_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = X1E80100_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = X1E80100_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sp = {
.name = "qxm_sp",
- .id = X1E80100_MASTER_SP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = X1E80100_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = X1E80100_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = X1E80100_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = X1E80100_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = X1E80100_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = X1E80100_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_QUP_CORE_2 },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qsm_cfg = {
.name = "qsm_cfg",
- .id = X1E80100_MASTER_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 47,
- .links = { X1E80100_SLAVE_AHB2PHY_SOUTH, X1E80100_SLAVE_AHB2PHY_NORTH,
- X1E80100_SLAVE_AHB2PHY_2, X1E80100_SLAVE_AV1_ENC_CFG,
- X1E80100_SLAVE_CAMERA_CFG, X1E80100_SLAVE_CLK_CTL,
- X1E80100_SLAVE_CRYPTO_0_CFG, X1E80100_SLAVE_DISPLAY_CFG,
- X1E80100_SLAVE_GFX3D_CFG, X1E80100_SLAVE_IMEM_CFG,
- X1E80100_SLAVE_IPC_ROUTER_CFG, X1E80100_SLAVE_PCIE_0_CFG,
- X1E80100_SLAVE_PCIE_1_CFG, X1E80100_SLAVE_PCIE_2_CFG,
- X1E80100_SLAVE_PCIE_3_CFG, X1E80100_SLAVE_PCIE_4_CFG,
- X1E80100_SLAVE_PCIE_5_CFG, X1E80100_SLAVE_PCIE_6A_CFG,
- X1E80100_SLAVE_PCIE_6B_CFG, X1E80100_SLAVE_PCIE_RSC_CFG,
- X1E80100_SLAVE_PDM, X1E80100_SLAVE_PRNG,
- X1E80100_SLAVE_QDSS_CFG, X1E80100_SLAVE_QSPI_0,
- X1E80100_SLAVE_QUP_0, X1E80100_SLAVE_QUP_1,
- X1E80100_SLAVE_QUP_2, X1E80100_SLAVE_SDCC_2,
- X1E80100_SLAVE_SDCC_4, X1E80100_SLAVE_SMMUV3_CFG,
- X1E80100_SLAVE_TCSR, X1E80100_SLAVE_TLMM,
- X1E80100_SLAVE_UFS_MEM_CFG, X1E80100_SLAVE_USB2,
- X1E80100_SLAVE_USB3_0, X1E80100_SLAVE_USB3_1,
- X1E80100_SLAVE_USB3_2, X1E80100_SLAVE_USB3_MP,
- X1E80100_SLAVE_USB4_0, X1E80100_SLAVE_USB4_1,
- X1E80100_SLAVE_USB4_2, X1E80100_SLAVE_VENUS_CFG,
- X1E80100_SLAVE_LPASS_QTB_CFG, X1E80100_SLAVE_CNOC_MNOC_CFG,
- X1E80100_SLAVE_NSP_QTB_CFG, X1E80100_SLAVE_QDSS_STM,
- X1E80100_SLAVE_TCU },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_ahb2phy2, &qhs_av1_enc_cfg,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_crypto0_cfg, &qhs_display_cfg,
+ &qhs_gpuss_cfg, &qhs_imem_cfg,
+ &qhs_ipc_router, &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg, &qhs_pcie2_cfg,
+ &qhs_pcie3_cfg, &qhs_pcie4_cfg,
+ &qhs_pcie5_cfg, &qhs_pcie6a_cfg,
+ &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg,
+ &qhs_pdm, &qhs_prng,
+ &qhs_qdss_cfg, &qhs_qspi,
+ &qhs_qup0, &qhs_qup1,
+ &qhs_qup2, &qhs_sdc2,
+ &qhs_sdc4, &qhs_smmuv3_cfg,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg,
+ &qhs_usb3_0_cfg, &qhs_usb3_1_cfg,
+ &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg,
+ &qhs_usb4_0_cfg, &qhs_usb4_1_cfg,
+ &qhs_usb4_2_cfg, &qhs_venus_cfg,
+ &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
+ &qss_nsp_qtb_cfg, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = X1E80100_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { X1E80100_SLAVE_AOSS, X1E80100_SLAVE_TME_CFG,
- X1E80100_SLAVE_APPSS, X1E80100_SLAVE_CNOC_CFG,
- X1E80100_SLAVE_BOOT_IMEM, X1E80100_SLAVE_IMEM },
+ .link_nodes = { &qhs_aoss, &qhs_tme_cfg,
+ &qns_apss, &qss_cfg,
+ &qxs_boot_imem, &qxs_imem, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = X1E80100_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 32,
- .num_links = 8,
- .links = { X1E80100_SLAVE_PCIE_0, X1E80100_SLAVE_PCIE_1,
- X1E80100_SLAVE_PCIE_2, X1E80100_SLAVE_PCIE_3,
- X1E80100_SLAVE_PCIE_4, X1E80100_SLAVE_PCIE_5,
- X1E80100_SLAVE_PCIE_6A, X1E80100_SLAVE_PCIE_6B },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1,
+ &xs_pcie_2, &xs_pcie_3,
+ &xs_pcie_4, &xs_pcie_5,
+ &xs_pcie_6a, &xs_pcie_6b, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = X1E80100_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_pcie_tcu = {
.name = "alm_pcie_tcu",
- .id = X1E80100_MASTER_PCIE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = X1E80100_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = X1E80100_MASTER_APPSS_PROC,
.channels = 6,
.buswidth = 32,
- .num_links = 3,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,
- X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = X1E80100_MASTER_GFX3D,
.channels = 4,
.buswidth = 32,
- .num_links = 2,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_lpass = {
.name = "qnm_lpass",
- .id = X1E80100_MASTER_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,
- X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = X1E80100_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = X1E80100_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_nsp_noc = {
.name = "qnm_nsp_noc",
- .id = X1E80100_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,
- X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 64,
- .num_links = 2,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = X1E80100_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 64,
- .num_links = 3,
- .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,
- X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = X1E80100_MASTER_GIC2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_lpiaon_noc = {
.name = "qnm_lpiaon_noc",
- .id = X1E80100_MASTER_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_LPASS_GEM_NOC },
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc, NULL },
};
static struct qcom_icc_node qnm_lpass_lpinoc = {
.name = "qnm_lpass_lpinoc",
- .id = X1E80100_MASTER_LPASS_LPINOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
+ .link_nodes = { &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
.name = "qxm_lpinoc_dsp_axim",
- .id = X1E80100_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC },
+ .link_nodes = { &qns_lpi_aon_noc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = X1E80100_MASTER_LLCC,
.channels = 8,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_av1_enc = {
.name = "qnm_av1_enc",
- .id = X1E80100_MASTER_AV1_ENC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = X1E80100_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = X1E80100_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = X1E80100_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_eva = {
.name = "qnm_eva",
- .id = X1E80100_MASTER_EVA,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_mdp = {
.name = "qnm_mdp",
- .id = X1E80100_MASTER_MDP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_video = {
.name = "qnm_video",
- .id = X1E80100_MASTER_VIDEO,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cv_cpu = {
.name = "qnm_video_cv_cpu",
- .id = X1E80100_MASTER_VIDEO_CV_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = X1E80100_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qsm_mnoc_cfg = {
.name = "qsm_mnoc_cfg",
- .id = X1E80100_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = X1E80100_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qnm_pcie_north_gem_noc = {
.name = "qnm_pcie_north_gem_noc",
- .id = X1E80100_MASTER_PCIE_NORTH,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node qnm_pcie_south_gem_noc = {
.name = "qnm_pcie_south_gem_noc",
- .id = X1E80100_MASTER_PCIE_SOUTH,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie_3 = {
.name = "xm_pcie_3",
- .id = X1E80100_MASTER_PCIE_3,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_SLAVE_PCIE_NORTH },
+ .link_nodes = { &qns_pcie_north_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie_4 = {
.name = "xm_pcie_4",
- .id = X1E80100_MASTER_PCIE_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_PCIE_NORTH },
+ .link_nodes = { &qns_pcie_north_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie_5 = {
.name = "xm_pcie_5",
- .id = X1E80100_MASTER_PCIE_5,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_PCIE_NORTH },
+ .link_nodes = { &qns_pcie_north_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie_0 = {
.name = "xm_pcie_0",
- .id = X1E80100_MASTER_PCIE_0,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_PCIE_SOUTH },
+ .link_nodes = { &qns_pcie_south_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie_1 = {
.name = "xm_pcie_1",
- .id = X1E80100_MASTER_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_PCIE_SOUTH },
+ .link_nodes = { &qns_pcie_south_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie_2 = {
.name = "xm_pcie_2",
- .id = X1E80100_MASTER_PCIE_2,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_PCIE_SOUTH },
+ .link_nodes = { &qns_pcie_south_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie_6a = {
.name = "xm_pcie_6a",
- .id = X1E80100_MASTER_PCIE_6A,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_SLAVE_PCIE_SOUTH },
+ .link_nodes = { &qns_pcie_south_gem_noc, NULL },
};
static struct qcom_icc_node xm_pcie_6b = {
.name = "xm_pcie_6b",
- .id = X1E80100_MASTER_PCIE_6B,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_PCIE_SOUTH },
+ .link_nodes = { &qns_pcie_south_gem_noc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = X1E80100_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = X1E80100_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_gic = {
.name = "qnm_gic",
- .id = X1E80100_MASTER_GIC1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_usb_anoc = {
.name = "qnm_usb_anoc",
- .id = X1E80100_MASTER_USB_NOC_SNOC,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre_usb_north_snoc = {
.name = "qnm_aggre_usb_north_snoc",
- .id = X1E80100_MASTER_AGGRE_USB_NORTH,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_SLAVE_USB_NOC_SNOC },
+ .link_nodes = { &qns_aggre_usb_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre_usb_south_snoc = {
.name = "qnm_aggre_usb_south_snoc",
- .id = X1E80100_MASTER_AGGRE_USB_SOUTH,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_SLAVE_USB_NOC_SNOC },
+ .link_nodes = { &qns_aggre_usb_snoc, NULL },
};
static struct qcom_icc_node xm_usb2_0 = {
.name = "xm_usb2_0",
- .id = X1E80100_MASTER_USB2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_AGGRE_USB_NORTH },
+ .link_nodes = { &qns_aggre_usb_north_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_mp = {
.name = "xm_usb3_mp",
- .id = X1E80100_MASTER_USB3_MP,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_AGGRE_USB_NORTH },
+ .link_nodes = { &qns_aggre_usb_north_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = X1E80100_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
+ .link_nodes = { &qns_aggre_usb_south_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
- .id = X1E80100_MASTER_USB3_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
+ .link_nodes = { &qns_aggre_usb_south_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_2 = {
.name = "xm_usb3_2",
- .id = X1E80100_MASTER_USB3_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
+ .link_nodes = { &qns_aggre_usb_south_snoc, NULL },
};
static struct qcom_icc_node xm_usb4_0 = {
.name = "xm_usb4_0",
- .id = X1E80100_MASTER_USB4_0,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
+ .link_nodes = { &qns_aggre_usb_south_snoc, NULL },
};
static struct qcom_icc_node xm_usb4_1 = {
.name = "xm_usb4_1",
- .id = X1E80100_MASTER_USB4_1,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
+ .link_nodes = { &qns_aggre_usb_south_snoc, NULL },
};
static struct qcom_icc_node xm_usb4_2 = {
.name = "xm_usb4_2",
- .id = X1E80100_MASTER_USB4_2,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
+ .link_nodes = { &qns_aggre_usb_south_snoc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = X1E80100_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = X1E80100_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = X1E80100_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = X1E80100_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = X1E80100_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = X1E80100_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = X1E80100_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy2 = {
.name = "qhs_ahb2phy2",
- .id = X1E80100_SLAVE_AHB2PHY_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_av1_enc_cfg = {
.name = "qhs_av1_enc_cfg",
- .id = X1E80100_SLAVE_AV1_ENC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = X1E80100_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = X1E80100_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = X1E80100_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = X1E80100_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = X1E80100_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = X1E80100_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = X1E80100_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = X1E80100_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = X1E80100_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie2_cfg = {
.name = "qhs_pcie2_cfg",
- .id = X1E80100_SLAVE_PCIE_2_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie3_cfg = {
.name = "qhs_pcie3_cfg",
- .id = X1E80100_SLAVE_PCIE_3_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie4_cfg = {
.name = "qhs_pcie4_cfg",
- .id = X1E80100_SLAVE_PCIE_4_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie5_cfg = {
.name = "qhs_pcie5_cfg",
- .id = X1E80100_SLAVE_PCIE_5_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie6a_cfg = {
.name = "qhs_pcie6a_cfg",
- .id = X1E80100_SLAVE_PCIE_6A_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie6b_cfg = {
.name = "qhs_pcie6b_cfg",
- .id = X1E80100_SLAVE_PCIE_6B_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_rsc_cfg = {
.name = "qhs_pcie_rsc_cfg",
- .id = X1E80100_SLAVE_PCIE_RSC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = X1E80100_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = X1E80100_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = X1E80100_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = X1E80100_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = X1E80100_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = X1E80100_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = X1E80100_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = X1E80100_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = X1E80100_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_smmuv3_cfg = {
.name = "qhs_smmuv3_cfg",
- .id = X1E80100_SLAVE_SMMUV3_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = X1E80100_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = X1E80100_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = X1E80100_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb2_0_cfg = {
.name = "qhs_usb2_0_cfg",
- .id = X1E80100_SLAVE_USB2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0_cfg = {
.name = "qhs_usb3_0_cfg",
- .id = X1E80100_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_1_cfg = {
.name = "qhs_usb3_1_cfg",
- .id = X1E80100_SLAVE_USB3_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_2_cfg = {
.name = "qhs_usb3_2_cfg",
- .id = X1E80100_SLAVE_USB3_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_mp_cfg = {
.name = "qhs_usb3_mp_cfg",
- .id = X1E80100_SLAVE_USB3_MP,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb4_0_cfg = {
.name = "qhs_usb4_0_cfg",
- .id = X1E80100_SLAVE_USB4_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb4_1_cfg = {
.name = "qhs_usb4_1_cfg",
- .id = X1E80100_SLAVE_USB4_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb4_2_cfg = {
.name = "qhs_usb4_2_cfg",
- .id = X1E80100_SLAVE_USB4_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = X1E80100_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_lpass_qtb_cfg = {
.name = "qss_lpass_qtb_cfg",
- .id = X1E80100_SLAVE_LPASS_QTB_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_mnoc_cfg = {
.name = "qss_mnoc_cfg",
- .id = X1E80100_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qsm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qss_nsp_qtb_cfg = {
.name = "qss_nsp_qtb_cfg",
- .id = X1E80100_SLAVE_NSP_QTB_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = X1E80100_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = X1E80100_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = X1E80100_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
- .id = X1E80100_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_apss = {
.name = "qns_apss",
- .id = X1E80100_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_cfg = {
.name = "qss_cfg",
- .id = X1E80100_SLAVE_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { X1E80100_MASTER_CNOC_CFG },
+ .link_nodes = { &qsm_cfg, NULL },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = X1E80100_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = X1E80100_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = X1E80100_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = X1E80100_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_2 = {
.name = "xs_pcie_2",
- .id = X1E80100_SLAVE_PCIE_2,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_3 = {
.name = "xs_pcie_3",
- .id = X1E80100_SLAVE_PCIE_3,
.channels = 1,
.buswidth = 64,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_4 = {
.name = "xs_pcie_4",
- .id = X1E80100_SLAVE_PCIE_4,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_5 = {
.name = "xs_pcie_5",
- .id = X1E80100_SLAVE_PCIE_5,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_6a = {
.name = "xs_pcie_6a",
- .id = X1E80100_SLAVE_PCIE_6A,
.channels = 1,
.buswidth = 32,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_6b = {
.name = "xs_pcie_6b",
- .id = X1E80100_SLAVE_PCIE_6B,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = X1E80100_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = X1E80100_SLAVE_LLCC,
.channels = 8,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = X1E80100_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
.name = "qns_lpass_ag_noc_gemnoc",
- .id = X1E80100_SLAVE_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_MASTER_LPASS_GEM_NOC },
+ .link_nodes = { &qnm_lpass, NULL },
};
static struct qcom_icc_node qns_lpass_aggnoc = {
.name = "qns_lpass_aggnoc",
- .id = X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_MASTER_LPIAON_NOC },
+ .link_nodes = { &qnm_lpiaon_noc, NULL },
};
static struct qcom_icc_node qns_lpi_aon_noc = {
.name = "qns_lpi_aon_noc",
- .id = X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { X1E80100_MASTER_LPASS_LPINOC },
+ .link_nodes = { &qnm_lpass_lpinoc, NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = X1E80100_SLAVE_EBI1,
.channels = 8,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = X1E80100_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = X1E80100_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = X1E80100_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { X1E80100_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_nsp_noc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node qns_pcie_north_gem_noc = {
.name = "qns_pcie_north_gem_noc",
- .id = X1E80100_SLAVE_PCIE_NORTH,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_MASTER_PCIE_NORTH },
+ .link_nodes = { &qnm_pcie_north_gem_noc, NULL },
};
static struct qcom_icc_node qns_pcie_south_gem_noc = {
.name = "qns_pcie_south_gem_noc",
- .id = X1E80100_SLAVE_PCIE_SOUTH,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_MASTER_PCIE_SOUTH },
+ .link_nodes = { &qnm_pcie_south_gem_noc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = X1E80100_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qns_aggre_usb_snoc = {
.name = "qns_aggre_usb_snoc",
- .id = X1E80100_SLAVE_USB_NOC_SNOC,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_MASTER_USB_NOC_SNOC },
+ .link_nodes = { &qnm_usb_anoc, NULL },
};
static struct qcom_icc_node qns_aggre_usb_north_snoc = {
.name = "qns_aggre_usb_north_snoc",
- .id = X1E80100_SLAVE_AGGRE_USB_NORTH,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_MASTER_AGGRE_USB_NORTH },
+ .link_nodes = { &qnm_aggre_usb_north_snoc, NULL },
};
static struct qcom_icc_node qns_aggre_usb_south_snoc = {
.name = "qns_aggre_usb_south_snoc",
- .id = X1E80100_SLAVE_AGGRE_USB_SOUTH,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { X1E80100_MASTER_AGGRE_USB_SOUTH },
+ .link_nodes = { &qnm_aggre_usb_south_snoc, NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1512,6 +1424,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1534,6 +1447,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1556,6 +1470,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1619,6 +1534,7 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_cnoc_cfg = {
+ .alloc_dyn_id = true,
.nodes = cnoc_cfg_nodes,
.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
.bcms = cnoc_cfg_bcms,
@@ -1649,6 +1565,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_cnoc_main = {
+ .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
@@ -1679,6 +1596,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1694,6 +1612,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1710,6 +1629,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
@@ -1725,6 +1645,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
.bcms = lpass_lpicx_noc_bcms,
@@ -1742,6 +1663,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1770,6 +1692,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1786,6 +1709,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_nsp_noc = {
+ .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1803,6 +1727,7 @@ static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_center_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes),
.bcms = pcie_center_anoc_bcms,
@@ -1820,6 +1745,7 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_north_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes),
.bcms = pcie_north_anoc_bcms,
@@ -1839,6 +1765,7 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_south_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes),
.bcms = pcie_south_anoc_bcms,
@@ -1861,6 +1788,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
@@ -1877,6 +1805,7 @@ static struct qcom_icc_node * const usb_center_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_usb_center_anoc = {
+ .alloc_dyn_id = true,
.nodes = usb_center_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_center_anoc_nodes),
.bcms = usb_center_anoc_bcms,
@@ -1893,6 +1822,7 @@ static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_usb_north_anoc = {
+ .alloc_dyn_id = true,
.nodes = usb_north_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_north_anoc_nodes),
.bcms = usb_north_anoc_bcms,
@@ -1913,6 +1843,7 @@ static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_usb_south_anoc = {
+ .alloc_dyn_id = true,
.nodes = usb_south_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_south_anoc_nodes),
.bcms = usb_south_anoc_bcms,
diff --git a/drivers/interconnect/qcom/x1e80100.h b/drivers/interconnect/qcom/x1e80100.h
deleted file mode 100644
index 2e14264f4c2b01d6c4e3fe63a5f5252dc6d29641..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/x1e80100.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * X1E80100 interconnect IDs
- *
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
- * Copyright (c) 2023, Linaro Limited
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_X1E80100_H
-#define __DRIVERS_INTERCONNECT_QCOM_X1E80100_H
-
-#define X1E80100_MASTER_A1NOC_SNOC 0
-#define X1E80100_MASTER_A2NOC_SNOC 1
-#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC 2
-#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP 3
-#define X1E80100_MASTER_APPSS_PROC 4
-#define X1E80100_MASTER_CAMNOC_HF 5
-#define X1E80100_MASTER_CAMNOC_ICP 6
-#define X1E80100_MASTER_CAMNOC_SF 7
-#define X1E80100_MASTER_CDSP_PROC 8
-#define X1E80100_MASTER_CNOC_CFG 9
-#define X1E80100_MASTER_CNOC_MNOC_CFG 10
-#define X1E80100_MASTER_COMPUTE_NOC 11
-#define X1E80100_MASTER_CRYPTO 12
-#define X1E80100_MASTER_GEM_NOC_CNOC 13
-#define X1E80100_MASTER_GEM_NOC_PCIE_SNOC 14
-#define X1E80100_MASTER_GFX3D 15
-#define X1E80100_MASTER_GPU_TCU 16
-#define X1E80100_MASTER_IPA 17
-#define X1E80100_MASTER_LLCC 18
-#define X1E80100_MASTER_LLCC_DISP 19
-#define X1E80100_MASTER_LPASS_GEM_NOC 20
-#define X1E80100_MASTER_LPASS_LPINOC 21
-#define X1E80100_MASTER_LPASS_PROC 22
-#define X1E80100_MASTER_LPIAON_NOC 23
-#define X1E80100_MASTER_MDP 24
-#define X1E80100_MASTER_MDP_DISP 25
-#define X1E80100_MASTER_MNOC_HF_MEM_NOC 26
-#define X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP 27
-#define X1E80100_MASTER_MNOC_SF_MEM_NOC 28
-#define X1E80100_MASTER_PCIE_0 29
-#define X1E80100_MASTER_PCIE_1 30
-#define X1E80100_MASTER_QDSS_ETR 31
-#define X1E80100_MASTER_QDSS_ETR_1 32
-#define X1E80100_MASTER_QSPI_0 33
-#define X1E80100_MASTER_QUP_0 34
-#define X1E80100_MASTER_QUP_1 35
-#define X1E80100_MASTER_QUP_2 36
-#define X1E80100_MASTER_QUP_CORE_0 37
-#define X1E80100_MASTER_QUP_CORE_1 38
-#define X1E80100_MASTER_SDCC_2 39
-#define X1E80100_MASTER_SDCC_4 40
-#define X1E80100_MASTER_SNOC_SF_MEM_NOC 41
-#define X1E80100_MASTER_SP 42
-#define X1E80100_MASTER_SYS_TCU 43
-#define X1E80100_MASTER_UFS_MEM 44
-#define X1E80100_MASTER_USB3_0 45
-#define X1E80100_MASTER_VIDEO 46
-#define X1E80100_MASTER_VIDEO_CV_PROC 47
-#define X1E80100_MASTER_VIDEO_V_PROC 48
-#define X1E80100_SLAVE_A1NOC_SNOC 49
-#define X1E80100_SLAVE_A2NOC_SNOC 50
-#define X1E80100_SLAVE_AHB2PHY_NORTH 51
-#define X1E80100_SLAVE_AHB2PHY_SOUTH 52
-#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC 53
-#define X1E80100_SLAVE_AOSS 54
-#define X1E80100_SLAVE_APPSS 55
-#define X1E80100_SLAVE_BOOT_IMEM 56
-#define X1E80100_SLAVE_CAMERA_CFG 57
-#define X1E80100_SLAVE_CDSP_MEM_NOC 58
-#define X1E80100_SLAVE_CLK_CTL 59
-#define X1E80100_SLAVE_CNOC_CFG 60
-#define X1E80100_SLAVE_CNOC_MNOC_CFG 61
-#define X1E80100_SLAVE_CRYPTO_0_CFG 62
-#define X1E80100_SLAVE_DISPLAY_CFG 63
-#define X1E80100_SLAVE_EBI1 64
-#define X1E80100_SLAVE_EBI1_DISP 65
-#define X1E80100_SLAVE_GEM_NOC_CNOC 66
-#define X1E80100_SLAVE_GFX3D_CFG 67
-#define X1E80100_SLAVE_IMEM 68
-#define X1E80100_SLAVE_IMEM_CFG 69
-#define X1E80100_SLAVE_IPC_ROUTER_CFG 70
-#define X1E80100_SLAVE_LLCC 71
-#define X1E80100_SLAVE_LLCC_DISP 72
-#define X1E80100_SLAVE_LPASS_GEM_NOC 73
-#define X1E80100_SLAVE_LPASS_QTB_CFG 74
-#define X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC 75
-#define X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC 76
-#define X1E80100_SLAVE_MEM_NOC_PCIE_SNOC 77
-#define X1E80100_SLAVE_MNOC_HF_MEM_NOC 78
-#define X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP 79
-#define X1E80100_SLAVE_MNOC_SF_MEM_NOC 80
-#define X1E80100_SLAVE_NSP_QTB_CFG 81
-#define X1E80100_SLAVE_PCIE_0 82
-#define X1E80100_SLAVE_PCIE_0_CFG 83
-#define X1E80100_SLAVE_PCIE_1 84
-#define X1E80100_SLAVE_PCIE_1_CFG 85
-#define X1E80100_SLAVE_PDM 86
-#define X1E80100_SLAVE_PRNG 87
-#define X1E80100_SLAVE_QDSS_CFG 88
-#define X1E80100_SLAVE_QDSS_STM 89
-#define X1E80100_SLAVE_QSPI_0 90
-#define X1E80100_SLAVE_QUP_1 91
-#define X1E80100_SLAVE_QUP_2 92
-#define X1E80100_SLAVE_QUP_CORE_0 93
-#define X1E80100_SLAVE_QUP_CORE_1 94
-#define X1E80100_SLAVE_QUP_CORE_2 95
-#define X1E80100_SLAVE_SDCC_2 96
-#define X1E80100_SLAVE_SDCC_4 97
-#define X1E80100_SLAVE_SERVICE_MNOC 98
-#define X1E80100_SLAVE_SNOC_GEM_NOC_SF 99
-#define X1E80100_SLAVE_TCSR 100
-#define X1E80100_SLAVE_TCU 101
-#define X1E80100_SLAVE_TLMM 102
-#define X1E80100_SLAVE_TME_CFG 103
-#define X1E80100_SLAVE_UFS_MEM_CFG 104
-#define X1E80100_SLAVE_USB3_0 105
-#define X1E80100_SLAVE_VENUS_CFG 106
-#define X1E80100_MASTER_DDR_PERF_MODE 107
-#define X1E80100_MASTER_QUP_CORE_2 108
-#define X1E80100_MASTER_PCIE_TCU 109
-#define X1E80100_MASTER_GIC2 110
-#define X1E80100_MASTER_AV1_ENC 111
-#define X1E80100_MASTER_EVA 112
-#define X1E80100_MASTER_PCIE_NORTH 113
-#define X1E80100_MASTER_PCIE_SOUTH 114
-#define X1E80100_MASTER_PCIE_3 115
-#define X1E80100_MASTER_PCIE_4 116
-#define X1E80100_MASTER_PCIE_5 117
-#define X1E80100_MASTER_PCIE_2 118
-#define X1E80100_MASTER_PCIE_6A 119
-#define X1E80100_MASTER_PCIE_6B 120
-#define X1E80100_MASTER_GIC1 121
-#define X1E80100_MASTER_USB_NOC_SNOC 122
-#define X1E80100_MASTER_AGGRE_USB_NORTH 123
-#define X1E80100_MASTER_AGGRE_USB_SOUTH 124
-#define X1E80100_MASTER_USB2 125
-#define X1E80100_MASTER_USB3_MP 126
-#define X1E80100_MASTER_USB3_1 127
-#define X1E80100_MASTER_USB3_2 128
-#define X1E80100_MASTER_USB4_0 129
-#define X1E80100_MASTER_USB4_1 130
-#define X1E80100_MASTER_USB4_2 131
-#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE 132
-#define X1E80100_MASTER_LLCC_PCIE 133
-#define X1E80100_MASTER_PCIE_NORTH_PCIE 134
-#define X1E80100_MASTER_PCIE_SOUTH_PCIE 135
-#define X1E80100_MASTER_PCIE_3_PCIE 136
-#define X1E80100_MASTER_PCIE_4_PCIE 137
-#define X1E80100_MASTER_PCIE_5_PCIE 138
-#define X1E80100_MASTER_PCIE_0_PCIE 139
-#define X1E80100_MASTER_PCIE_1_PCIE 140
-#define X1E80100_MASTER_PCIE_2_PCIE 141
-#define X1E80100_MASTER_PCIE_6A_PCIE 142
-#define X1E80100_MASTER_PCIE_6B_PCIE 143
-#define X1E80100_SLAVE_AHB2PHY_2 144
-#define X1E80100_SLAVE_AV1_ENC_CFG 145
-#define X1E80100_SLAVE_PCIE_2_CFG 146
-#define X1E80100_SLAVE_PCIE_3_CFG 147
-#define X1E80100_SLAVE_PCIE_4_CFG 148
-#define X1E80100_SLAVE_PCIE_5_CFG 149
-#define X1E80100_SLAVE_PCIE_6A_CFG 150
-#define X1E80100_SLAVE_PCIE_6B_CFG 151
-#define X1E80100_SLAVE_PCIE_RSC_CFG 152
-#define X1E80100_SLAVE_QUP_0 153
-#define X1E80100_SLAVE_SMMUV3_CFG 154
-#define X1E80100_SLAVE_USB2 155
-#define X1E80100_SLAVE_USB3_1 156
-#define X1E80100_SLAVE_USB3_2 157
-#define X1E80100_SLAVE_USB3_MP 158
-#define X1E80100_SLAVE_USB4_0 159
-#define X1E80100_SLAVE_USB4_1 160
-#define X1E80100_SLAVE_USB4_2 161
-#define X1E80100_SLAVE_PCIE_2 162
-#define X1E80100_SLAVE_PCIE_3 163
-#define X1E80100_SLAVE_PCIE_4 164
-#define X1E80100_SLAVE_PCIE_5 165
-#define X1E80100_SLAVE_PCIE_6A 166
-#define X1E80100_SLAVE_PCIE_6B 167
-#define X1E80100_SLAVE_DDR_PERF_MODE 168
-#define X1E80100_SLAVE_PCIE_NORTH 169
-#define X1E80100_SLAVE_PCIE_SOUTH 170
-#define X1E80100_SLAVE_USB_NOC_SNOC 171
-#define X1E80100_SLAVE_AGGRE_USB_NORTH 172
-#define X1E80100_SLAVE_AGGRE_USB_SOUTH 173
-#define X1E80100_SLAVE_LLCC_PCIE 174
-#define X1E80100_SLAVE_EBI1_PCIE 175
-#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE 176
-#define X1E80100_SLAVE_PCIE_NORTH_PCIE 177
-#define X1E80100_SLAVE_PCIE_SOUTH_PCIE 178
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 11/28] interconnect: qcom: qcs615: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (9 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 10/28] interconnect: qcom: x1e80100: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 12/28] interconnect: qcom: qcs8300: " Dmitry Baryshkov
` (17 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/qcs615.c | 644 +++++++++++++++++--------------------
drivers/interconnect/qcom/qcs615.h | 128 --------
2 files changed, 293 insertions(+), 479 deletions(-)
diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom/qcs615.c
index acf452b5ed023b2e42b23f7455e57ab124bfa524..4fc58de384e9dec2364d78e89630ef61d0338155 100644
--- a/drivers/interconnect/qcom/qcs615.c
+++ b/drivers/interconnect/qcom/qcs615.c
@@ -13,1058 +13,991 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "qcs615.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qnm_cnoc;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_emac_avb;
+static struct qcom_icc_node xm_pcie;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb2;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node qxm_camnoc_hf1_uncomp;
+static struct qcom_icc_node qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node qhm_spdm;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qhm_cnoc;
+static struct qcom_icc_node acm_apps;
+static struct qcom_icc_node acm_gpu_tcu;
+static struct qcom_icc_node acm_sys_tcu;
+static struct qcom_icc_node qhm_gemnoc_cfg;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node ipa_core_master;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qxm_camnoc_hf0;
+static struct qcom_icc_node qxm_camnoc_hf1;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node qxm_venus0;
+static struct qcom_icc_node qxm_venus_arm9;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_gemnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qnm_lpass_anoc;
+static struct qcom_icc_node qnm_pcie_anoc;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_lpass_snoc;
+static struct qcom_icc_node qns_pcie_snoc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_camnoc_uncomp;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_ahb2phy_east;
+static struct qcom_icc_node qhs_ahb2phy_west;
+static struct qcom_icc_node qhs_aop;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_emac_avb_cfg;
+static struct qcom_icc_node qhs_glm;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_pcie_config;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_spdm;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm_east;
+static struct qcom_icc_node qhs_tlmm_south;
+static struct qcom_icc_node qhs_tlmm_west;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb2;
+static struct qcom_icc_node qhs_usb3;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_dc_noc_gemnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qns_gem_noc_snoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_sys_pcie;
+static struct qcom_icc_node srvc_gemnoc;
+static struct qcom_icc_node ipa_core_slave;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns2_mem_noc;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qns_memnoc_gc;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_pcie;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qhm_a1noc_cfg = {
.name = "qhm_a1noc_cfg",
- .id = QCS615_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = QCS615_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = QCS615_MASTER_QSPI,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = QCS615_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = QCS615_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
- .id = QCS615_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = QCS615_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = QCS615_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_LPASS_SNOC },
+ .link_nodes = { &qns_lpass_snoc, NULL },
};
static struct qcom_icc_node xm_emac_avb = {
.name = "xm_emac_avb",
- .id = QCS615_MASTER_EMAC_EVB,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
- .id = QCS615_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_ANOC_PCIE_SNOC },
+ .link_nodes = { &qns_pcie_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = QCS615_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = QCS615_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = QCS615_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = QCS615_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb2 = {
.name = "xm_usb2",
- .id = QCS615_MASTER_USB2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = QCS615_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
.name = "qxm_camnoc_hf0_uncomp",
- .id = QCS615_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
.name = "qxm_camnoc_hf1_uncomp",
- .id = QCS615_MASTER_CAMNOC_HF1_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
.name = "qxm_camnoc_sf_uncomp",
- .id = QCS615_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qhm_spdm = {
.name = "qhm_spdm",
- .id = QCS615_MASTER_SPDM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_CNOC_A2NOC },
+ .link_nodes = { &qns_cnoc_a2noc, NULL },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = QCS615_MASTER_SNOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 39,
- .links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST,
- QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP,
- QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG,
- QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG,
- QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG,
- QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG,
- QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM,
- QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG,
- QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG,
- QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG,
- QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG,
- QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0,
- QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1,
- QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG,
- QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR,
- QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH,
- QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG,
- QCS615_SLAVE_USB2, QCS615_SLAVE_USB3,
- QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG,
- QCS615_SLAVE_SERVICE_CNOC },
+ .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east,
+ &qhs_ahb2phy_west, &qhs_aop,
+ &qhs_aoss, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_cpr_cx,
+ &qhs_cpr_mx, &qhs_crypto0_cfg,
+ &qhs_ddrss_cfg, &qhs_display_cfg,
+ &qhs_emac_avb_cfg, &qhs_glm,
+ &qhs_gpuss_cfg, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_mnoc_cfg,
+ &qhs_pcie_config, &qhs_pimem_cfg,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc1,
+ &qhs_sdc2, &qhs_snoc_cfg,
+ &qhs_spdm, &qhs_tcsr,
+ &qhs_tlmm_east, &qhs_tlmm_south,
+ &qhs_tlmm_west, &qhs_ufs_mem_cfg,
+ &qhs_usb2, &qhs_usb3,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = QCS615_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 40,
- .links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST,
- QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP,
- QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG,
- QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG,
- QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG,
- QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG,
- QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM,
- QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG,
- QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG,
- QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG,
- QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG,
- QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0,
- QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1,
- QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG,
- QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR,
- QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH,
- QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG,
- QCS615_SLAVE_USB2, QCS615_SLAVE_USB3,
- QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG,
- QCS615_SLAVE_CNOC_A2NOC, QCS615_SLAVE_SERVICE_CNOC },
+ .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east,
+ &qhs_ahb2phy_west, &qhs_aop,
+ &qhs_aoss, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_cpr_cx,
+ &qhs_cpr_mx, &qhs_crypto0_cfg,
+ &qhs_ddrss_cfg, &qhs_display_cfg,
+ &qhs_emac_avb_cfg, &qhs_glm,
+ &qhs_gpuss_cfg, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_mnoc_cfg,
+ &qhs_pcie_config, &qhs_pimem_cfg,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc1,
+ &qhs_sdc2, &qhs_snoc_cfg,
+ &qhs_spdm, &qhs_tcsr,
+ &qhs_tlmm_east, &qhs_tlmm_south,
+ &qhs_tlmm_west, &qhs_ufs_mem_cfg,
+ &qhs_usb2, &qhs_usb3,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qns_cnoc_a2noc, &srvc_cnoc, NULL },
};
static struct qcom_icc_node qhm_cnoc = {
.name = "qhm_cnoc",
- .id = QCS615_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { QCS615_SLAVE_DC_NOC_GEMNOC, QCS615_SLAVE_LLCC_CFG },
+ .link_nodes = { &qhs_dc_noc_gemnoc, &qhs_llcc, NULL },
};
static struct qcom_icc_node acm_apps = {
.name = "acm_apps",
- .id = QCS615_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC,
- QCS615_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_snoc, &qns_llcc,
+ &qns_sys_pcie, NULL },
};
static struct qcom_icc_node acm_gpu_tcu = {
.name = "acm_gpu_tcu",
- .id = QCS615_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_snoc, &qns_llcc, NULL },
};
static struct qcom_icc_node acm_sys_tcu = {
.name = "acm_sys_tcu",
- .id = QCS615_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_snoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qhm_gemnoc_cfg = {
.name = "qhm_gemnoc_cfg",
- .id = QCS615_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, QCS615_SLAVE_SERVICE_GEM_NOC },
+ .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &srvc_gemnoc, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = QCS615_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_snoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = QCS615_MASTER_MNOC_HF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = QCS615_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_snoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = QCS615_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = QCS615_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS615_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node ipa_core_master = {
.name = "ipa_core_master",
- .id = QCS615_MASTER_IPA_CORE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_IPA_CORE },
+ .link_nodes = { &ipa_core_slave, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = QCS615_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = QCS615_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0 = {
.name = "qxm_camnoc_hf0",
- .id = QCS615_MASTER_CAMNOC_HF0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1 = {
.name = "qxm_camnoc_hf1",
- .id = QCS615_MASTER_CAMNOC_HF1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = QCS615_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = QCS615_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = QCS615_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus0 = {
.name = "qxm_venus0",
- .id = QCS615_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus_arm9 = {
.name = "qxm_venus_arm9",
- .id = QCS615_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = QCS615_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = QCS615_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 8,
- .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
- QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
- QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0,
- QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU },
+ .link_nodes = { &qhs_apss, &qns_cnoc,
+ &qns_gemnoc_sf, &qxs_imem,
+ &qxs_pimem, &xs_pcie,
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc = {
.name = "qnm_gemnoc",
- .id = QCS615_MASTER_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 6,
- .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
- QCS615_SLAVE_IMEM, QCS615_SLAVE_PIMEM,
- QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU },
+ .link_nodes = { &qhs_apss, &qns_cnoc,
+ &qxs_imem, &qxs_pimem,
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = QCS615_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_SLAVE_PCIE_0 },
+ .link_nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_node qnm_lpass_anoc = {
.name = "qnm_lpass_anoc",
- .id = QCS615_MASTER_LPASS_ANOC,
.channels = 1,
.buswidth = 8,
- .num_links = 7,
- .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
- QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
- QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0,
- QCS615_SLAVE_QDSS_STM },
+ .link_nodes = { &qhs_apss, &qns_cnoc,
+ &qns_gemnoc_sf, &qxs_imem,
+ &qxs_pimem, &xs_pcie,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_pcie_anoc = {
.name = "qnm_pcie_anoc",
- .id = QCS615_MASTER_ANOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 5,
- .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
- QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
- QCS615_SLAVE_QDSS_STM },
+ .link_nodes = { &qhs_apss, &qns_cnoc,
+ &qns_gemnoc_sf, &qxs_imem,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = QCS615_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM },
+ .link_nodes = { &qns_memnoc_gc, &qxs_imem, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = QCS615_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM },
+ .link_nodes = { &qns_memnoc_gc, &qxs_imem, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = QCS615_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS615_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_lpass_snoc = {
.name = "qns_lpass_snoc",
- .id = QCS615_SLAVE_LPASS_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_MASTER_LPASS_ANOC },
+ .link_nodes = { &qnm_lpass_anoc, NULL },
};
static struct qcom_icc_node qns_pcie_snoc = {
.name = "qns_pcie_snoc",
- .id = QCS615_SLAVE_ANOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_MASTER_ANOC_PCIE_SNOC },
+ .link_nodes = { &qnm_pcie_anoc, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = QCS615_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_camnoc_uncomp = {
.name = "qns_camnoc_uncomp",
- .id = QCS615_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = QCS615_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qhs_ahb2phy_east = {
.name = "qhs_ahb2phy_east",
- .id = QCS615_SLAVE_AHB2PHY_EAST,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy_west = {
.name = "qhs_ahb2phy_west",
- .id = QCS615_SLAVE_AHB2PHY_WEST,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
- .id = QCS615_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = QCS615_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = QCS615_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = QCS615_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = QCS615_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = QCS615_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = QCS615_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = QCS615_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc, NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = QCS615_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emac_avb_cfg = {
.name = "qhs_emac_avb_cfg",
- .id = QCS615_SLAVE_EMAC_AVB_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_glm = {
.name = "qhs_glm",
- .id = QCS615_SLAVE_GLM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = QCS615_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = QCS615_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = QCS615_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = QCS615_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_pcie_config = {
.name = "qhs_pcie_config",
- .id = QCS615_SLAVE_PCIE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = QCS615_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = QCS615_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = QCS615_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = QCS615_SLAVE_QSPI,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = QCS615_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = QCS615_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = QCS615_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = QCS615_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = QCS615_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_spdm = {
.name = "qhs_spdm",
- .id = QCS615_SLAVE_SPDM_WRAPPER,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = QCS615_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_east = {
.name = "qhs_tlmm_east",
- .id = QCS615_SLAVE_TLMM_EAST,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_south = {
.name = "qhs_tlmm_south",
- .id = QCS615_SLAVE_TLMM_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_west = {
.name = "qhs_tlmm_west",
- .id = QCS615_SLAVE_TLMM_WEST,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = QCS615_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb2 = {
.name = "qhs_usb2",
- .id = QCS615_SLAVE_USB2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
- .id = QCS615_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = QCS615_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = QCS615_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = QCS615_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc, NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = QCS615_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dc_noc_gemnoc = {
.name = "qhs_dc_noc_gemnoc",
- .id = QCS615_SLAVE_DC_NOC_GEMNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS615_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qhm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = QCS615_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = QCS615_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_snoc = {
.name = "qns_gem_noc_snoc",
- .id = QCS615_SLAVE_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_MASTER_GEM_NOC_SNOC },
+ .link_nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = QCS615_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS615_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_sys_pcie = {
.name = "qns_sys_pcie",
- .id = QCS615_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node srvc_gemnoc = {
.name = "srvc_gemnoc",
- .id = QCS615_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ipa_core_slave = {
.name = "ipa_core_slave",
- .id = QCS615_SLAVE_IPA_CORE,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = QCS615_SLAVE_EBI1,
.channels = 2,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns2_mem_noc = {
.name = "qns2_mem_noc",
- .id = QCS615_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = QCS615_SLAVE_MNOC_HF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS615_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = QCS615_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = QCS615_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = QCS615_SLAVE_SNOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_MASTER_SNOC_CNOC },
+ .link_nodes = { &qnm_snoc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = QCS615_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS615_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qns_memnoc_gc = {
.name = "qns_memnoc_gc",
- .id = QCS615_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS615_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = QCS615_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = QCS615_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = QCS615_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
- .id = QCS615_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = QCS615_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = QCS615_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1261,6 +1194,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1279,6 +1213,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs615_camnoc_virt = {
+ .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1337,6 +1272,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1350,6 +1286,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@@ -1379,6 +1316,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1395,6 +1333,7 @@ static struct qcom_icc_node * const ipa_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs615_ipa_virt = {
+ .alloc_dyn_id = true,
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
@@ -1412,6 +1351,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs615_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1440,6 +1380,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1482,6 +1423,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/qcs615.h b/drivers/interconnect/qcom/qcs615.h
deleted file mode 100644
index 66e66c7e23d4ecaf92c2697e695980c3f8663664..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/qcs615.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS615_H
-#define __DRIVERS_INTERCONNECT_QCOM_QCS615_H
-
-#define QCS615_MASTER_A1NOC_CFG 1
-#define QCS615_MASTER_A1NOC_SNOC 2
-#define QCS615_MASTER_ANOC_PCIE_SNOC 3
-#define QCS615_MASTER_APPSS_PROC 4
-#define QCS615_MASTER_BLSP_1 5
-#define QCS615_MASTER_CAMNOC_HF0 6
-#define QCS615_MASTER_CAMNOC_HF0_UNCOMP 7
-#define QCS615_MASTER_CAMNOC_HF1 8
-#define QCS615_MASTER_CAMNOC_HF1_UNCOMP 9
-#define QCS615_MASTER_CAMNOC_SF 10
-#define QCS615_MASTER_CAMNOC_SF_UNCOMP 11
-#define QCS615_MASTER_CNOC_A2NOC 12
-#define QCS615_MASTER_CNOC_DC_NOC 13
-#define QCS615_MASTER_CNOC_MNOC_CFG 14
-#define QCS615_MASTER_CRYPTO 15
-#define QCS615_MASTER_EMAC_EVB 16
-#define QCS615_MASTER_GEM_NOC_CFG 17
-#define QCS615_MASTER_GEM_NOC_PCIE_SNOC 18
-#define QCS615_MASTER_GEM_NOC_SNOC 19
-#define QCS615_MASTER_GFX3D 20
-#define QCS615_MASTER_GIC 21
-#define QCS615_MASTER_GPU_TCU 22
-#define QCS615_MASTER_IPA 23
-#define QCS615_MASTER_IPA_CORE 24
-#define QCS615_MASTER_LLCC 25
-#define QCS615_MASTER_LPASS_ANOC 26
-#define QCS615_MASTER_MDP0 27
-#define QCS615_MASTER_MNOC_HF_MEM_NOC 28
-#define QCS615_MASTER_MNOC_SF_MEM_NOC 29
-#define QCS615_MASTER_PCIE 30
-#define QCS615_MASTER_PIMEM 31
-#define QCS615_MASTER_QDSS_BAM 32
-#define QCS615_MASTER_QDSS_DAP 33
-#define QCS615_MASTER_QDSS_ETR 34
-#define QCS615_MASTER_QSPI 35
-#define QCS615_MASTER_QUP_0 36
-#define QCS615_MASTER_ROTATOR 37
-#define QCS615_MASTER_SDCC_1 38
-#define QCS615_MASTER_SDCC_2 39
-#define QCS615_MASTER_SNOC_CFG 40
-#define QCS615_MASTER_SNOC_CNOC 41
-#define QCS615_MASTER_SNOC_GC_MEM_NOC 42
-#define QCS615_MASTER_SNOC_SF_MEM_NOC 43
-#define QCS615_MASTER_SPDM 44
-#define QCS615_MASTER_SYS_TCU 45
-#define QCS615_MASTER_UFS_MEM 46
-#define QCS615_MASTER_USB2 47
-#define QCS615_MASTER_USB3_0 48
-#define QCS615_MASTER_VIDEO_P0 49
-#define QCS615_MASTER_VIDEO_PROC 50
-#define QCS615_SLAVE_A1NOC_CFG 51
-#define QCS615_SLAVE_A1NOC_SNOC 52
-#define QCS615_SLAVE_AHB2PHY_EAST 53
-#define QCS615_SLAVE_AHB2PHY_WEST 54
-#define QCS615_SLAVE_ANOC_PCIE_SNOC 55
-#define QCS615_SLAVE_AOP 56
-#define QCS615_SLAVE_AOSS 57
-#define QCS615_SLAVE_APPSS 58
-#define QCS615_SLAVE_CAMERA_CFG 59
-#define QCS615_SLAVE_CAMNOC_UNCOMP 60
-#define QCS615_SLAVE_CLK_CTL 61
-#define QCS615_SLAVE_CNOC_A2NOC 62
-#define QCS615_SLAVE_CNOC_DDRSS 63
-#define QCS615_SLAVE_CNOC_MNOC_CFG 64
-#define QCS615_SLAVE_CRYPTO_0_CFG 65
-#define QCS615_SLAVE_DC_NOC_GEMNOC 66
-#define QCS615_SLAVE_DISPLAY_CFG 67
-#define QCS615_SLAVE_EBI1 68
-#define QCS615_SLAVE_EMAC_AVB_CFG 69
-#define QCS615_SLAVE_GEM_NOC_SNOC 70
-#define QCS615_SLAVE_GFX3D_CFG 71
-#define QCS615_SLAVE_GLM 72
-#define QCS615_SLAVE_IMEM 73
-#define QCS615_SLAVE_IMEM_CFG 74
-#define QCS615_SLAVE_IPA_CFG 75
-#define QCS615_SLAVE_IPA_CORE 76
-#define QCS615_SLAVE_LLCC 77
-#define QCS615_SLAVE_LLCC_CFG 78
-#define QCS615_SLAVE_LPASS_SNOC 79
-#define QCS615_SLAVE_MEM_NOC_PCIE_SNOC 80
-#define QCS615_SLAVE_MNOC_HF_MEM_NOC 81
-#define QCS615_SLAVE_MNOC_SF_MEM_NOC 82
-#define QCS615_SLAVE_MSS_PROC_MS_MPU_CFG 83
-#define QCS615_SLAVE_PCIE_0 84
-#define QCS615_SLAVE_PCIE_CFG 85
-#define QCS615_SLAVE_PIMEM 86
-#define QCS615_SLAVE_PIMEM_CFG 87
-#define QCS615_SLAVE_PRNG 88
-#define QCS615_SLAVE_QDSS_CFG 89
-#define QCS615_SLAVE_QDSS_STM 90
-#define QCS615_SLAVE_QSPI 91
-#define QCS615_SLAVE_QUP_0 92
-#define QCS615_SLAVE_QUP_1 93
-#define QCS615_SLAVE_RBCPR_CX_CFG 94
-#define QCS615_SLAVE_RBCPR_MX_CFG 95
-#define QCS615_SLAVE_SDCC_1 96
-#define QCS615_SLAVE_SDCC_2 97
-#define QCS615_SLAVE_SERVICE_A2NOC 98
-#define QCS615_SLAVE_SERVICE_CNOC 99
-#define QCS615_SLAVE_SERVICE_GEM_NOC 100
-#define QCS615_SLAVE_SERVICE_MNOC 101
-#define QCS615_SLAVE_SERVICE_SNOC 102
-#define QCS615_SLAVE_SNOC_CFG 103
-#define QCS615_SLAVE_SNOC_CNOC 104
-#define QCS615_SLAVE_SNOC_GEM_NOC_SF 105
-#define QCS615_SLAVE_SNOC_MEM_NOC_GC 106
-#define QCS615_SLAVE_SPDM_WRAPPER 107
-#define QCS615_SLAVE_TCSR 108
-#define QCS615_SLAVE_TCU 109
-#define QCS615_SLAVE_TLMM_EAST 110
-#define QCS615_SLAVE_TLMM_SOUTH 111
-#define QCS615_SLAVE_TLMM_WEST 112
-#define QCS615_SLAVE_UFS_MEM_CFG 113
-#define QCS615_SLAVE_USB2 114
-#define QCS615_SLAVE_USB3 115
-#define QCS615_SLAVE_VENUS_CFG 116
-#define QCS615_SLAVE_VSENSE_CTRL_CFG 117
-
-#endif
-
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 12/28] interconnect: qcom: qcs8300: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (10 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 11/28] interconnect: qcom: qcs615: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 13/28] interconnect: qcom: qdu1000: " Dmitry Baryshkov
` (16 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/qcs8300.c | 849 +++++++++++++++++-------------------
drivers/interconnect/qcom/qcs8300.h | 177 --------
2 files changed, 391 insertions(+), 635 deletions(-)
diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qcom/qcs8300.c
index 0987a7e9dddda298b1afca4ad95f6d8a909d57e6..ebe9a2eab554bcb199497e4efbfbebeec3bb2c53 100644
--- a/drivers/interconnect/qcom/qcs8300.c
+++ b/drivers/interconnect/qcom/qcs8300.c
@@ -13,1465 +13,1385 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "qcs8300.h"
+
+static struct qcom_icc_node qxm_qup3;
+static struct qcom_icc_node xm_emac_0;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb2_2;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qnm_cnoc_datapath;
+static struct qcom_icc_node qxm_crypto_0;
+static struct qcom_icc_node qxm_crypto_1;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup3_core_master;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qnm_cnoc_dc_noc;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_pcie_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_cmpnoc0;
+static struct qcom_icc_node qnm_gemnoc_cfg;
+static struct qcom_icc_node qnm_gpdsp_sail;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qnm_sailss_md0;
+static struct qcom_icc_node qxm_dsp0;
+static struct qcom_icc_node qhm_config_noc;
+static struct qcom_icc_node qxm_lpass_dsp;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_mdp0_0;
+static struct qcom_icc_node qnm_mdp0_1;
+static struct qcom_icc_node qnm_mnoc_hf_cfg;
+static struct qcom_icc_node qnm_mnoc_sf_cfg;
+static struct qcom_icc_node qnm_video0;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qhm_nsp_noc_config;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node qhm_gic;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_lpass_noc;
+static struct qcom_icc_node qnm_snoc_cfg;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup3_core_slave;
+static struct qcom_icc_node qhs_ahb2phy2;
+static struct qcom_icc_node qhs_ahb2phy3;
+static struct qcom_icc_node qhs_anoc_throttle_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qhs_boot_rom;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_camera_nrt_throttle_cfg;
+static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute0_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_cpr_nspcx;
+static struct qcom_icc_node qhs_cpr_nsphmx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_display0_cfg;
+static struct qcom_icc_node qhs_display0_rt_throttle_cfg;
+static struct qcom_icc_node qhs_emac0_cfg;
+static struct qcom_icc_node qhs_gp_dsp0_cfg;
+static struct qcom_icc_node qhs_gpdsp0_throttle_cfg;
+static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_hwkm;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_lpass_throttle_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_mxc_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg;
+static struct qcom_icc_node qhs_pcie_throttle_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_pke_wrapper_cfg;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qm_cfg;
+static struct qcom_icc_node qhs_qm_mpu_cfg;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup3;
+static struct qcom_icc_node qhs_sail_throttle_cfg;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_security;
+static struct qcom_icc_node qhs_snoc_throttle_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_tsc_cfg;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb2_0;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_venus_cvp_throttle_cfg;
+static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg;
+static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qns_gpdsp_noc_cfg;
+static struct qcom_icc_node qns_mnoc_hf_cfg;
+static struct qcom_icc_node qns_mnoc_sf_cfg;
+static struct qcom_icc_node qns_pcie_anoc_cfg;
+static struct qcom_icc_node qns_snoc_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qns_gemnoc;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node srvc_even_gemnoc;
+static struct qcom_icc_node srvc_odd_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc_2;
+static struct qcom_icc_node qns_gp_dsp_sail_noc;
+static struct qcom_icc_node qhs_lpass_core;
+static struct qcom_icc_node qhs_lpass_lpi;
+static struct qcom_icc_node qhs_lpass_mpu;
+static struct qcom_icc_node qhs_lpass_top;
+static struct qcom_icc_node qns_sysnoc;
+static struct qcom_icc_node srvc_niu_aml_noc;
+static struct qcom_icc_node srvc_niu_lpass_agnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc_hf;
+static struct qcom_icc_node srvc_mnoc_sf;
+static struct qcom_icc_node qns_hcp;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node service_nsp_noc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node srvc_snoc;
static struct qcom_icc_node qxm_qup3 = {
.name = "qxm_qup3",
- .id = QCS8300_MASTER_QUP_3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
- .id = QCS8300_MASTER_EMAC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = QCS8300_MASTER_SDC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = QCS8300_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb2_2 = {
.name = "xm_usb2_2",
- .id = QCS8300_MASTER_USB2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = QCS8300_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = QCS8300_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = QCS8300_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = QCS8300_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
- .id = QCS8300_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto_0 = {
.name = "qxm_crypto_0",
- .id = QCS8300_MASTER_CRYPTO_CORE0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto_1 = {
.name = "qxm_crypto_1",
- .id = QCS8300_MASTER_CRYPTO_CORE1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = QCS8300_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = QCS8300_MASTER_QDSS_ETR_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = QCS8300_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = QCS8300_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = QCS8300_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup3_core_master = {
.name = "qup3_core_master",
- .id = QCS8300_MASTER_QUP_CORE_3,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_QUP_CORE_3 },
+ .link_nodes = { &qup3_core_slave, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = QCS8300_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 71,
- .links = { QCS8300_SLAVE_AHB2PHY_2, QCS8300_SLAVE_AHB2PHY_3,
- QCS8300_SLAVE_ANOC_THROTTLE_CFG, QCS8300_SLAVE_AOSS,
- QCS8300_SLAVE_APPSS, QCS8300_SLAVE_BOOT_ROM,
- QCS8300_SLAVE_CAMERA_CFG, QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG, QCS8300_SLAVE_CLK_CTL,
- QCS8300_SLAVE_CDSP_CFG, QCS8300_SLAVE_RBCPR_CX_CFG,
- QCS8300_SLAVE_RBCPR_MMCX_CFG, QCS8300_SLAVE_RBCPR_MX_CFG,
- QCS8300_SLAVE_CPR_NSPCX, QCS8300_SLAVE_CPR_NSPHMX,
- QCS8300_SLAVE_CRYPTO_0_CFG, QCS8300_SLAVE_CX_RDPM,
- QCS8300_SLAVE_DISPLAY_CFG, QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG,
- QCS8300_SLAVE_EMAC_CFG, QCS8300_SLAVE_GP_DSP0_CFG,
- QCS8300_SLAVE_GPDSP0_THROTTLE_CFG, QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG,
- QCS8300_SLAVE_GFX3D_CFG, QCS8300_SLAVE_HWKM,
- QCS8300_SLAVE_IMEM_CFG, QCS8300_SLAVE_IPA_CFG,
- QCS8300_SLAVE_IPC_ROUTER_CFG, QCS8300_SLAVE_LPASS,
- QCS8300_SLAVE_LPASS_THROTTLE_CFG, QCS8300_SLAVE_MX_RDPM,
- QCS8300_SLAVE_MXC_RDPM, QCS8300_SLAVE_PCIE_0_CFG,
- QCS8300_SLAVE_PCIE_1_CFG, QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG,
- QCS8300_SLAVE_PCIE_THROTTLE_CFG, QCS8300_SLAVE_PDM,
- QCS8300_SLAVE_PIMEM_CFG, QCS8300_SLAVE_PKA_WRAPPER_CFG,
- QCS8300_SLAVE_QDSS_CFG, QCS8300_SLAVE_QM_CFG,
- QCS8300_SLAVE_QM_MPU_CFG, QCS8300_SLAVE_QUP_0,
- QCS8300_SLAVE_QUP_1, QCS8300_SLAVE_QUP_3,
- QCS8300_SLAVE_SAIL_THROTTLE_CFG, QCS8300_SLAVE_SDC1,
- QCS8300_SLAVE_SECURITY, QCS8300_SLAVE_SNOC_THROTTLE_CFG,
- QCS8300_SLAVE_TCSR, QCS8300_SLAVE_TLMM,
- QCS8300_SLAVE_TSC_CFG, QCS8300_SLAVE_UFS_MEM_CFG,
- QCS8300_SLAVE_USB2, QCS8300_SLAVE_USB3_0,
- QCS8300_SLAVE_VENUS_CFG, QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG,
- QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
- QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
- QCS8300_SLAVE_DDRSS_CFG, QCS8300_SLAVE_GPDSP_NOC_CFG,
- QCS8300_SLAVE_CNOC_MNOC_HF_CFG, QCS8300_SLAVE_CNOC_MNOC_SF_CFG,
- QCS8300_SLAVE_PCIE_ANOC_CFG, QCS8300_SLAVE_SNOC_CFG,
- QCS8300_SLAVE_BOOT_IMEM, QCS8300_SLAVE_IMEM,
- QCS8300_SLAVE_PIMEM, QCS8300_SLAVE_QDSS_STM,
- QCS8300_SLAVE_TCU },
+ .link_nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3,
+ &qhs_anoc_throttle_cfg, &qhs_aoss,
+ &qhs_apss, &qhs_boot_rom,
+ &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
+ &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
+ &qhs_compute0_cfg, &qhs_cpr_cx,
+ &qhs_cpr_mmcx, &qhs_cpr_mx,
+ &qhs_cpr_nspcx, &qhs_cpr_nsphmx,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
+ &qhs_emac0_cfg, &qhs_gp_dsp0_cfg,
+ &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg,
+ &qhs_gpuss_cfg, &qhs_hwkm,
+ &qhs_imem_cfg, &qhs_ipa,
+ &qhs_ipc_router, &qhs_lpass_cfg,
+ &qhs_lpass_throttle_cfg, &qhs_mx_rdpm,
+ &qhs_mxc_rdpm, &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg,
+ &qhs_pcie_throttle_cfg, &qhs_pdm,
+ &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
+ &qhs_qdss_cfg, &qhs_qm_cfg,
+ &qhs_qm_mpu_cfg, &qhs_qup0,
+ &qhs_qup1, &qhs_qup3,
+ &qhs_sail_throttle_cfg, &qhs_sdc1,
+ &qhs_security, &qhs_snoc_throttle_cfg,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_tsc_cfg, &qhs_ufs_mem_cfg,
+ &qhs_usb2_0, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_venus_cvp_throttle_cfg,
+ &qhs_venus_v_cpu_throttle_cfg,
+ &qhs_venus_vcodec_throttle_cfg,
+ &qns_ddrss_cfg, &qns_gpdsp_noc_cfg,
+ &qns_mnoc_hf_cfg, &qns_mnoc_sf_cfg,
+ &qns_pcie_anoc_cfg, &qns_snoc_cfg,
+ &qxs_boot_imem, &qxs_imem,
+ &qxs_pimem, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = QCS8300_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { QCS8300_SLAVE_PCIE_0, QCS8300_SLAVE_PCIE_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_node qnm_cnoc_dc_noc = {
.name = "qnm_cnoc_dc_noc",
- .id = QCS8300_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { QCS8300_SLAVE_LLCC_CFG, QCS8300_SLAVE_GEM_NOC_CFG },
+ .link_nodes = { &qhs_llcc, &qns_gemnoc, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = QCS8300_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_pcie_tcu = {
.name = "alm_pcie_tcu",
- .id = QCS8300_MASTER_PCIE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = QCS8300_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = QCS8300_MASTER_APPSS_PROC,
.channels = 4,
.buswidth = 32,
- .num_links = 3,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
- QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_cmpnoc0 = {
.name = "qnm_cmpnoc0",
- .id = QCS8300_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
- .id = QCS8300_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 4,
- .links = { QCS8300_SLAVE_SERVICE_GEM_NOC_1, QCS8300_SLAVE_SERVICE_GEM_NOC_2,
- QCS8300_SLAVE_SERVICE_GEM_NOC, QCS8300_SLAVE_SERVICE_GEM_NOC2 },
+ .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc,
+ &srvc_sys_gemnoc, &srvc_sys_gemnoc_2, NULL },
};
static struct qcom_icc_node qnm_gpdsp_sail = {
.name = "qnm_gpdsp_sail",
- .id = QCS8300_MASTER_GPDSP_SAIL,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = QCS8300_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = QCS8300_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { QCS8300_SLAVE_LLCC, QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
+ .link_nodes = { &qns_llcc, &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = QCS8300_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
- QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = QCS8300_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = QCS8300_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = QCS8300_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
- QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_sailss_md0 = {
.name = "qnm_sailss_md0",
- .id = QCS8300_MASTER_SAILSS_MD0,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_SLAVE_GP_DSP_SAIL_NOC },
+ .link_nodes = { &qns_gp_dsp_sail_noc, NULL },
};
static struct qcom_icc_node qxm_dsp0 = {
.name = "qxm_dsp0",
- .id = QCS8300_MASTER_DSP0,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_SLAVE_GP_DSP_SAIL_NOC },
+ .link_nodes = { &qns_gp_dsp_sail_noc, NULL },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
- .id = QCS8300_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 6,
- .links = { QCS8300_SLAVE_LPASS_CORE_CFG, QCS8300_SLAVE_LPASS_LPI_CFG,
- QCS8300_SLAVE_LPASS_MPU_CFG, QCS8300_SLAVE_LPASS_TOP_CFG,
- QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_NOC },
+ .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
+ &qhs_lpass_mpu, &qhs_lpass_top,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node qxm_lpass_dsp = {
.name = "qxm_lpass_dsp",
- .id = QCS8300_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 4,
- .links = { QCS8300_SLAVE_LPASS_TOP_CFG, QCS8300_SLAVE_LPASS_SNOC,
- QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_NOC },
+ .link_nodes = { &qhs_lpass_top, &qns_sysnoc,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = QCS8300_MASTER_LLCC,
.channels = 8,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = QCS8300_MASTER_CAMNOC_HF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = QCS8300_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = QCS8300_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_mdp0_0 = {
.name = "qnm_mdp0_0",
- .id = QCS8300_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mdp0_1 = {
.name = "qnm_mdp0_1",
- .id = QCS8300_MASTER_MDP1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf_cfg = {
.name = "qnm_mnoc_hf_cfg",
- .id = QCS8300_MASTER_CNOC_MNOC_HF_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SERVICE_MNOC_HF },
+ .link_nodes = { &srvc_mnoc_hf, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf_cfg = {
.name = "qnm_mnoc_sf_cfg",
- .id = QCS8300_MASTER_CNOC_MNOC_SF_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SERVICE_MNOC_SF },
+ .link_nodes = { &srvc_mnoc_sf, NULL },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
- .id = QCS8300_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = QCS8300_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = QCS8300_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
- .id = QCS8300_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SERVICE_NSP_NOC },
+ .link_nodes = { &service_nsp_noc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = QCS8300_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { QCS8300_SLAVE_HCP_A, QCS8300_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_hcp, &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = QCS8300_MASTER_PCIE_0,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = QCS8300_MASTER_PCIE_1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
- .id = QCS8300_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = QCS8300_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = QCS8300_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_lpass_noc = {
.name = "qnm_lpass_noc",
- .id = QCS8300_MASTER_LPASS_ANOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
- .id = QCS8300_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = QCS8300_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = QCS8300_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = QCS8300_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = QCS8300_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = QCS8300_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = QCS8300_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup3_core_slave = {
.name = "qup3_core_slave",
- .id = QCS8300_SLAVE_QUP_CORE_3,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy2 = {
.name = "qhs_ahb2phy2",
- .id = QCS8300_SLAVE_AHB2PHY_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy3 = {
.name = "qhs_ahb2phy3",
- .id = QCS8300_SLAVE_AHB2PHY_3,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_anoc_throttle_cfg = {
.name = "qhs_anoc_throttle_cfg",
- .id = QCS8300_SLAVE_ANOC_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = QCS8300_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = QCS8300_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_boot_rom = {
.name = "qhs_boot_rom",
- .id = QCS8300_SLAVE_BOOT_ROM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = QCS8300_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
.name = "qhs_camera_nrt_throttle_cfg",
- .id = QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
.name = "qhs_camera_rt_throttle_cfg",
- .id = QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = QCS8300_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute0_cfg = {
.name = "qhs_compute0_cfg",
- .id = QCS8300_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_MASTER_CDSP_NOC_CFG },
+ .link_nodes = { &qhm_nsp_noc_config, NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = QCS8300_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = QCS8300_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = QCS8300_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_nspcx = {
.name = "qhs_cpr_nspcx",
- .id = QCS8300_SLAVE_CPR_NSPCX,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_nsphmx = {
.name = "qhs_cpr_nsphmx",
- .id = QCS8300_SLAVE_CPR_NSPHMX,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = QCS8300_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = QCS8300_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display0_cfg = {
.name = "qhs_display0_cfg",
- .id = QCS8300_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
.name = "qhs_display0_rt_throttle_cfg",
- .id = QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emac0_cfg = {
.name = "qhs_emac0_cfg",
- .id = QCS8300_SLAVE_EMAC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gp_dsp0_cfg = {
.name = "qhs_gp_dsp0_cfg",
- .id = QCS8300_SLAVE_GP_DSP0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
.name = "qhs_gpdsp0_throttle_cfg",
- .id = QCS8300_SLAVE_GPDSP0_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
.name = "qhs_gpu_tcu_throttle_cfg",
- .id = QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = QCS8300_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_hwkm = {
.name = "qhs_hwkm",
- .id = QCS8300_SLAVE_HWKM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = QCS8300_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = QCS8300_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = QCS8300_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = QCS8300_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_MASTER_CNOC_LPASS_AG_NOC },
+ .link_nodes = { &qhm_config_noc, NULL },
};
static struct qcom_icc_node qhs_lpass_throttle_cfg = {
.name = "qhs_lpass_throttle_cfg",
- .id = QCS8300_SLAVE_LPASS_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = QCS8300_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mxc_rdpm = {
.name = "qhs_mxc_rdpm",
- .id = QCS8300_SLAVE_MXC_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = QCS8300_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = QCS8300_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
.name = "qhs_pcie_tcu_throttle_cfg",
- .id = QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_throttle_cfg = {
.name = "qhs_pcie_throttle_cfg",
- .id = QCS8300_SLAVE_PCIE_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = QCS8300_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = QCS8300_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pke_wrapper_cfg = {
.name = "qhs_pke_wrapper_cfg",
- .id = QCS8300_SLAVE_PKA_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = QCS8300_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qm_cfg = {
.name = "qhs_qm_cfg",
- .id = QCS8300_SLAVE_QM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qm_mpu_cfg = {
.name = "qhs_qm_mpu_cfg",
- .id = QCS8300_SLAVE_QM_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = QCS8300_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = QCS8300_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup3 = {
.name = "qhs_qup3",
- .id = QCS8300_SLAVE_QUP_3,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sail_throttle_cfg = {
.name = "qhs_sail_throttle_cfg",
- .id = QCS8300_SLAVE_SAIL_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = QCS8300_SLAVE_SDC1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
- .id = QCS8300_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_throttle_cfg = {
.name = "qhs_snoc_throttle_cfg",
- .id = QCS8300_SLAVE_SNOC_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = QCS8300_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = QCS8300_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tsc_cfg = {
.name = "qhs_tsc_cfg",
- .id = QCS8300_SLAVE_TSC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = QCS8300_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb2_0 = {
.name = "qhs_usb2_0",
- .id = QCS8300_SLAVE_USB2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = QCS8300_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = QCS8300_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
.name = "qhs_venus_cvp_throttle_cfg",
- .id = QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
.name = "qhs_venus_v_cpu_throttle_cfg",
- .id = QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
.name = "qhs_venus_vcodec_throttle_cfg",
- .id = QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = QCS8300_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qnm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qns_gpdsp_noc_cfg = {
.name = "qns_gpdsp_noc_cfg",
- .id = QCS8300_SLAVE_GPDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mnoc_hf_cfg = {
.name = "qns_mnoc_hf_cfg",
- .id = QCS8300_SLAVE_CNOC_MNOC_HF_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_MASTER_CNOC_MNOC_HF_CFG },
+ .link_nodes = { &qnm_mnoc_hf_cfg, NULL },
};
static struct qcom_icc_node qns_mnoc_sf_cfg = {
.name = "qns_mnoc_sf_cfg",
- .id = QCS8300_SLAVE_CNOC_MNOC_SF_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_MASTER_CNOC_MNOC_SF_CFG },
+ .link_nodes = { &qnm_mnoc_sf_cfg, NULL },
};
static struct qcom_icc_node qns_pcie_anoc_cfg = {
.name = "qns_pcie_anoc_cfg",
- .id = QCS8300_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
- .id = QCS8300_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_MASTER_SNOC_CFG },
+ .link_nodes = { &qnm_snoc_cfg, NULL },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = QCS8300_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = QCS8300_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = QCS8300_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = QCS8300_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = QCS8300_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 32,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = QCS8300_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = QCS8300_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = QCS8300_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
- .id = QCS8300_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QCS8300_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qnm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = QCS8300_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = QCS8300_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = QCS8300_SLAVE_GEM_NOC_PCIE_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
- .id = QCS8300_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
- .id = QCS8300_SLAVE_SERVICE_GEM_NOC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
- .id = QCS8300_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_sys_gemnoc_2 = {
.name = "srvc_sys_gemnoc_2",
- .id = QCS8300_SLAVE_SERVICE_GEM_NOC2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gp_dsp_sail_noc = {
.name = "qns_gp_dsp_sail_noc",
- .id = QCS8300_SLAVE_GP_DSP_SAIL_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_MASTER_GPDSP_SAIL },
+ .link_nodes = { &qnm_gpdsp_sail, NULL },
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
- .id = QCS8300_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
- .id = QCS8300_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
- .id = QCS8300_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
- .id = QCS8300_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_sysnoc = {
.name = "qns_sysnoc",
- .id = QCS8300_SLAVE_LPASS_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_MASTER_LPASS_ANOC },
+ .link_nodes = { &qnm_lpass_noc, NULL },
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
- .id = QCS8300_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
- .id = QCS8300_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = QCS8300_SLAVE_EBI1,
.channels = 8,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = QCS8300_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = QCS8300_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc_hf = {
.name = "srvc_mnoc_hf",
- .id = QCS8300_SLAVE_SERVICE_MNOC_HF,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_mnoc_sf = {
.name = "srvc_mnoc_sf",
- .id = QCS8300_SLAVE_SERVICE_MNOC_SF,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_hcp = {
.name = "qns_hcp",
- .id = QCS8300_SLAVE_HCP_A,
.channels = 2,
.buswidth = 32,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = QCS8300_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc0, NULL },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
- .id = QCS8300_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = QCS8300_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { QCS8300_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = QCS8300_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QCS8300_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = QCS8300_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QCS8300_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = QCS8300_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1662,6 +1582,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1687,6 +1608,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1709,6 +1631,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1803,6 +1726,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1816,6 +1740,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@@ -1849,6 +1774,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1866,6 +1792,7 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_gpdsp_anoc = {
+ .alloc_dyn_id = true,
.nodes = gpdsp_anoc_nodes,
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
.bcms = gpdsp_anoc_bcms,
@@ -1889,6 +1816,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1906,6 +1834,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1935,6 +1864,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1955,6 +1885,7 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_nspa_noc = {
+ .alloc_dyn_id = true,
.nodes = nspa_noc_nodes,
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
@@ -1972,6 +1903,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_pcie_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -2000,6 +1932,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/qcs8300.h b/drivers/interconnect/qcom/qcs8300.h
deleted file mode 100644
index 6b9e2b424c2ad0401f72d5fb8cfb7e0f48a1db85..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/qcs8300.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS8300_H
-#define __DRIVERS_INTERCONNECT_QCOM_QCS8300_H
-
-#define QCS8300_MASTER_GPU_TCU 0
-#define QCS8300_MASTER_PCIE_TCU 1
-#define QCS8300_MASTER_SYS_TCU 2
-#define QCS8300_MASTER_APPSS_PROC 3
-#define QCS8300_MASTER_LLCC 4
-#define QCS8300_MASTER_CNOC_LPASS_AG_NOC 5
-#define QCS8300_MASTER_GIC_AHB 6
-#define QCS8300_MASTER_CDSP_NOC_CFG 7
-#define QCS8300_MASTER_QDSS_BAM 8
-#define QCS8300_MASTER_QUP_0 9
-#define QCS8300_MASTER_QUP_1 10
-#define QCS8300_MASTER_A1NOC_SNOC 11
-#define QCS8300_MASTER_A2NOC_SNOC 12
-#define QCS8300_MASTER_CAMNOC_HF 13
-#define QCS8300_MASTER_CAMNOC_ICP 14
-#define QCS8300_MASTER_CAMNOC_SF 15
-#define QCS8300_MASTER_COMPUTE_NOC 16
-#define QCS8300_MASTER_CNOC_A2NOC 17
-#define QCS8300_MASTER_CNOC_DC_NOC 18
-#define QCS8300_MASTER_GEM_NOC_CFG 19
-#define QCS8300_MASTER_GEM_NOC_CNOC 20
-#define QCS8300_MASTER_GEM_NOC_PCIE_SNOC 21
-#define QCS8300_MASTER_GPDSP_SAIL 22
-#define QCS8300_MASTER_GFX3D 23
-#define QCS8300_MASTER_LPASS_ANOC 24
-#define QCS8300_MASTER_MDP0 25
-#define QCS8300_MASTER_MDP1 26
-#define QCS8300_MASTER_MNOC_HF_MEM_NOC 27
-#define QCS8300_MASTER_CNOC_MNOC_HF_CFG 28
-#define QCS8300_MASTER_MNOC_SF_MEM_NOC 29
-#define QCS8300_MASTER_CNOC_MNOC_SF_CFG 30
-#define QCS8300_MASTER_ANOC_PCIE_GEM_NOC 31
-#define QCS8300_MASTER_SAILSS_MD0 32
-#define QCS8300_MASTER_SNOC_CFG 33
-#define QCS8300_MASTER_SNOC_GC_MEM_NOC 34
-#define QCS8300_MASTER_SNOC_SF_MEM_NOC 35
-#define QCS8300_MASTER_VIDEO_P0 36
-#define QCS8300_MASTER_VIDEO_PROC 37
-#define QCS8300_MASTER_VIDEO_V_PROC 38
-#define QCS8300_MASTER_QUP_CORE_0 39
-#define QCS8300_MASTER_QUP_CORE_1 40
-#define QCS8300_MASTER_QUP_CORE_3 41
-#define QCS8300_MASTER_CRYPTO_CORE0 42
-#define QCS8300_MASTER_CRYPTO_CORE1 43
-#define QCS8300_MASTER_DSP0 44
-#define QCS8300_MASTER_IPA 45
-#define QCS8300_MASTER_LPASS_PROC 46
-#define QCS8300_MASTER_CDSP_PROC 47
-#define QCS8300_MASTER_PIMEM 48
-#define QCS8300_MASTER_QUP_3 49
-#define QCS8300_MASTER_EMAC 50
-#define QCS8300_MASTER_GIC 51
-#define QCS8300_MASTER_PCIE_0 52
-#define QCS8300_MASTER_PCIE_1 53
-#define QCS8300_MASTER_QDSS_ETR_0 54
-#define QCS8300_MASTER_QDSS_ETR_1 55
-#define QCS8300_MASTER_SDC 56
-#define QCS8300_MASTER_UFS_MEM 57
-#define QCS8300_MASTER_USB2 58
-#define QCS8300_MASTER_USB3_0 59
-#define QCS8300_SLAVE_EBI1 60
-#define QCS8300_SLAVE_AHB2PHY_2 61
-#define QCS8300_SLAVE_AHB2PHY_3 62
-#define QCS8300_SLAVE_ANOC_THROTTLE_CFG 63
-#define QCS8300_SLAVE_AOSS 64
-#define QCS8300_SLAVE_APPSS 65
-#define QCS8300_SLAVE_BOOT_ROM 66
-#define QCS8300_SLAVE_CAMERA_CFG 67
-#define QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG 68
-#define QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG 69
-#define QCS8300_SLAVE_CLK_CTL 70
-#define QCS8300_SLAVE_CDSP_CFG 71
-#define QCS8300_SLAVE_RBCPR_CX_CFG 72
-#define QCS8300_SLAVE_RBCPR_MMCX_CFG 73
-#define QCS8300_SLAVE_RBCPR_MX_CFG 74
-#define QCS8300_SLAVE_CPR_NSPCX 75
-#define QCS8300_SLAVE_CPR_NSPHMX 76
-#define QCS8300_SLAVE_CRYPTO_0_CFG 77
-#define QCS8300_SLAVE_CX_RDPM 78
-#define QCS8300_SLAVE_DISPLAY_CFG 79
-#define QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG 80
-#define QCS8300_SLAVE_EMAC_CFG 81
-#define QCS8300_SLAVE_GP_DSP0_CFG 82
-#define QCS8300_SLAVE_GPDSP0_THROTTLE_CFG 83
-#define QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG 84
-#define QCS8300_SLAVE_GFX3D_CFG 85
-#define QCS8300_SLAVE_HWKM 86
-#define QCS8300_SLAVE_IMEM_CFG 87
-#define QCS8300_SLAVE_IPA_CFG 88
-#define QCS8300_SLAVE_IPC_ROUTER_CFG 89
-#define QCS8300_SLAVE_LLCC_CFG 90
-#define QCS8300_SLAVE_LPASS 91
-#define QCS8300_SLAVE_LPASS_CORE_CFG 92
-#define QCS8300_SLAVE_LPASS_LPI_CFG 93
-#define QCS8300_SLAVE_LPASS_MPU_CFG 94
-#define QCS8300_SLAVE_LPASS_THROTTLE_CFG 95
-#define QCS8300_SLAVE_LPASS_TOP_CFG 96
-#define QCS8300_SLAVE_MX_RDPM 97
-#define QCS8300_SLAVE_MXC_RDPM 98
-#define QCS8300_SLAVE_PCIE_0_CFG 99
-#define QCS8300_SLAVE_PCIE_1_CFG 100
-#define QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG 101
-#define QCS8300_SLAVE_PCIE_THROTTLE_CFG 102
-#define QCS8300_SLAVE_PDM 103
-#define QCS8300_SLAVE_PIMEM_CFG 104
-#define QCS8300_SLAVE_PKA_WRAPPER_CFG 105
-#define QCS8300_SLAVE_QDSS_CFG 106
-#define QCS8300_SLAVE_QM_CFG 107
-#define QCS8300_SLAVE_QM_MPU_CFG 108
-#define QCS8300_SLAVE_QUP_0 109
-#define QCS8300_SLAVE_QUP_1 110
-#define QCS8300_SLAVE_QUP_3 111
-#define QCS8300_SLAVE_SAIL_THROTTLE_CFG 112
-#define QCS8300_SLAVE_SDC1 113
-#define QCS8300_SLAVE_SECURITY 114
-#define QCS8300_SLAVE_SNOC_THROTTLE_CFG 115
-#define QCS8300_SLAVE_TCSR 116
-#define QCS8300_SLAVE_TLMM 117
-#define QCS8300_SLAVE_TSC_CFG 118
-#define QCS8300_SLAVE_UFS_MEM_CFG 119
-#define QCS8300_SLAVE_USB2 120
-#define QCS8300_SLAVE_USB3_0 121
-#define QCS8300_SLAVE_VENUS_CFG 122
-#define QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG 123
-#define QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG 124
-#define QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG 125
-#define QCS8300_SLAVE_A1NOC_SNOC 126
-#define QCS8300_SLAVE_A2NOC_SNOC 127
-#define QCS8300_SLAVE_DDRSS_CFG 128
-#define QCS8300_SLAVE_GEM_NOC_CNOC 129
-#define QCS8300_SLAVE_GEM_NOC_CFG 130
-#define QCS8300_SLAVE_SNOC_GEM_NOC_GC 131
-#define QCS8300_SLAVE_SNOC_GEM_NOC_SF 132
-#define QCS8300_SLAVE_GP_DSP_SAIL_NOC 133
-#define QCS8300_SLAVE_GPDSP_NOC_CFG 134
-#define QCS8300_SLAVE_HCP_A 135
-#define QCS8300_SLAVE_LLCC 136
-#define QCS8300_SLAVE_MNOC_HF_MEM_NOC 137
-#define QCS8300_SLAVE_MNOC_SF_MEM_NOC 138
-#define QCS8300_SLAVE_CNOC_MNOC_HF_CFG 139
-#define QCS8300_SLAVE_CNOC_MNOC_SF_CFG 140
-#define QCS8300_SLAVE_CDSP_MEM_NOC 141
-#define QCS8300_SLAVE_GEM_NOC_PCIE_CNOC 142
-#define QCS8300_SLAVE_PCIE_ANOC_CFG 143
-#define QCS8300_SLAVE_ANOC_PCIE_GEM_NOC 144
-#define QCS8300_SLAVE_SNOC_CFG 145
-#define QCS8300_SLAVE_LPASS_SNOC 146
-#define QCS8300_SLAVE_QUP_CORE_0 147
-#define QCS8300_SLAVE_QUP_CORE_1 148
-#define QCS8300_SLAVE_QUP_CORE_3 149
-#define QCS8300_SLAVE_BOOT_IMEM 150
-#define QCS8300_SLAVE_IMEM 151
-#define QCS8300_SLAVE_PIMEM 152
-#define QCS8300_SLAVE_SERVICE_NSP_NOC 153
-#define QCS8300_SLAVE_SERVICE_GEM_NOC_1 154
-#define QCS8300_SLAVE_SERVICE_MNOC_HF 155
-#define QCS8300_SLAVE_SERVICE_MNOC_SF 156
-#define QCS8300_SLAVE_SERVICES_LPASS_AML_NOC 157
-#define QCS8300_SLAVE_SERVICE_LPASS_AG_NOC 158
-#define QCS8300_SLAVE_SERVICE_GEM_NOC_2 159
-#define QCS8300_SLAVE_SERVICE_SNOC 160
-#define QCS8300_SLAVE_SERVICE_GEM_NOC 161
-#define QCS8300_SLAVE_SERVICE_GEM_NOC2 162
-#define QCS8300_SLAVE_PCIE_0 163
-#define QCS8300_SLAVE_PCIE_1 164
-#define QCS8300_SLAVE_QDSS_STM 165
-#define QCS8300_SLAVE_TCU 166
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 13/28] interconnect: qcom: qdu1000: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (11 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 12/28] interconnect: qcom: qcs8300: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 14/28] interconnect: qcom: sar2130p: " Dmitry Baryshkov
` (15 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/qdu1000.c | 437 ++++++++++++++++--------------------
drivers/interconnect/qcom/qdu1000.h | 95 --------
2 files changed, 196 insertions(+), 336 deletions(-)
diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c
index 727482c0f7f8f15e32cf508a5f7300546e9d2daf..6bd7b16f8129758eca38ed9d348ac745226897dd 100644
--- a/drivers/interconnect/qcom/qdu1000.c
+++ b/drivers/interconnect/qcom/qdu1000.c
@@ -15,756 +15,707 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
-#include "qdu1000.h"
+
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_ecpri_dma;
+static struct qcom_icc_node qnm_fec_2_gemnoc;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_mdsp;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qhm_gic;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qpic;
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qhm_system_noc_cfg;
+static struct qcom_icc_node qnm_aggre_noc;
+static struct qcom_icc_node qnm_aggre_noc_gsi;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_modem_slave;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ecpri_gsi;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_ecpri_dma;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node xm_pcie;
+static struct qcom_icc_node xm_qdss_etr0;
+static struct qcom_icc_node xm_qdss_etr1;
+static struct qcom_icc_node xm_sdc;
+static struct qcom_icc_node xm_usb3;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_modem_slave;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qhs_ahb2phy0_south;
+static struct qcom_icc_node qhs_ahb2phy1_north;
+static struct qcom_icc_node qhs_ahb2phy2_east;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto_cfg;
+static struct qcom_icc_node qhs_ecpri_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_pcie_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qpic;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_smbus_cfg;
+static struct qcom_icc_node qhs_system_noc_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_tme_cfg;
+static struct qcom_icc_node qhs_tsc_cfg;
+static struct qcom_icc_node qhs_usb3;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_anoc_snoc_gsi;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qns_ecpri_gemnoc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qns_modem;
+static struct qcom_icc_node qns_pcie_gemnoc;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_system_noc;
+static struct qcom_icc_node xs_ethernet_ss;
+static struct qcom_icc_node xs_pcie;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = QDU1000_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = QDU1000_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = QDU1000_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = QDU1000_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 4,
- .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
- QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_modem_slave, &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_ecpri_dma = {
.name = "qnm_ecpri_dma",
- .id = QDU1000_MASTER_GEMNOC_ECPRI_DMA,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_fec_2_gemnoc = {
.name = "qnm_fec_2_gemnoc",
- .id = QDU1000_MASTER_FEC_2_GEMNOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = QDU1000_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 64,
- .num_links = 3,
- .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
- QDU1000_SLAVE_GEMNOC_MODEM_CNOC
- },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_modem_slave, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = QDU1000_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = QDU1000_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 4,
- .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
- QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_modem_slave, &qns_pcie, NULL },
};
static struct qcom_icc_node qxm_mdsp = {
.name = "qxm_mdsp",
- .id = QDU1000_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
- QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = QDU1000_MASTER_LLCC,
.channels = 8,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
- .id = QDU1000_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = QDU1000_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
- .id = QDU1000_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = QDU1000_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = QDU1000_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = QDU1000_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_system_noc_cfg = {
.name = "qhm_system_noc_cfg",
- .id = QDU1000_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_system_noc, NULL },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
- .id = QDU1000_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre_noc_gsi = {
.name = "qnm_aggre_noc_gsi",
- .id = QDU1000_MASTER_ANOC_GSI,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = QDU1000_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 36,
- .links = { QDU1000_SLAVE_AHB2PHY_SOUTH, QDU1000_SLAVE_AHB2PHY_NORTH,
- QDU1000_SLAVE_AHB2PHY_EAST, QDU1000_SLAVE_AOSS,
- QDU1000_SLAVE_CLK_CTL, QDU1000_SLAVE_RBCPR_CX_CFG,
- QDU1000_SLAVE_RBCPR_MX_CFG, QDU1000_SLAVE_CRYPTO_0_CFG,
- QDU1000_SLAVE_ECPRI_CFG, QDU1000_SLAVE_IMEM_CFG,
- QDU1000_SLAVE_IPC_ROUTER_CFG, QDU1000_SLAVE_CNOC_MSS,
- QDU1000_SLAVE_PCIE_CFG, QDU1000_SLAVE_PDM,
- QDU1000_SLAVE_PIMEM_CFG, QDU1000_SLAVE_PRNG,
- QDU1000_SLAVE_QDSS_CFG, QDU1000_SLAVE_QPIC,
- QDU1000_SLAVE_QSPI_0, QDU1000_SLAVE_QUP_0,
- QDU1000_SLAVE_QUP_1, QDU1000_SLAVE_SDCC_2,
- QDU1000_SLAVE_SMBUS_CFG, QDU1000_SLAVE_SNOC_CFG,
- QDU1000_SLAVE_TCSR, QDU1000_SLAVE_TLMM,
- QDU1000_SLAVE_TME_CFG, QDU1000_SLAVE_TSC_CFG,
- QDU1000_SLAVE_USB3_0, QDU1000_SLAVE_VSENSE_CTRL_CFG,
- QDU1000_SLAVE_DDRSS_CFG, QDU1000_SLAVE_IMEM,
- QDU1000_SLAVE_PIMEM, QDU1000_SLAVE_ETHERNET_SS,
- QDU1000_SLAVE_QDSS_STM, QDU1000_SLAVE_TCU
- },
+ .link_nodes = { &qhs_ahb2phy0_south, &qhs_ahb2phy1_north,
+ &qhs_ahb2phy2_east, &qhs_aoss,
+ &qhs_clk_ctl, &qhs_cpr_cx,
+ &qhs_cpr_mx, &qhs_crypto_cfg,
+ &qhs_ecpri_cfg, &qhs_imem_cfg,
+ &qhs_ipc_router, &qhs_mss_cfg,
+ &qhs_pcie_cfg, &qhs_pdm,
+ &qhs_pimem_cfg, &qhs_prng,
+ &qhs_qdss_cfg, &qhs_qpic,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc2,
+ &qhs_smbus_cfg, &qhs_system_noc_cfg,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_tme_cfg, &qhs_tsc_cfg,
+ &qhs_usb3, &qhs_vsense_ctrl_cfg,
+ &qns_ddrss_cfg, &qxs_imem,
+ &qxs_pimem, &xs_ethernet_ss,
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_modem_slave = {
.name = "qnm_gemnoc_modem_slave",
- .id = QDU1000_MASTER_GEMNOC_MODEM_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QDU1000_SLAVE_MODEM_OFFLINE },
+ .link_nodes = { &qns_modem, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = QDU1000_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QDU1000_SLAVE_PCIE_0 },
+ .link_nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = QDU1000_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ecpri_gsi = {
.name = "qxm_ecpri_gsi",
- .id = QDU1000_MASTER_ECPRI_GSI,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { QDU1000_SLAVE_ANOC_SNOC_GSI, QDU1000_SLAVE_PCIE_0 },
+ .link_nodes = { &qns_anoc_snoc_gsi, &xs_pcie, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = QDU1000_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_ecpri_dma = {
.name = "xm_ecpri_dma",
- .id = QDU1000_MASTER_SNOC_ECPRI_DMA,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { QDU1000_SLAVE_ECPRI_GEMNOC, QDU1000_SLAVE_PCIE_0 },
+ .link_nodes = { &qns_ecpri_gemnoc, &xs_pcie, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = QDU1000_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
- .id = QDU1000_MASTER_PCIE,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { QDU1000_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gemnoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr0 = {
.name = "xm_qdss_etr0",
- .id = QDU1000_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node xm_qdss_etr1 = {
.name = "xm_qdss_etr1",
- .id = QDU1000_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node xm_sdc = {
.name = "xm_sdc",
- .id = QDU1000_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
- .id = QDU1000_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = QDU1000_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = QDU1000_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = QDU1000_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QDU1000_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = QDU1000_SLAVE_LLCC,
.channels = 8,
.buswidth = 16,
- .num_links = 1,
- .links = { QDU1000_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_modem_slave = {
.name = "qns_modem_slave",
- .id = QDU1000_SLAVE_GEMNOC_MODEM_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QDU1000_MASTER_GEMNOC_MODEM_CNOC },
+ .link_nodes = { &qnm_gemnoc_modem_slave, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = QDU1000_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QDU1000_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = QDU1000_SLAVE_EBI1,
.channels = 8,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0_south = {
.name = "qhs_ahb2phy0_south",
- .id = QDU1000_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1_north = {
.name = "qhs_ahb2phy1_north",
- .id = QDU1000_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy2_east = {
.name = "qhs_ahb2phy2_east",
- .id = QDU1000_SLAVE_AHB2PHY_EAST,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = QDU1000_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = QDU1000_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = QDU1000_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = QDU1000_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto_cfg = {
.name = "qhs_crypto_cfg",
- .id = QDU1000_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ecpri_cfg = {
.name = "qhs_ecpri_cfg",
- .id = QDU1000_SLAVE_ECPRI_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = QDU1000_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = QDU1000_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = QDU1000_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_cfg = {
.name = "qhs_pcie_cfg",
- .id = QDU1000_SLAVE_PCIE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = QDU1000_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = QDU1000_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = QDU1000_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = QDU1000_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
- .id = QDU1000_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = QDU1000_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = QDU1000_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = QDU1000_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = QDU1000_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_smbus_cfg = {
.name = "qhs_smbus_cfg",
- .id = QDU1000_SLAVE_SMBUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_system_noc_cfg = {
.name = "qhs_system_noc_cfg",
- .id = QDU1000_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { QDU1000_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_system_noc_cfg, NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = QDU1000_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = QDU1000_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
- .id = QDU1000_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tsc_cfg = {
.name = "qhs_tsc_cfg",
- .id = QDU1000_SLAVE_TSC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
- .id = QDU1000_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = QDU1000_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = QDU1000_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_MASTER_ANOC_SNOC },
+ .link_nodes = { &qnm_aggre_noc, NULL },
};
static struct qcom_icc_node qns_anoc_snoc_gsi = {
.name = "qns_anoc_snoc_gsi",
- .id = QDU1000_SLAVE_ANOC_SNOC_GSI,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_MASTER_ANOC_GSI },
+ .link_nodes = { &qnm_aggre_noc_gsi, NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = QDU1000_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_ecpri_gemnoc = {
.name = "qns_ecpri_gemnoc",
- .id = QDU1000_SLAVE_ECPRI_GEMNOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { QDU1000_MASTER_GEMNOC_ECPRI_DMA },
+ .link_nodes = { &qnm_ecpri_dma, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = QDU1000_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { QDU1000_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = QDU1000_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { QDU1000_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qns_modem = {
.name = "qns_modem",
- .id = QDU1000_SLAVE_MODEM_OFFLINE,
.channels = 1,
.buswidth = 32,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_pcie_gemnoc = {
.name = "qns_pcie_gemnoc",
- .id = QDU1000_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 64,
- .num_links = 1,
- .links = { QDU1000_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = QDU1000_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = QDU1000_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_system_noc = {
.name = "srvc_system_noc",
- .id = QDU1000_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_ethernet_ss = {
.name = "xs_ethernet_ss",
- .id = QDU1000_SLAVE_ETHERNET_SS,
.channels = 1,
.buswidth = 32,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
- .id = QDU1000_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 64,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = QDU1000_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = QDU1000_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -865,6 +816,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc qdu1000_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -892,6 +844,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc qdu1000_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -909,6 +862,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc qdu1000_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -995,6 +949,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc qdu1000_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/qdu1000.h b/drivers/interconnect/qcom/qdu1000.h
deleted file mode 100644
index e75a6419df235353a5dcfbefe1cb3979ae966054..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/qdu1000.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_QDU1000_H
-#define __DRIVERS_INTERCONNECT_QCOM_QDU1000_H
-
-#define QDU1000_MASTER_SYS_TCU 0
-#define QDU1000_MASTER_APPSS_PROC 1
-#define QDU1000_MASTER_LLCC 2
-#define QDU1000_MASTER_GIC_AHB 3
-#define QDU1000_MASTER_QDSS_BAM 4
-#define QDU1000_MASTER_QPIC 5
-#define QDU1000_MASTER_QSPI_0 6
-#define QDU1000_MASTER_QUP_0 7
-#define QDU1000_MASTER_QUP_1 8
-#define QDU1000_MASTER_SNOC_CFG 9
-#define QDU1000_MASTER_ANOC_SNOC 10
-#define QDU1000_MASTER_ANOC_GSI 11
-#define QDU1000_MASTER_GEMNOC_ECPRI_DMA 12
-#define QDU1000_MASTER_FEC_2_GEMNOC 13
-#define QDU1000_MASTER_GEM_NOC_CNOC 14
-#define QDU1000_MASTER_GEMNOC_MODEM_CNOC 15
-#define QDU1000_MASTER_GEM_NOC_PCIE_SNOC 16
-#define QDU1000_MASTER_ANOC_PCIE_GEM_NOC 17
-#define QDU1000_MASTER_SNOC_GC_MEM_NOC 18
-#define QDU1000_MASTER_SNOC_SF_MEM_NOC 19
-#define QDU1000_MASTER_QUP_CORE_0 20
-#define QDU1000_MASTER_QUP_CORE_1 21
-#define QDU1000_MASTER_CRYPTO 22
-#define QDU1000_MASTER_ECPRI_GSI 23
-#define QDU1000_MASTER_MSS_PROC 24
-#define QDU1000_MASTER_PIMEM 25
-#define QDU1000_MASTER_SNOC_ECPRI_DMA 26
-#define QDU1000_MASTER_GIC 27
-#define QDU1000_MASTER_PCIE 28
-#define QDU1000_MASTER_QDSS_ETR 29
-#define QDU1000_MASTER_QDSS_ETR_1 30
-#define QDU1000_MASTER_SDCC_1 31
-#define QDU1000_MASTER_USB3 32
-#define QDU1000_SLAVE_EBI1 512
-#define QDU1000_SLAVE_AHB2PHY_SOUTH 513
-#define QDU1000_SLAVE_AHB2PHY_NORTH 514
-#define QDU1000_SLAVE_AHB2PHY_EAST 515
-#define QDU1000_SLAVE_AOSS 516
-#define QDU1000_SLAVE_CLK_CTL 517
-#define QDU1000_SLAVE_RBCPR_CX_CFG 518
-#define QDU1000_SLAVE_RBCPR_MX_CFG 519
-#define QDU1000_SLAVE_CRYPTO_0_CFG 520
-#define QDU1000_SLAVE_ECPRI_CFG 521
-#define QDU1000_SLAVE_IMEM_CFG 522
-#define QDU1000_SLAVE_IPC_ROUTER_CFG 523
-#define QDU1000_SLAVE_CNOC_MSS 524
-#define QDU1000_SLAVE_PCIE_CFG 525
-#define QDU1000_SLAVE_PDM 526
-#define QDU1000_SLAVE_PIMEM_CFG 527
-#define QDU1000_SLAVE_PRNG 528
-#define QDU1000_SLAVE_QDSS_CFG 529
-#define QDU1000_SLAVE_QPIC 530
-#define QDU1000_SLAVE_QSPI_0 531
-#define QDU1000_SLAVE_QUP_0 532
-#define QDU1000_SLAVE_QUP_1 533
-#define QDU1000_SLAVE_SDCC_2 534
-#define QDU1000_SLAVE_SMBUS_CFG 535
-#define QDU1000_SLAVE_SNOC_CFG 536
-#define QDU1000_SLAVE_TCSR 537
-#define QDU1000_SLAVE_TLMM 538
-#define QDU1000_SLAVE_TME_CFG 539
-#define QDU1000_SLAVE_TSC_CFG 540
-#define QDU1000_SLAVE_USB3_0 541
-#define QDU1000_SLAVE_VSENSE_CTRL_CFG 542
-#define QDU1000_SLAVE_A1NOC_SNOC 543
-#define QDU1000_SLAVE_ANOC_SNOC_GSI 544
-#define QDU1000_SLAVE_DDRSS_CFG 545
-#define QDU1000_SLAVE_ECPRI_GEMNOC 546
-#define QDU1000_SLAVE_GEM_NOC_CNOC 547
-#define QDU1000_SLAVE_SNOC_GEM_NOC_GC 548
-#define QDU1000_SLAVE_SNOC_GEM_NOC_SF 549
-#define QDU1000_SLAVE_LLCC 550
-#define QDU1000_SLAVE_MODEM_OFFLINE 551
-#define QDU1000_SLAVE_GEMNOC_MODEM_CNOC 552
-#define QDU1000_SLAVE_MEM_NOC_PCIE_SNOC 553
-#define QDU1000_SLAVE_ANOC_PCIE_GEM_NOC 554
-#define QDU1000_SLAVE_QUP_CORE_0 555
-#define QDU1000_SLAVE_QUP_CORE_1 556
-#define QDU1000_SLAVE_IMEM 557
-#define QDU1000_SLAVE_PIMEM 558
-#define QDU1000_SLAVE_SERVICE_SNOC 559
-#define QDU1000_SLAVE_ETHERNET_SS 560
-#define QDU1000_SLAVE_PCIE_0 561
-#define QDU1000_SLAVE_QDSS_STM 562
-#define QDU1000_SLAVE_TCU 563
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 14/28] interconnect: qcom: sar2130p: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (12 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 13/28] interconnect: qcom: qdu1000: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 15/28] interconnect: qcom: sc7180: " Dmitry Baryshkov
` (14 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sar2130p.c | 756 ++++++++++++++---------------------
1 file changed, 291 insertions(+), 465 deletions(-)
diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qcom/sar2130p.c
index cae3601b6789ff38e7bd88c60c4c8dd8d00e8850..df9bd10ffe0589f135a0c6199162b7f33233598f 100644
--- a/drivers/interconnect/qcom/sar2130p.c
+++ b/drivers/interconnect/qcom/sar2130p.c
@@ -20,125 +20,123 @@
#include "icc-common.h"
#include "icc-rpmh.h"
-enum {
- SAR2130P_MASTER_QUP_CORE_0,
- SAR2130P_MASTER_QUP_CORE_1,
- SAR2130P_MASTER_GEM_NOC_CNOC,
- SAR2130P_MASTER_GEM_NOC_PCIE_SNOC,
- SAR2130P_MASTER_QDSS_DAP,
- SAR2130P_MASTER_GPU_TCU,
- SAR2130P_MASTER_SYS_TCU,
- SAR2130P_MASTER_APPSS_PROC,
- SAR2130P_MASTER_GFX3D,
- SAR2130P_MASTER_MNOC_HF_MEM_NOC,
- SAR2130P_MASTER_MNOC_SF_MEM_NOC,
- SAR2130P_MASTER_COMPUTE_NOC,
- SAR2130P_MASTER_ANOC_PCIE_GEM_NOC,
- SAR2130P_MASTER_SNOC_GC_MEM_NOC,
- SAR2130P_MASTER_SNOC_SF_MEM_NOC,
- SAR2130P_MASTER_WLAN_Q6,
- SAR2130P_MASTER_CNOC_LPASS_AG_NOC,
- SAR2130P_MASTER_LPASS_PROC,
- SAR2130P_MASTER_LLCC,
- SAR2130P_MASTER_CAMNOC_HF,
- SAR2130P_MASTER_CAMNOC_ICP,
- SAR2130P_MASTER_CAMNOC_SF,
- SAR2130P_MASTER_LSR,
- SAR2130P_MASTER_MDP,
- SAR2130P_MASTER_CNOC_MNOC_CFG,
- SAR2130P_MASTER_VIDEO,
- SAR2130P_MASTER_VIDEO_CV_PROC,
- SAR2130P_MASTER_VIDEO_PROC,
- SAR2130P_MASTER_VIDEO_V_PROC,
- SAR2130P_MASTER_CDSP_NOC_CFG,
- SAR2130P_MASTER_CDSP_PROC,
- SAR2130P_MASTER_PCIE_0,
- SAR2130P_MASTER_PCIE_1,
- SAR2130P_MASTER_GIC_AHB,
- SAR2130P_MASTER_QDSS_BAM,
- SAR2130P_MASTER_QSPI_0,
- SAR2130P_MASTER_QUP_0,
- SAR2130P_MASTER_QUP_1,
- SAR2130P_MASTER_A2NOC_SNOC,
- SAR2130P_MASTER_CNOC_DATAPATH,
- SAR2130P_MASTER_LPASS_ANOC,
- SAR2130P_MASTER_SNOC_CFG,
- SAR2130P_MASTER_CRYPTO,
- SAR2130P_MASTER_PIMEM,
- SAR2130P_MASTER_GIC,
- SAR2130P_MASTER_QDSS_ETR,
- SAR2130P_MASTER_QDSS_ETR_1,
- SAR2130P_MASTER_SDCC_1,
- SAR2130P_MASTER_USB3_0,
- SAR2130P_SLAVE_QUP_CORE_0,
- SAR2130P_SLAVE_QUP_CORE_1,
- SAR2130P_SLAVE_AHB2PHY_SOUTH,
- SAR2130P_SLAVE_AOSS,
- SAR2130P_SLAVE_CAMERA_CFG,
- SAR2130P_SLAVE_CLK_CTL,
- SAR2130P_SLAVE_CDSP_CFG,
- SAR2130P_SLAVE_RBCPR_CX_CFG,
- SAR2130P_SLAVE_RBCPR_MMCX_CFG,
- SAR2130P_SLAVE_RBCPR_MXA_CFG,
- SAR2130P_SLAVE_RBCPR_MXC_CFG,
- SAR2130P_SLAVE_CPR_NSPCX,
- SAR2130P_SLAVE_CRYPTO_0_CFG,
- SAR2130P_SLAVE_CX_RDPM,
- SAR2130P_SLAVE_DISPLAY_CFG,
- SAR2130P_SLAVE_GFX3D_CFG,
- SAR2130P_SLAVE_IMEM_CFG,
- SAR2130P_SLAVE_IPC_ROUTER_CFG,
- SAR2130P_SLAVE_LPASS,
- SAR2130P_SLAVE_MX_RDPM,
- SAR2130P_SLAVE_PCIE_0_CFG,
- SAR2130P_SLAVE_PCIE_1_CFG,
- SAR2130P_SLAVE_PDM,
- SAR2130P_SLAVE_PIMEM_CFG,
- SAR2130P_SLAVE_PRNG,
- SAR2130P_SLAVE_QDSS_CFG,
- SAR2130P_SLAVE_QSPI_0,
- SAR2130P_SLAVE_QUP_0,
- SAR2130P_SLAVE_QUP_1,
- SAR2130P_SLAVE_SDCC_1,
- SAR2130P_SLAVE_TCSR,
- SAR2130P_SLAVE_TLMM,
- SAR2130P_SLAVE_TME_CFG,
- SAR2130P_SLAVE_USB3_0,
- SAR2130P_SLAVE_VENUS_CFG,
- SAR2130P_SLAVE_VSENSE_CTRL_CFG,
- SAR2130P_SLAVE_WLAN_Q6_CFG,
- SAR2130P_SLAVE_DDRSS_CFG,
- SAR2130P_SLAVE_CNOC_MNOC_CFG,
- SAR2130P_SLAVE_SNOC_CFG,
- SAR2130P_SLAVE_IMEM,
- SAR2130P_SLAVE_PIMEM,
- SAR2130P_SLAVE_SERVICE_CNOC,
- SAR2130P_SLAVE_PCIE_0,
- SAR2130P_SLAVE_PCIE_1,
- SAR2130P_SLAVE_QDSS_STM,
- SAR2130P_SLAVE_TCU,
- SAR2130P_SLAVE_GEM_NOC_CNOC,
- SAR2130P_SLAVE_LLCC,
- SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC,
- SAR2130P_SLAVE_LPASS_CORE_CFG,
- SAR2130P_SLAVE_LPASS_LPI_CFG,
- SAR2130P_SLAVE_LPASS_MPU_CFG,
- SAR2130P_SLAVE_LPASS_TOP_CFG,
- SAR2130P_SLAVE_LPASS_SNOC,
- SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC,
- SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC,
- SAR2130P_SLAVE_EBI1,
- SAR2130P_SLAVE_MNOC_HF_MEM_NOC,
- SAR2130P_SLAVE_MNOC_SF_MEM_NOC,
- SAR2130P_SLAVE_SERVICE_MNOC,
- SAR2130P_SLAVE_CDSP_MEM_NOC,
- SAR2130P_SLAVE_SERVICE_NSP_NOC,
- SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC,
- SAR2130P_SLAVE_A2NOC_SNOC,
- SAR2130P_SLAVE_SNOC_GEM_NOC_GC,
- SAR2130P_SLAVE_SNOC_GEM_NOC_SF,
- SAR2130P_SLAVE_SERVICE_SNOC,
-};
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_nsp_gemnoc;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_wlan_q6;
+static struct qcom_icc_node qhm_config_noc;
+static struct qcom_icc_node qxm_lpass_dsp;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_lsr;
+static struct qcom_icc_node qnm_mdp;
+static struct qcom_icc_node qnm_mnoc_cfg;
+static struct qcom_icc_node qnm_video;
+static struct qcom_icc_node qnm_video_cv_cpu;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qhm_nsp_noc_config;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node qhm_gic;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_cnoc_datapath;
+static struct qcom_icc_node qnm_lpass_noc;
+static struct qcom_icc_node qnm_snoc_cfg;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mxa;
+static struct qcom_icc_node qhs_cpr_mxc;
+static struct qcom_icc_node qhs_cpr_nspcx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_tme_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qhs_wlan_q6;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qns_mnoc_cfg;
+static struct qcom_icc_node qns_snoc_cfg;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node qhs_lpass_core;
+static struct qcom_icc_node qhs_lpass_lpi;
+static struct qcom_icc_node qhs_lpass_mpu;
+static struct qcom_icc_node qhs_lpass_top;
+static struct qcom_icc_node qns_sysnoc;
+static struct qcom_icc_node srvc_niu_aml_noc;
+static struct qcom_icc_node srvc_niu_lpass_agnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node service_nsp_noc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node srvc_snoc;
static const struct regmap_config icc_regmap_config = {
.reg_bits = 32,
@@ -149,89 +147,79 @@ static const struct regmap_config icc_regmap_config = {
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SAR2130P_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SAR2130P_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SAR2130P_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 43,
- .links = { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS,
- SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL,
- SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG,
- SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG,
- SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX,
- SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM,
- SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG,
- SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG,
- SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM,
- SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG,
- SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG,
- SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG,
- SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0,
- SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1,
- SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM,
- SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0,
- SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG,
- SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG,
- SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG,
- SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM,
- SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM,
- SAR2130P_SLAVE_TCU },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_aoss,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_compute_cfg, &qhs_cpr_cx,
+ &qhs_cpr_mmcx, &qhs_cpr_mxa,
+ &qhs_cpr_mxc, &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_imem_cfg, &qhs_ipc_router,
+ &qhs_lpass_cfg, &qhs_mx_rdpm,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pdm, &qhs_pimem_cfg,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc1,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_tme_cfg, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qhs_wlan_q6, &qns_ddrss_cfg,
+ &qns_mnoc_cfg, &qns_snoc_cfg,
+ &qxs_imem, &qxs_pimem,
+ &srvc_cnoc, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SAR2130P_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SAR2130P_SLAVE_PCIE_0, SAR2130P_SLAVE_PCIE_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SAR2130P_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 43,
- .links = { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS,
- SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL,
- SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG,
- SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG,
- SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX,
- SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM,
- SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG,
- SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG,
- SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM,
- SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG,
- SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG,
- SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG,
- SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0,
- SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1,
- SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM,
- SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0,
- SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG,
- SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG,
- SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG,
- SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM,
- SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM,
- SAR2130P_SLAVE_TCU },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_aoss,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_compute_cfg, &qhs_cpr_cx,
+ &qhs_cpr_mmcx, &qhs_cpr_mxa,
+ &qhs_cpr_mxc, &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_imem_cfg, &qhs_ipc_router,
+ &qhs_lpass_cfg, &qhs_mx_rdpm,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pdm, &qhs_pimem_cfg,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc1,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_tme_cfg, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qhs_wlan_q6, &qns_ddrss_cfg,
+ &qns_mnoc_cfg, &qns_snoc_cfg,
+ &qxs_imem, &qxs_pimem,
+ &srvc_cnoc, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
@@ -244,12 +232,10 @@ static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SAR2130P_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
.qosbox = &alm_gpu_tcu_qos,
- .num_links = 2,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
@@ -262,22 +248,18 @@ static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SAR2130P_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.qosbox = &alm_sys_tcu_qos,
- .num_links = 2,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SAR2130P_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 3,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC,
- SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static const struct qcom_icc_qosbox qnm_gpu_qos = {
@@ -290,12 +272,10 @@ static const struct qcom_icc_qosbox qnm_gpu_qos = {
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SAR2130P_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_gpu_qos,
- .num_links = 2,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
@@ -307,12 +287,10 @@ static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SAR2130P_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_mnoc_hf_qos,
- .num_links = 2,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
@@ -324,12 +302,10 @@ static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SAR2130P_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
.qosbox = &qnm_mnoc_sf_qos,
- .num_links = 2,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
@@ -342,12 +318,10 @@ static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
static struct qcom_icc_node qnm_nsp_gemnoc = {
.name = "qnm_nsp_gemnoc",
- .id = SAR2130P_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_nsp_gemnoc_qos,
- .num_links = 2,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static const struct qcom_icc_qosbox qnm_pcie_qos = {
@@ -359,12 +333,10 @@ static const struct qcom_icc_qosbox qnm_pcie_qos = {
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SAR2130P_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
.qosbox = &qnm_pcie_qos,
- .num_links = 2,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static const struct qcom_icc_qosbox qnm_snoc_gc_qos = {
@@ -376,12 +348,10 @@ static const struct qcom_icc_qosbox qnm_snoc_gc_qos = {
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SAR2130P_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.qosbox = &qnm_snoc_gc_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
@@ -393,53 +363,43 @@ static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SAR2130P_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.qosbox = &qnm_snoc_sf_qos,
- .num_links = 3,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC,
- SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qxm_wlan_q6 = {
.name = "qxm_wlan_q6",
- .id = SAR2130P_MASTER_WLAN_Q6,
.channels = 1,
.buswidth = 8,
- .num_links = 3,
- .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC,
- SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
- .id = SAR2130P_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 6,
- .links = { SAR2130P_SLAVE_LPASS_CORE_CFG, SAR2130P_SLAVE_LPASS_LPI_CFG,
- SAR2130P_SLAVE_LPASS_MPU_CFG, SAR2130P_SLAVE_LPASS_TOP_CFG,
- SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC },
+ .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
+ &qhs_lpass_mpu, &qhs_lpass_top,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node qxm_lpass_dsp = {
.name = "qxm_lpass_dsp",
- .id = SAR2130P_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 4,
- .links = { SAR2130P_SLAVE_LPASS_TOP_CFG, SAR2130P_SLAVE_LPASS_SNOC,
- SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC },
+ .link_nodes = { &qhs_lpass_top, &qns_sysnoc,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SAR2130P_MASTER_LLCC,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
@@ -451,12 +411,10 @@ static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SAR2130P_MASTER_CAMNOC_HF,
.channels = 1,
.buswidth = 32,
.qosbox = &qnm_camnoc_hf_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
@@ -468,12 +426,10 @@ static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = SAR2130P_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
.qosbox = &qnm_camnoc_icp_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
@@ -485,12 +441,10 @@ static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SAR2130P_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
.qosbox = &qnm_camnoc_sf_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static const struct qcom_icc_qosbox qnm_lsr_qos = {
@@ -502,12 +456,10 @@ static const struct qcom_icc_qosbox qnm_lsr_qos = {
static struct qcom_icc_node qnm_lsr = {
.name = "qnm_lsr",
- .id = SAR2130P_MASTER_LSR,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_lsr_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static const struct qcom_icc_qosbox qnm_mdp_qos = {
@@ -519,21 +471,17 @@ static const struct qcom_icc_qosbox qnm_mdp_qos = {
static struct qcom_icc_node qnm_mdp = {
.name = "qnm_mdp",
- .id = SAR2130P_MASTER_MDP,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_mdp_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mnoc_cfg = {
.name = "qnm_mnoc_cfg",
- .id = SAR2130P_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static const struct qcom_icc_qosbox qnm_video_qos = {
@@ -545,12 +493,10 @@ static const struct qcom_icc_qosbox qnm_video_qos = {
static struct qcom_icc_node qnm_video = {
.name = "qnm_video",
- .id = SAR2130P_MASTER_VIDEO,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_video_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
@@ -562,12 +508,10 @@ static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
static struct qcom_icc_node qnm_video_cv_cpu = {
.name = "qnm_video_cv_cpu",
- .id = SAR2130P_MASTER_VIDEO_CV_PROC,
.channels = 1,
.buswidth = 8,
.qosbox = &qnm_video_cv_cpu_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static const struct qcom_icc_qosbox qnm_video_cvp_qos = {
@@ -579,12 +523,10 @@ static const struct qcom_icc_qosbox qnm_video_cvp_qos = {
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SAR2130P_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
.qosbox = &qnm_video_cvp_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
@@ -596,30 +538,24 @@ static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = SAR2130P_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
.qosbox = &qnm_video_v_cpu_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
- .id = SAR2130P_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_SERVICE_NSP_NOC },
+ .link_nodes = { &service_nsp_noc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SAR2130P_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static const struct qcom_icc_qosbox xm_pcie3_0_qos = {
@@ -632,12 +568,10 @@ static const struct qcom_icc_qosbox xm_pcie3_0_qos = {
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SAR2130P_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_pcie3_0_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static const struct qcom_icc_qosbox xm_pcie3_1_qos = {
@@ -650,12 +584,10 @@ static const struct qcom_icc_qosbox xm_pcie3_1_qos = {
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SAR2130P_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_pcie3_1_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static const struct qcom_icc_qosbox qhm_gic_qos = {
@@ -668,12 +600,10 @@ static const struct qcom_icc_qosbox qhm_gic_qos = {
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
- .id = SAR2130P_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_gic_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
@@ -686,12 +616,10 @@ static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SAR2130P_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_qdss_bam_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static const struct qcom_icc_qosbox qhm_qspi_qos = {
@@ -704,12 +632,10 @@ static const struct qcom_icc_qosbox qhm_qspi_qos = {
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SAR2130P_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_qspi_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static const struct qcom_icc_qosbox qhm_qup0_qos = {
@@ -722,12 +648,10 @@ static const struct qcom_icc_qosbox qhm_qup0_qos = {
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SAR2130P_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_qup0_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static const struct qcom_icc_qosbox qhm_qup1_qos = {
@@ -740,21 +664,17 @@ static const struct qcom_icc_qosbox qhm_qup1_qos = {
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SAR2130P_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_qup1_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SAR2130P_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = {
@@ -767,12 +687,10 @@ static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = {
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
- .id = SAR2130P_MASTER_CNOC_DATAPATH,
.channels = 1,
.buswidth = 8,
.qosbox = &qnm_cnoc_datapath_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static const struct qcom_icc_qosbox qnm_lpass_noc_qos = {
@@ -785,21 +703,17 @@ static const struct qcom_icc_qosbox qnm_lpass_noc_qos = {
static struct qcom_icc_node qnm_lpass_noc = {
.name = "qnm_lpass_noc",
- .id = SAR2130P_MASTER_LPASS_ANOC,
.channels = 1,
.buswidth = 16,
.qosbox = &qnm_lpass_noc_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
- .id = SAR2130P_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static const struct qcom_icc_qosbox qxm_crypto_qos = {
@@ -812,12 +726,10 @@ static const struct qcom_icc_qosbox qxm_crypto_qos = {
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SAR2130P_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
.qosbox = &qxm_crypto_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static const struct qcom_icc_qosbox qxm_pimem_qos = {
@@ -830,12 +742,10 @@ static const struct qcom_icc_qosbox qxm_pimem_qos = {
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SAR2130P_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
.qosbox = &qxm_pimem_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static const struct qcom_icc_qosbox xm_gic_qos = {
@@ -848,12 +758,10 @@ static const struct qcom_icc_qosbox xm_gic_qos = {
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SAR2130P_MASTER_GIC,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_gic_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
@@ -866,12 +774,10 @@ static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = SAR2130P_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_qdss_etr_0_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
@@ -884,12 +790,10 @@ static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = SAR2130P_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_qdss_etr_1_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static const struct qcom_icc_qosbox xm_sdc1_qos = {
@@ -902,12 +806,10 @@ static const struct qcom_icc_qosbox xm_sdc1_qos = {
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = SAR2130P_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_sdc1_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static const struct qcom_icc_qosbox xm_usb3_0_qos = {
@@ -920,571 +822,486 @@ static const struct qcom_icc_qosbox xm_usb3_0_qos = {
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SAR2130P_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_usb3_0_qos,
- .num_links = 1,
- .links = { SAR2130P_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SAR2130P_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SAR2130P_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SAR2130P_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SAR2130P_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SAR2130P_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SAR2130P_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_cfg = {
.name = "qhs_compute_cfg",
- .id = SAR2130P_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_MASTER_CDSP_NOC_CFG },
+ .link_nodes = { &qhm_nsp_noc_config, NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SAR2130P_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SAR2130P_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxa = {
.name = "qhs_cpr_mxa",
- .id = SAR2130P_SLAVE_RBCPR_MXA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxc = {
.name = "qhs_cpr_mxc",
- .id = SAR2130P_SLAVE_RBCPR_MXC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_nspcx = {
.name = "qhs_cpr_nspcx",
- .id = SAR2130P_SLAVE_CPR_NSPCX,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SAR2130P_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SAR2130P_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SAR2130P_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SAR2130P_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SAR2130P_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SAR2130P_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = SAR2130P_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_MASTER_CNOC_LPASS_AG_NOC },
+ .link_nodes = { &qhm_config_noc, NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SAR2130P_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SAR2130P_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SAR2130P_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SAR2130P_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SAR2130P_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SAR2130P_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SAR2130P_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SAR2130P_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SAR2130P_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SAR2130P_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = SAR2130P_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SAR2130P_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SAR2130P_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
- .id = SAR2130P_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SAR2130P_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SAR2130P_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SAR2130P_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_wlan_q6 = {
.name = "qhs_wlan_q6",
- .id = SAR2130P_SLAVE_WLAN_Q6_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = SAR2130P_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mnoc_cfg = {
.name = "qns_mnoc_cfg",
- .id = SAR2130P_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qnm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
- .id = SAR2130P_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SAR2130P_MASTER_SNOC_CFG },
+ .link_nodes = { &qnm_snoc_cfg, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SAR2130P_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SAR2130P_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SAR2130P_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SAR2130P_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SAR2130P_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SAR2130P_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SAR2130P_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SAR2130P_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SAR2130P_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SAR2130P_SLAVE_LLCC,
.channels = 2,
.buswidth = 16,
- .num_links = 1,
- .links = { SAR2130P_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SAR2130P_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
- .id = SAR2130P_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
- .id = SAR2130P_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
- .id = SAR2130P_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
- .id = SAR2130P_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_sysnoc = {
.name = "qns_sysnoc",
- .id = SAR2130P_SLAVE_LPASS_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SAR2130P_MASTER_LPASS_ANOC },
+ .link_nodes = { &qnm_lpass_noc, NULL },
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
- .id = SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
- .id = SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SAR2130P_SLAVE_EBI1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SAR2130P_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SAR2130P_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SAR2130P_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SAR2130P_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SAR2130P_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SAR2130P_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SAR2130P_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_nsp_gemnoc, NULL },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
- .id = SAR2130P_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SAR2130P_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SAR2130P_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SAR2130P_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SAR2130P_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SAR2130P_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SAR2130P_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SAR2130P_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SAR2130P_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1630,6 +1447,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1692,6 +1510,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_config_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
@@ -1722,6 +1541,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_gem_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
@@ -1745,6 +1565,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
@@ -1763,6 +1584,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1791,6 +1613,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_mmss_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
@@ -1810,6 +1633,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_nsp_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
@@ -1828,6 +1652,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_pcie_anoc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
@@ -1867,6 +1692,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_system_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 15/28] interconnect: qcom: sc7180: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (13 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 14/28] interconnect: qcom: sar2130p: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 16/28] interconnect: qcom: sdm670: " Dmitry Baryshkov
` (13 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sc7180.c | 829 +++++++++++++++++++------------------
drivers/interconnect/qcom/sc7180.h | 149 -------
2 files changed, 416 insertions(+), 562 deletions(-)
diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c
index 6397d693918b41e35684b180fd6b8f5cb359386e..2d9099e909bb9fbc9b82370e488d014391324637 100644
--- a/drivers/interconnect/qcom/sc7180.c
+++ b/drivers/interconnect/qcom/sc7180.c
@@ -14,1226 +14,1217 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sc7180.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup_0;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_emmc;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node qhm_a2noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup_1;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node qhm_usb3;
+static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node qxm_camnoc_hf1_uncomp;
+static struct qcom_icc_node qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node qnm_npu;
+static struct qcom_icc_node qxm_npu_dsp;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qhm_cnoc_dc_noc;
+static struct qcom_icc_node acm_apps0;
+static struct qcom_icc_node acm_sys_tcu;
+static struct qcom_icc_node qhm_gemnoc_cfg;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_gpu;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qxm_camnoc_hf0;
+static struct qcom_icc_node qxm_camnoc_hf1;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node qxm_venus0;
+static struct qcom_icc_node qxm_venus_arm9;
+static struct qcom_icc_node amm_npu_sys;
+static struct qcom_icc_node qhm_npu_cfg;
+static struct qcom_icc_node qup_core_master_1;
+static struct qcom_icc_node qup_core_master_2;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gemnoc;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_camnoc_uncomp;
+static struct qcom_icc_node qns_cdsp_gemnoc;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_a2_noc_cfg;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy2;
+static struct qcom_icc_node qhs_aop;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_boot_rom;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_camera_nrt_throttle_cfg;
+static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_display_rt_throttle_cfg;
+static struct qcom_icc_node qhs_display_throttle_cfg;
+static struct qcom_icc_node qhs_emmc_cfg;
+static struct qcom_icc_node qhs_glm;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_npu_cfg;
+static struct qcom_icc_node qhs_npu_dma_throttle_cfg;
+static struct qcom_icc_node qhs_npu_dsp_throttle_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qm_cfg;
+static struct qcom_icc_node qhs_qm_mpu_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_security;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm_1;
+static struct qcom_icc_node qhs_tlmm_2;
+static struct qcom_icc_node qhs_tlmm_3;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_venus_throttle_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_gemnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qns_gem_noc_snoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node srvc_gemnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_cal_dp0;
+static struct qcom_icc_node qhs_cp;
+static struct qcom_icc_node qhs_dma_bwmon;
+static struct qcom_icc_node qhs_dpm;
+static struct qcom_icc_node qhs_isense;
+static struct qcom_icc_node qhs_llm;
+static struct qcom_icc_node qhs_tcm;
+static struct qcom_icc_node qns_npu_sys;
+static struct qcom_icc_node srvc_noc;
+static struct qcom_icc_node qup_core_slave_1;
+static struct qcom_icc_node qup_core_slave_2;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qhm_a1noc_cfg = {
.name = "qhm_a1noc_cfg",
- .id = SC7180_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SC7180_MASTER_QSPI,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup_0 = {
.name = "qhm_qup_0",
- .id = SC7180_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SC7180_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emmc = {
.name = "xm_emmc",
- .id = SC7180_MASTER_EMMC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SC7180_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_a2noc_cfg = {
.name = "qhm_a2noc_cfg",
- .id = SC7180_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SC7180_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup_1 = {
.name = "qhm_qup_1",
- .id = SC7180_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SC7180_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SC7180_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SC7180_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_usb3 = {
.name = "qhm_usb3",
- .id = SC7180_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
.name = "qxm_camnoc_hf0_uncomp",
- .id = SC7180_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
.name = "qxm_camnoc_hf1_uncomp",
- .id = SC7180_MASTER_CAMNOC_HF1_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
.name = "qxm_camnoc_sf_uncomp",
- .id = SC7180_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qnm_npu = {
.name = "qnm_npu",
- .id = SC7180_MASTER_NPU,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_CDSP_GEM_NOC },
+ .link_nodes = { &qns_cdsp_gemnoc, NULL },
};
static struct qcom_icc_node qxm_npu_dsp = {
.name = "qxm_npu_dsp",
- .id = SC7180_MASTER_NPU_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_CDSP_GEM_NOC },
+ .link_nodes = { &qns_cdsp_gemnoc, NULL },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = SC7180_MASTER_SNOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 51,
- .links = { SC7180_SLAVE_A1NOC_CFG,
- SC7180_SLAVE_A2NOC_CFG,
- SC7180_SLAVE_AHB2PHY_SOUTH,
- SC7180_SLAVE_AHB2PHY_CENTER,
- SC7180_SLAVE_AOP,
- SC7180_SLAVE_AOSS,
- SC7180_SLAVE_BOOT_ROM,
- SC7180_SLAVE_CAMERA_CFG,
- SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SC7180_SLAVE_CLK_CTL,
- SC7180_SLAVE_RBCPR_CX_CFG,
- SC7180_SLAVE_RBCPR_MX_CFG,
- SC7180_SLAVE_CRYPTO_0_CFG,
- SC7180_SLAVE_DCC_CFG,
- SC7180_SLAVE_CNOC_DDRSS,
- SC7180_SLAVE_DISPLAY_CFG,
- SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
- SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
- SC7180_SLAVE_EMMC_CFG,
- SC7180_SLAVE_GLM,
- SC7180_SLAVE_GFX3D_CFG,
- SC7180_SLAVE_IMEM_CFG,
- SC7180_SLAVE_IPA_CFG,
- SC7180_SLAVE_CNOC_MNOC_CFG,
- SC7180_SLAVE_CNOC_MSS,
- SC7180_SLAVE_NPU_CFG,
- SC7180_SLAVE_NPU_DMA_BWMON_CFG,
- SC7180_SLAVE_NPU_PROC_BWMON_CFG,
- SC7180_SLAVE_PDM,
- SC7180_SLAVE_PIMEM_CFG,
- SC7180_SLAVE_PRNG,
- SC7180_SLAVE_QDSS_CFG,
- SC7180_SLAVE_QM_CFG,
- SC7180_SLAVE_QM_MPU_CFG,
- SC7180_SLAVE_QSPI_0,
- SC7180_SLAVE_QUP_0,
- SC7180_SLAVE_QUP_1,
- SC7180_SLAVE_SDCC_2,
- SC7180_SLAVE_SECURITY,
- SC7180_SLAVE_SNOC_CFG,
- SC7180_SLAVE_TCSR,
- SC7180_SLAVE_TLMM_WEST,
- SC7180_SLAVE_TLMM_NORTH,
- SC7180_SLAVE_TLMM_SOUTH,
- SC7180_SLAVE_UFS_MEM_CFG,
- SC7180_SLAVE_USB3,
- SC7180_SLAVE_VENUS_CFG,
- SC7180_SLAVE_VENUS_THROTTLE_CFG,
- SC7180_SLAVE_VSENSE_CTRL_CFG,
- SC7180_SLAVE_SERVICE_CNOC
- },
+ .link_nodes = { &qhs_a1_noc_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_ahb2phy0,
+ &qhs_ahb2phy2,
+ &qhs_aop,
+ &qhs_aoss,
+ &qhs_boot_rom,
+ &qhs_camera_cfg,
+ &qhs_camera_nrt_throttle_cfg,
+ &qhs_camera_rt_throttle_cfg,
+ &qhs_clk_ctl,
+ &qhs_cpr_cx,
+ &qhs_cpr_mx,
+ &qhs_crypto0_cfg,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_display_cfg,
+ &qhs_display_rt_throttle_cfg,
+ &qhs_display_throttle_cfg,
+ &qhs_emmc_cfg,
+ &qhs_glm,
+ &qhs_gpuss_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mnoc_cfg,
+ &qhs_mss_cfg,
+ &qhs_npu_cfg,
+ &qhs_npu_dma_throttle_cfg,
+ &qhs_npu_dsp_throttle_cfg,
+ &qhs_pdm,
+ &qhs_pimem_cfg,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qm_cfg,
+ &qhs_qm_mpu_cfg,
+ &qhs_qspi,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_sdc2,
+ &qhs_security,
+ &qhs_snoc_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm_1,
+ &qhs_tlmm_2,
+ &qhs_tlmm_3,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3,
+ &qhs_venus_cfg,
+ &qhs_venus_throttle_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SC7180_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 51,
- .links = { SC7180_SLAVE_A1NOC_CFG,
- SC7180_SLAVE_A2NOC_CFG,
- SC7180_SLAVE_AHB2PHY_SOUTH,
- SC7180_SLAVE_AHB2PHY_CENTER,
- SC7180_SLAVE_AOP,
- SC7180_SLAVE_AOSS,
- SC7180_SLAVE_BOOT_ROM,
- SC7180_SLAVE_CAMERA_CFG,
- SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SC7180_SLAVE_CLK_CTL,
- SC7180_SLAVE_RBCPR_CX_CFG,
- SC7180_SLAVE_RBCPR_MX_CFG,
- SC7180_SLAVE_CRYPTO_0_CFG,
- SC7180_SLAVE_DCC_CFG,
- SC7180_SLAVE_CNOC_DDRSS,
- SC7180_SLAVE_DISPLAY_CFG,
- SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
- SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
- SC7180_SLAVE_EMMC_CFG,
- SC7180_SLAVE_GLM,
- SC7180_SLAVE_GFX3D_CFG,
- SC7180_SLAVE_IMEM_CFG,
- SC7180_SLAVE_IPA_CFG,
- SC7180_SLAVE_CNOC_MNOC_CFG,
- SC7180_SLAVE_CNOC_MSS,
- SC7180_SLAVE_NPU_CFG,
- SC7180_SLAVE_NPU_DMA_BWMON_CFG,
- SC7180_SLAVE_NPU_PROC_BWMON_CFG,
- SC7180_SLAVE_PDM,
- SC7180_SLAVE_PIMEM_CFG,
- SC7180_SLAVE_PRNG,
- SC7180_SLAVE_QDSS_CFG,
- SC7180_SLAVE_QM_CFG,
- SC7180_SLAVE_QM_MPU_CFG,
- SC7180_SLAVE_QSPI_0,
- SC7180_SLAVE_QUP_0,
- SC7180_SLAVE_QUP_1,
- SC7180_SLAVE_SDCC_2,
- SC7180_SLAVE_SECURITY,
- SC7180_SLAVE_SNOC_CFG,
- SC7180_SLAVE_TCSR,
- SC7180_SLAVE_TLMM_WEST,
- SC7180_SLAVE_TLMM_NORTH,
- SC7180_SLAVE_TLMM_SOUTH,
- SC7180_SLAVE_UFS_MEM_CFG,
- SC7180_SLAVE_USB3,
- SC7180_SLAVE_VENUS_CFG,
- SC7180_SLAVE_VENUS_THROTTLE_CFG,
- SC7180_SLAVE_VSENSE_CTRL_CFG,
- SC7180_SLAVE_SERVICE_CNOC
- },
+ .link_nodes = { &qhs_a1_noc_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_ahb2phy0,
+ &qhs_ahb2phy2,
+ &qhs_aop,
+ &qhs_aoss,
+ &qhs_boot_rom,
+ &qhs_camera_cfg,
+ &qhs_camera_nrt_throttle_cfg,
+ &qhs_camera_rt_throttle_cfg,
+ &qhs_clk_ctl,
+ &qhs_cpr_cx,
+ &qhs_cpr_mx,
+ &qhs_crypto0_cfg,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_display_cfg,
+ &qhs_display_rt_throttle_cfg,
+ &qhs_display_throttle_cfg,
+ &qhs_emmc_cfg,
+ &qhs_glm,
+ &qhs_gpuss_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mnoc_cfg,
+ &qhs_mss_cfg,
+ &qhs_npu_cfg,
+ &qhs_npu_dma_throttle_cfg,
+ &qhs_npu_dsp_throttle_cfg,
+ &qhs_pdm,
+ &qhs_pimem_cfg,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qm_cfg,
+ &qhs_qm_mpu_cfg,
+ &qhs_qspi,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_sdc2,
+ &qhs_security,
+ &qhs_snoc_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm_1,
+ &qhs_tlmm_2,
+ &qhs_tlmm_3,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3,
+ &qhs_venus_cfg,
+ &qhs_venus_throttle_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &srvc_cnoc, NULL },
};
static struct qcom_icc_node qhm_cnoc_dc_noc = {
.name = "qhm_cnoc_dc_noc",
- .id = SC7180_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SC7180_SLAVE_GEM_NOC_CFG,
- SC7180_SLAVE_LLCC_CFG
- },
+ .link_nodes = { &qhs_gemnoc,
+ &qhs_llcc, NULL },
};
static struct qcom_icc_node acm_apps0 = {
.name = "acm_apps0",
- .id = SC7180_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SC7180_SLAVE_GEM_NOC_SNOC,
- SC7180_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_snoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node acm_sys_tcu = {
.name = "acm_sys_tcu",
- .id = SC7180_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC7180_SLAVE_GEM_NOC_SNOC,
- SC7180_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_snoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qhm_gemnoc_cfg = {
.name = "qhm_gemnoc_cfg",
- .id = SC7180_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG,
- SC7180_SLAVE_SERVICE_GEM_NOC
- },
+ .link_nodes = { &qhs_mdsp_ms_mpu_cfg,
+ &srvc_gemnoc, NULL },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SC7180_MASTER_COMPUTE_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SC7180_SLAVE_GEM_NOC_SNOC,
- SC7180_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_snoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SC7180_MASTER_MNOC_HF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SC7180_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SC7180_SLAVE_GEM_NOC_SNOC,
- SC7180_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_snoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SC7180_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SC7180_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7180_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qxm_gpu = {
.name = "qxm_gpu",
- .id = SC7180_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SC7180_SLAVE_GEM_NOC_SNOC,
- SC7180_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_snoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SC7180_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = SC7180_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0 = {
.name = "qxm_camnoc_hf0",
- .id = SC7180_MASTER_CAMNOC_HF0,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1 = {
.name = "qxm_camnoc_hf1",
- .id = SC7180_MASTER_CAMNOC_HF1,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SC7180_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SC7180_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = SC7180_MASTER_ROTATOR,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_venus0 = {
.name = "qxm_venus0",
- .id = SC7180_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_venus_arm9 = {
.name = "qxm_venus_arm9",
- .id = SC7180_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node amm_npu_sys = {
.name = "amm_npu_sys",
- .id = SC7180_MASTER_NPU_SYS,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_SLAVE_NPU_COMPUTE_NOC },
+ .link_nodes = { &qns_npu_sys, NULL },
};
static struct qcom_icc_node qhm_npu_cfg = {
.name = "qhm_npu_cfg",
- .id = SC7180_MASTER_NPU_NOC_CFG,
- .channels = 1,
- .buswidth = 4,
- .num_links = 8,
- .links = { SC7180_SLAVE_NPU_CAL_DP0,
- SC7180_SLAVE_NPU_CP,
- SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG,
- SC7180_SLAVE_NPU_DPM,
- SC7180_SLAVE_ISENSE_CFG,
- SC7180_SLAVE_NPU_LLM_CFG,
- SC7180_SLAVE_NPU_TCM,
- SC7180_SLAVE_SERVICE_NPU_NOC
- },
+ .channels = 1,
+ .buswidth = 4,
+ .link_nodes = { &qhs_cal_dp0,
+ &qhs_cp,
+ &qhs_dma_bwmon,
+ &qhs_dpm,
+ &qhs_isense,
+ &qhs_llm,
+ &qhs_tcm,
+ &srvc_noc, NULL },
};
static struct qcom_icc_node qup_core_master_1 = {
.name = "qup_core_master_1",
- .id = SC7180_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup_core_slave_1, NULL },
};
static struct qcom_icc_node qup_core_master_2 = {
.name = "qup_core_master_2",
- .id = SC7180_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup_core_slave_2, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SC7180_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SC7180_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SC7180_SLAVE_APPSS,
- SC7180_SLAVE_SNOC_CNOC,
- SC7180_SLAVE_SNOC_GEM_NOC_SF,
- SC7180_SLAVE_IMEM,
- SC7180_SLAVE_PIMEM,
- SC7180_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qhs_apss,
+ &qns_cnoc,
+ &qns_gemnoc_sf,
+ &qxs_imem,
+ &qxs_pimem,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SC7180_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 7,
- .links = { SC7180_SLAVE_APPSS,
- SC7180_SLAVE_SNOC_CNOC,
- SC7180_SLAVE_SNOC_GEM_NOC_SF,
- SC7180_SLAVE_IMEM,
- SC7180_SLAVE_PIMEM,
- SC7180_SLAVE_QDSS_STM,
- SC7180_SLAVE_TCU
- },
+ .link_nodes = { &qhs_apss,
+ &qns_cnoc,
+ &qns_gemnoc_sf,
+ &qxs_imem,
+ &qxs_pimem,
+ &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc = {
.name = "qnm_gemnoc",
- .id = SC7180_MASTER_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 6,
- .links = { SC7180_SLAVE_APPSS,
- SC7180_SLAVE_SNOC_CNOC,
- SC7180_SLAVE_IMEM,
- SC7180_SLAVE_PIMEM,
- SC7180_SLAVE_QDSS_STM,
- SC7180_SLAVE_TCU
- },
+ .link_nodes = { &qhs_apss,
+ &qns_cnoc,
+ &qxs_imem,
+ &qxs_pimem,
+ &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SC7180_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SC7180_SLAVE_SNOC_GEM_NOC_GC,
- SC7180_SLAVE_IMEM
- },
+ .link_nodes = { &qns_gemnoc_gc,
+ &qxs_imem, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SC7180_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7180_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SC7180_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SC7180_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7180_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SC7180_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_camnoc_uncomp = {
.name = "qns_camnoc_uncomp",
- .id = SC7180_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cdsp_gemnoc = {
.name = "qns_cdsp_gemnoc",
- .id = SC7180_SLAVE_CDSP_GEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = SC7180_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qhs_a2_noc_cfg = {
.name = "qhs_a2_noc_cfg",
- .id = SC7180_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_MASTER_A2NOC_CFG },
+ .link_nodes = { &qhm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SC7180_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy2 = {
.name = "qhs_ahb2phy2",
- .id = SC7180_SLAVE_AHB2PHY_CENTER,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
- .id = SC7180_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SC7180_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_boot_rom = {
.name = "qhs_boot_rom",
- .id = SC7180_SLAVE_BOOT_ROM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SC7180_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
.name = "qhs_camera_nrt_throttle_cfg",
- .id = SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
.name = "qhs_camera_rt_throttle_cfg",
- .id = SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SC7180_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SC7180_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SC7180_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SC7180_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SC7180_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SC7180_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SC7180_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_rt_throttle_cfg = {
.name = "qhs_display_rt_throttle_cfg",
- .id = SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_throttle_cfg = {
.name = "qhs_display_throttle_cfg",
- .id = SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emmc_cfg = {
.name = "qhs_emmc_cfg",
- .id = SC7180_SLAVE_EMMC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_glm = {
.name = "qhs_glm",
- .id = SC7180_SLAVE_GLM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SC7180_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SC7180_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SC7180_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = SC7180_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SC7180_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_npu_cfg = {
.name = "qhs_npu_cfg",
- .id = SC7180_SLAVE_NPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_MASTER_NPU_NOC_CFG },
+ .link_nodes = { &qhm_npu_cfg, NULL },
};
static struct qcom_icc_node qhs_npu_dma_throttle_cfg = {
.name = "qhs_npu_dma_throttle_cfg",
- .id = SC7180_SLAVE_NPU_DMA_BWMON_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = {
.name = "qhs_npu_dsp_throttle_cfg",
- .id = SC7180_SLAVE_NPU_PROC_BWMON_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SC7180_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SC7180_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SC7180_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SC7180_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qm_cfg = {
.name = "qhs_qm_cfg",
- .id = SC7180_SLAVE_QM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qm_mpu_cfg = {
.name = "qhs_qm_mpu_cfg",
- .id = SC7180_SLAVE_QM_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SC7180_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SC7180_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SC7180_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SC7180_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
- .id = SC7180_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SC7180_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SC7180_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_1 = {
.name = "qhs_tlmm_1",
- .id = SC7180_SLAVE_TLMM_WEST,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_2 = {
.name = "qhs_tlmm_2",
- .id = SC7180_SLAVE_TLMM_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_3 = {
.name = "qhs_tlmm_3",
- .id = SC7180_SLAVE_TLMM_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SC7180_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
- .id = SC7180_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SC7180_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_throttle_cfg = {
.name = "qhs_venus_throttle_cfg",
- .id = SC7180_SLAVE_VENUS_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SC7180_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SC7180_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gemnoc = {
.name = "qhs_gemnoc",
- .id = SC7180_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SC7180_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qhm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SC7180_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SC7180_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_snoc = {
.name = "qns_gem_noc_snoc",
- .id = SC7180_SLAVE_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_MASTER_GEM_NOC_SNOC },
+ .link_nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SC7180_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7180_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node srvc_gemnoc = {
.name = "srvc_gemnoc",
- .id = SC7180_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SC7180_SLAVE_EBI1,
.channels = 2,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SC7180_SLAVE_MNOC_HF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SC7180_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SC7180_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SC7180_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cal_dp0 = {
.name = "qhs_cal_dp0",
- .id = SC7180_SLAVE_NPU_CAL_DP0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cp = {
.name = "qhs_cp",
- .id = SC7180_SLAVE_NPU_CP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dma_bwmon = {
.name = "qhs_dma_bwmon",
- .id = SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dpm = {
.name = "qhs_dpm",
- .id = SC7180_SLAVE_NPU_DPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_isense = {
.name = "qhs_isense",
- .id = SC7180_SLAVE_ISENSE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llm = {
.name = "qhs_llm",
- .id = SC7180_SLAVE_NPU_LLM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcm = {
.name = "qhs_tcm",
- .id = SC7180_SLAVE_NPU_TCM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_npu_sys = {
.name = "qns_npu_sys",
- .id = SC7180_SLAVE_NPU_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_noc = {
.name = "srvc_noc",
- .id = SC7180_SLAVE_SERVICE_NPU_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup_core_slave_1 = {
.name = "qup_core_slave_1",
- .id = SC7180_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup_core_slave_2 = {
.name = "qup_core_slave_2",
- .id = SC7180_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SC7180_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = SC7180_SLAVE_SNOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_MASTER_SNOC_CNOC },
+ .link_nodes = { &qnm_snoc, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SC7180_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SC7180_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SC7180_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SC7180_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SC7180_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SC7180_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SC7180_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SC7180_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SC7180_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1458,6 +1449,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1481,6 +1473,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1499,6 +1492,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = {
};
static const struct qcom_icc_desc sc7180_camnoc_virt = {
+ .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1518,6 +1512,7 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_compute_noc = {
+ .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1586,6 +1581,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1599,6 +1595,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@@ -1627,6 +1624,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1644,6 +1642,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sc7180_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1671,6 +1670,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1692,6 +1692,7 @@ static struct qcom_icc_node * const npu_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_npu_noc = {
+ .alloc_dyn_id = true,
.nodes = npu_noc_nodes,
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
};
@@ -1708,6 +1709,7 @@ static struct qcom_icc_node * const qup_virt_nodes[] = {
};
static const struct qcom_icc_desc sc7180_qup_virt = {
+ .alloc_dyn_id = true,
.nodes = qup_virt_nodes,
.num_nodes = ARRAY_SIZE(qup_virt_nodes),
.bcms = qup_virt_bcms,
@@ -1743,6 +1745,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom/sc7180.h
deleted file mode 100644
index 2b718922c10903fbb4f127e9b1d15f99f385c5c5..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sc7180.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm #define SC7180 interconnect IDs
- *
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7180_H
-#define __DRIVERS_INTERCONNECT_QCOM_SC7180_H
-
-#define SC7180_MASTER_APPSS_PROC 0
-#define SC7180_MASTER_SYS_TCU 1
-#define SC7180_MASTER_NPU_SYS 2
-/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */
-#define SC7180_MASTER_LLCC 4
-#define SC7180_MASTER_A1NOC_CFG 5
-#define SC7180_MASTER_A2NOC_CFG 6
-#define SC7180_MASTER_CNOC_DC_NOC 7
-#define SC7180_MASTER_GEM_NOC_CFG 8
-#define SC7180_MASTER_CNOC_MNOC_CFG 9
-#define SC7180_MASTER_NPU_NOC_CFG 10
-#define SC7180_MASTER_QDSS_BAM 11
-#define SC7180_MASTER_QSPI 12
-#define SC7180_MASTER_QUP_0 13
-#define SC7180_MASTER_QUP_1 14
-#define SC7180_MASTER_SNOC_CFG 15
-#define SC7180_MASTER_A1NOC_SNOC 16
-#define SC7180_MASTER_A2NOC_SNOC 17
-#define SC7180_MASTER_COMPUTE_NOC 18
-#define SC7180_MASTER_GEM_NOC_SNOC 19
-#define SC7180_MASTER_MNOC_HF_MEM_NOC 20
-#define SC7180_MASTER_MNOC_SF_MEM_NOC 21
-#define SC7180_MASTER_NPU 22
-#define SC7180_MASTER_SNOC_CNOC 23
-#define SC7180_MASTER_SNOC_GC_MEM_NOC 24
-#define SC7180_MASTER_SNOC_SF_MEM_NOC 25
-#define SC7180_MASTER_QUP_CORE_0 26
-#define SC7180_MASTER_QUP_CORE_1 27
-#define SC7180_MASTER_CAMNOC_HF0 28
-#define SC7180_MASTER_CAMNOC_HF1 29
-#define SC7180_MASTER_CAMNOC_HF0_UNCOMP 30
-#define SC7180_MASTER_CAMNOC_HF1_UNCOMP 31
-#define SC7180_MASTER_CAMNOC_SF 32
-#define SC7180_MASTER_CAMNOC_SF_UNCOMP 33
-#define SC7180_MASTER_CRYPTO 34
-#define SC7180_MASTER_GFX3D 35
-#define SC7180_MASTER_IPA 36
-#define SC7180_MASTER_MDP0 37
-#define SC7180_MASTER_NPU_PROC 38
-#define SC7180_MASTER_PIMEM 39
-#define SC7180_MASTER_ROTATOR 40
-#define SC7180_MASTER_VIDEO_P0 41
-#define SC7180_MASTER_VIDEO_PROC 42
-#define SC7180_MASTER_QDSS_DAP 43
-#define SC7180_MASTER_QDSS_ETR 44
-#define SC7180_MASTER_SDCC_2 45
-#define SC7180_MASTER_UFS_MEM 46
-#define SC7180_MASTER_USB3 47
-#define SC7180_MASTER_EMMC 48
-#define SC7180_SLAVE_EBI1 49
-/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
-#define SC7180_SLAVE_A1NOC_CFG 51
-#define SC7180_SLAVE_A2NOC_CFG 52
-#define SC7180_SLAVE_AHB2PHY_SOUTH 53
-#define SC7180_SLAVE_AHB2PHY_CENTER 54
-#define SC7180_SLAVE_AOP 55
-#define SC7180_SLAVE_AOSS 56
-#define SC7180_SLAVE_APPSS 57
-#define SC7180_SLAVE_BOOT_ROM 58
-#define SC7180_SLAVE_NPU_CAL_DP0 59
-#define SC7180_SLAVE_CAMERA_CFG 60
-#define SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG 61
-#define SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG 62
-#define SC7180_SLAVE_CLK_CTL 63
-#define SC7180_SLAVE_NPU_CP 64
-#define SC7180_SLAVE_RBCPR_CX_CFG 65
-#define SC7180_SLAVE_RBCPR_MX_CFG 66
-#define SC7180_SLAVE_CRYPTO_0_CFG 67
-#define SC7180_SLAVE_DCC_CFG 68
-#define SC7180_SLAVE_CNOC_DDRSS 69
-#define SC7180_SLAVE_DISPLAY_CFG 70
-#define SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG 71
-#define SC7180_SLAVE_DISPLAY_THROTTLE_CFG 72
-#define SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG 73
-#define SC7180_SLAVE_NPU_DPM 74
-#define SC7180_SLAVE_EMMC_CFG 75
-#define SC7180_SLAVE_GEM_NOC_CFG 76
-#define SC7180_SLAVE_GLM 77
-#define SC7180_SLAVE_GFX3D_CFG 78
-#define SC7180_SLAVE_IMEM_CFG 79
-#define SC7180_SLAVE_IPA_CFG 80
-#define SC7180_SLAVE_ISENSE_CFG 81
-#define SC7180_SLAVE_LLCC_CFG 82
-#define SC7180_SLAVE_NPU_LLM_CFG 83
-#define SC7180_SLAVE_MSS_PROC_MS_MPU_CFG 84
-#define SC7180_SLAVE_CNOC_MNOC_CFG 85
-#define SC7180_SLAVE_CNOC_MSS 86
-#define SC7180_SLAVE_NPU_CFG 87
-#define SC7180_SLAVE_NPU_DMA_BWMON_CFG 88
-#define SC7180_SLAVE_NPU_PROC_BWMON_CFG 89
-#define SC7180_SLAVE_PDM 90
-#define SC7180_SLAVE_PIMEM_CFG 91
-#define SC7180_SLAVE_PRNG 92
-#define SC7180_SLAVE_QDSS_CFG 93
-#define SC7180_SLAVE_QM_CFG 94
-#define SC7180_SLAVE_QM_MPU_CFG 95
-#define SC7180_SLAVE_QSPI_0 96
-#define SC7180_SLAVE_QUP_0 97
-#define SC7180_SLAVE_QUP_1 98
-#define SC7180_SLAVE_SDCC_2 99
-#define SC7180_SLAVE_SECURITY 100
-#define SC7180_SLAVE_SNOC_CFG 101
-#define SC7180_SLAVE_NPU_TCM 102
-#define SC7180_SLAVE_TCSR 103
-#define SC7180_SLAVE_TLMM_WEST 104
-#define SC7180_SLAVE_TLMM_NORTH 105
-#define SC7180_SLAVE_TLMM_SOUTH 106
-#define SC7180_SLAVE_UFS_MEM_CFG 107
-#define SC7180_SLAVE_USB3 108
-#define SC7180_SLAVE_VENUS_CFG 109
-#define SC7180_SLAVE_VENUS_THROTTLE_CFG 110
-#define SC7180_SLAVE_VSENSE_CTRL_CFG 111
-#define SC7180_SLAVE_A1NOC_SNOC 112
-#define SC7180_SLAVE_A2NOC_SNOC 113
-#define SC7180_SLAVE_CAMNOC_UNCOMP 114
-#define SC7180_SLAVE_CDSP_GEM_NOC 115
-#define SC7180_SLAVE_SNOC_CNOC 116
-#define SC7180_SLAVE_GEM_NOC_SNOC 117
-#define SC7180_SLAVE_SNOC_GEM_NOC_GC 118
-#define SC7180_SLAVE_SNOC_GEM_NOC_SF 119
-#define SC7180_SLAVE_LLCC 120
-#define SC7180_SLAVE_MNOC_HF_MEM_NOC 121
-#define SC7180_SLAVE_MNOC_SF_MEM_NOC 122
-#define SC7180_SLAVE_NPU_COMPUTE_NOC 123
-#define SC7180_SLAVE_QUP_CORE_0 124
-#define SC7180_SLAVE_QUP_CORE_1 125
-#define SC7180_SLAVE_IMEM 126
-#define SC7180_SLAVE_PIMEM 127
-#define SC7180_SLAVE_SERVICE_A1NOC 128
-#define SC7180_SLAVE_SERVICE_A2NOC 129
-#define SC7180_SLAVE_SERVICE_CNOC 130
-#define SC7180_SLAVE_SERVICE_GEM_NOC 131
-#define SC7180_SLAVE_SERVICE_MNOC 132
-#define SC7180_SLAVE_SERVICE_NPU_NOC 133
-#define SC7180_SLAVE_SERVICE_SNOC 134
-#define SC7180_SLAVE_QDSS_STM 135
-#define SC7180_SLAVE_TCU 136
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 16/28] interconnect: qcom: sdm670: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (14 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 15/28] interconnect: qcom: sc7180: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 17/28] interconnect: qcom: sdx55: " Dmitry Baryshkov
` (12 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sdm670.c | 646 ++++++++++++++++++-------------------
drivers/interconnect/qcom/sdm670.h | 128 --------
2 files changed, 311 insertions(+), 463 deletions(-)
diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c
index 7a61e2472319b0f6a2a3dee5df014640345e3e79..d1aa6e3532821659d06373c4082cc6bd77e420ab 100644
--- a/drivers/interconnect/qcom/sdm670.c
+++ b/drivers/interconnect/qcom/sdm670.c
@@ -13,1036 +13,1004 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sdm670.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qhm_tsif;
+static struct qcom_icc_node xm_emmc;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node qhm_a2noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qnm_cnoc;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node qxm_camnoc_hf1_uncomp;
+static struct qcom_icc_node qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node qhm_spdm;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node qhm_cnoc;
+static struct qcom_icc_node acm_l3;
+static struct qcom_icc_node pm_gnoc_cfg;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node acm_tcu;
+static struct qcom_icc_node qhm_memnoc_cfg;
+static struct qcom_icc_node qnm_apps;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_gpu;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qxm_camnoc_hf0;
+static struct qcom_icc_node qxm_camnoc_hf1;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_mdp1;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node qxm_venus0;
+static struct qcom_icc_node qxm_venus1;
+static struct qcom_icc_node qxm_venus_arm9;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gladiator_sodv;
+static struct qcom_icc_node qnm_memnoc;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_camnoc_uncomp;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_a2_noc_cfg;
+static struct qcom_icc_node qhs_aop;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_dsp_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_emmc_cfg;
+static struct qcom_icc_node qhs_glm;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_phy_refgen_south;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qupv3_north;
+static struct qcom_icc_node qhs_qupv3_south;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_spdm;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm_north;
+static struct qcom_icc_node qhs_tlmm_south;
+static struct qcom_icc_node qhs_tsif;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_memnoc;
+static struct qcom_icc_node qns_gladiator_sodv;
+static struct qcom_icc_node qns_gnoc_memnoc;
+static struct qcom_icc_node srvc_gnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qns_apps_io;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_memnoc_snoc;
+static struct qcom_icc_node srvc_memnoc;
+static struct qcom_icc_node qns2_mem_noc;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_memnoc_gc;
+static struct qcom_icc_node qns_memnoc_sf;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qhm_a1noc_cfg = {
.name = "qhm_a1noc_cfg",
- .id = SDM670_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SDM670_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_tsif = {
.name = "qhm_tsif",
- .id = SDM670_MASTER_TSIF,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emmc = {
.name = "xm_emmc",
- .id = SDM670_MASTER_EMMC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SDM670_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SDM670_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SDM670_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_a2noc_cfg = {
.name = "qhm_a2noc_cfg",
- .id = SDM670_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SDM670_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SDM670_MASTER_BLSP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
- .id = SDM670_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SDM670_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SDM670_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SDM670_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SDM670_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
.name = "qxm_camnoc_hf0_uncomp",
- .id = SDM670_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
.name = "qxm_camnoc_hf1_uncomp",
- .id = SDM670_MASTER_CAMNOC_HF1_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
.name = "qxm_camnoc_sf_uncomp",
- .id = SDM670_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qhm_spdm = {
.name = "qhm_spdm",
- .id = SDM670_MASTER_SPDM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_CNOC_A2NOC },
+ .link_nodes = { &qns_cnoc_a2noc, NULL },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = SDM670_MASTER_SNOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 38,
- .links = { SDM670_SLAVE_TLMM_SOUTH,
- SDM670_SLAVE_CAMERA_CFG,
- SDM670_SLAVE_SDCC_4,
- SDM670_SLAVE_SDCC_2,
- SDM670_SLAVE_CNOC_MNOC_CFG,
- SDM670_SLAVE_UFS_MEM_CFG,
- SDM670_SLAVE_GLM,
- SDM670_SLAVE_PDM,
- SDM670_SLAVE_A2NOC_CFG,
- SDM670_SLAVE_QDSS_CFG,
- SDM670_SLAVE_DISPLAY_CFG,
- SDM670_SLAVE_TCSR,
- SDM670_SLAVE_DCC_CFG,
- SDM670_SLAVE_CNOC_DDRSS,
- SDM670_SLAVE_SNOC_CFG,
- SDM670_SLAVE_SOUTH_PHY_CFG,
- SDM670_SLAVE_GRAPHICS_3D_CFG,
- SDM670_SLAVE_VENUS_CFG,
- SDM670_SLAVE_TSIF,
- SDM670_SLAVE_CDSP_CFG,
- SDM670_SLAVE_AOP,
- SDM670_SLAVE_BLSP_2,
- SDM670_SLAVE_SERVICE_CNOC,
- SDM670_SLAVE_USB3,
- SDM670_SLAVE_IPA_CFG,
- SDM670_SLAVE_RBCPR_CX_CFG,
- SDM670_SLAVE_A1NOC_CFG,
- SDM670_SLAVE_AOSS,
- SDM670_SLAVE_PRNG,
- SDM670_SLAVE_VSENSE_CTRL_CFG,
- SDM670_SLAVE_EMMC_CFG,
- SDM670_SLAVE_BLSP_1,
- SDM670_SLAVE_SPDM_WRAPPER,
- SDM670_SLAVE_CRYPTO_0_CFG,
- SDM670_SLAVE_PIMEM_CFG,
- SDM670_SLAVE_TLMM_NORTH,
- SDM670_SLAVE_CLK_CTL,
- SDM670_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_tlmm_south,
+ &qhs_camera_cfg,
+ &qhs_sdc4,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_glm,
+ &qhs_pdm,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_display_cfg,
+ &qhs_tcsr,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_snoc_cfg,
+ &qhs_phy_refgen_south,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_compute_dsp_cfg,
+ &qhs_aop,
+ &qhs_qupv3_north,
+ &srvc_cnoc,
+ &qhs_usb3_0,
+ &qhs_ipa,
+ &qhs_cpr_cx,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_emmc_cfg,
+ &qhs_qupv3_south,
+ &qhs_spdm,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_tlmm_north,
+ &qhs_clk_ctl,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node qhm_cnoc = {
.name = "qhm_cnoc",
- .id = SDM670_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SDM670_SLAVE_MEM_NOC_CFG,
- SDM670_SLAVE_LLCC_CFG
- },
+ .link_nodes = { &qhs_memnoc,
+ &qhs_llcc, NULL },
};
static struct qcom_icc_node acm_l3 = {
.name = "acm_l3",
- .id = SDM670_MASTER_AMPSS_M0,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SDM670_SLAVE_SERVICE_GNOC,
- SDM670_SLAVE_GNOC_SNOC,
- SDM670_SLAVE_GNOC_MEM_NOC
- },
+ .link_nodes = { &srvc_gnoc,
+ &qns_gladiator_sodv,
+ &qns_gnoc_memnoc, NULL },
};
static struct qcom_icc_node pm_gnoc_cfg = {
.name = "pm_gnoc_cfg",
- .id = SDM670_MASTER_GNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_SERVICE_GNOC },
+ .link_nodes = { &srvc_gnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SDM670_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_EBI_CH0 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
- .id = SDM670_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
- .num_links = 3,
- .links = { SDM670_SLAVE_MEM_NOC_GNOC,
- SDM670_SLAVE_LLCC,
- SDM670_SLAVE_MEM_NOC_SNOC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc,
+ &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_node qhm_memnoc_cfg = {
.name = "qhm_memnoc_cfg",
- .id = SDM670_MASTER_MEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SDM670_SLAVE_SERVICE_MEM_NOC,
- SDM670_SLAVE_MSS_PROC_MS_MPU_CFG
- },
+ .link_nodes = { &srvc_memnoc,
+ &qhs_mdsp_ms_mpu_cfg, NULL },
};
static struct qcom_icc_node qnm_apps = {
.name = "qnm_apps",
- .id = SDM670_MASTER_GNOC_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SDM670_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SDM670_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 3,
- .links = { SDM670_SLAVE_MEM_NOC_GNOC,
- SDM670_SLAVE_LLCC,
- SDM670_SLAVE_MEM_NOC_SNOC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc,
+ &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SDM670_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SDM670_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SDM670_SLAVE_MEM_NOC_GNOC,
- SDM670_SLAVE_LLCC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qxm_gpu = {
.name = "qxm_gpu",
- .id = SDM670_MASTER_GRAPHICS_3D,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SDM670_SLAVE_MEM_NOC_GNOC,
- SDM670_SLAVE_LLCC,
- SDM670_SLAVE_MEM_NOC_SNOC
- },
+ .link_nodes = { &qns_apps_io,
+ &qns_llcc,
+ &qns_memnoc_snoc, NULL },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = SDM670_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0 = {
.name = "qxm_camnoc_hf0",
- .id = SDM670_MASTER_CAMNOC_HF0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1 = {
.name = "qxm_camnoc_hf1",
- .id = SDM670_MASTER_CAMNOC_HF1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SDM670_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SDM670_MASTER_MDP_PORT0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_mdp1 = {
.name = "qxm_mdp1",
- .id = SDM670_MASTER_MDP_PORT1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = SDM670_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus0 = {
.name = "qxm_venus0",
- .id = SDM670_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus1 = {
.name = "qxm_venus1",
- .id = SDM670_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus_arm9 = {
.name = "qxm_venus_arm9",
- .id = SDM670_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SDM670_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SDM670_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SDM670_SLAVE_PIMEM,
- SDM670_SLAVE_SNOC_MEM_NOC_SF,
- SDM670_SLAVE_OCIMEM,
- SDM670_SLAVE_APPSS,
- SDM670_SLAVE_SNOC_CNOC,
- SDM670_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_pimem,
+ &qns_memnoc_sf,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SDM670_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 7,
- .links = { SDM670_SLAVE_PIMEM,
- SDM670_SLAVE_SNOC_MEM_NOC_SF,
- SDM670_SLAVE_OCIMEM,
- SDM670_SLAVE_APPSS,
- SDM670_SLAVE_SNOC_CNOC,
- SDM670_SLAVE_TCU,
- SDM670_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_pimem,
+ &qns_memnoc_sf,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_gladiator_sodv = {
.name = "qnm_gladiator_sodv",
- .id = SDM670_MASTER_GNOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 6,
- .links = { SDM670_SLAVE_PIMEM,
- SDM670_SLAVE_OCIMEM,
- SDM670_SLAVE_APPSS,
- SDM670_SLAVE_SNOC_CNOC,
- SDM670_SLAVE_TCU,
- SDM670_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_memnoc = {
.name = "qnm_memnoc",
- .id = SDM670_MASTER_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 5,
- .links = { SDM670_SLAVE_OCIMEM,
- SDM670_SLAVE_APPSS,
- SDM670_SLAVE_PIMEM,
- SDM670_SLAVE_SNOC_CNOC,
- SDM670_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_imem,
+ &qhs_apss,
+ &qxs_pimem,
+ &qns_cnoc,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SDM670_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SDM670_SLAVE_OCIMEM,
- SDM670_SLAVE_SNOC_MEM_NOC_GC
- },
+ .link_nodes = { &qxs_imem,
+ &qns_memnoc_gc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SDM670_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SDM670_SLAVE_OCIMEM,
- SDM670_SLAVE_SNOC_MEM_NOC_GC
- },
+ .link_nodes = { &qxs_imem,
+ &qns_memnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SDM670_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM670_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SDM670_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SDM670_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM670_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SDM670_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_camnoc_uncomp = {
.name = "qns_camnoc_uncomp",
- .id = SDM670_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = SDM670_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qhs_a2_noc_cfg = {
.name = "qhs_a2_noc_cfg",
- .id = SDM670_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_MASTER_A2NOC_CFG },
+ .link_nodes = { &qhm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
- .id = SDM670_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SDM670_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SDM670_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SDM670_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_dsp_cfg = {
.name = "qhs_compute_dsp_cfg",
- .id = SDM670_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SDM670_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SDM670_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SDM670_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc, NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SDM670_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SDM670_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emmc_cfg = {
.name = "qhs_emmc_cfg",
- .id = SDM670_SLAVE_EMMC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_glm = {
.name = "qhs_glm",
- .id = SDM670_SLAVE_GLM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SDM670_SLAVE_GRAPHICS_3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SDM670_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SDM670_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = SDM670_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SDM670_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_phy_refgen_south = {
.name = "qhs_phy_refgen_south",
- .id = SDM670_SLAVE_SOUTH_PHY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SDM670_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SDM670_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SDM670_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_north = {
.name = "qhs_qupv3_north",
- .id = SDM670_SLAVE_BLSP_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_south = {
.name = "qhs_qupv3_south",
- .id = SDM670_SLAVE_BLSP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SDM670_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SDM670_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SDM670_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_spdm = {
.name = "qhs_spdm",
- .id = SDM670_SLAVE_SPDM_WRAPPER,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SDM670_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_north = {
.name = "qhs_tlmm_north",
- .id = SDM670_SLAVE_TLMM_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_south = {
.name = "qhs_tlmm_south",
- .id = SDM670_SLAVE_TLMM_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tsif = {
.name = "qhs_tsif",
- .id = SDM670_SLAVE_TSIF,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SDM670_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SDM670_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SDM670_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SDM670_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = SDM670_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc, NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SDM670_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SDM670_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_memnoc = {
.name = "qhs_memnoc",
- .id = SDM670_SLAVE_MEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDM670_MASTER_MEM_NOC_CFG },
+ .link_nodes = { &qhm_memnoc_cfg, NULL },
};
static struct qcom_icc_node qns_gladiator_sodv = {
.name = "qns_gladiator_sodv",
- .id = SDM670_SLAVE_GNOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_MASTER_GNOC_SNOC },
+ .link_nodes = { &qnm_gladiator_sodv, NULL },
};
static struct qcom_icc_node qns_gnoc_memnoc = {
.name = "qns_gnoc_memnoc",
- .id = SDM670_SLAVE_GNOC_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_MASTER_GNOC_MEM_NOC },
+ .link_nodes = { &qnm_apps, NULL },
};
static struct qcom_icc_node srvc_gnoc = {
.name = "srvc_gnoc",
- .id = SDM670_SLAVE_SERVICE_GNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SDM670_SLAVE_EBI_CH0,
.channels = 2,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SDM670_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_apps_io = {
.name = "qns_apps_io",
- .id = SDM670_SLAVE_MEM_NOC_GNOC,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SDM670_SLAVE_LLCC,
.channels = 2,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM670_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_memnoc_snoc = {
.name = "qns_memnoc_snoc",
- .id = SDM670_SLAVE_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_MASTER_MEM_NOC_SNOC },
+ .link_nodes = { &qnm_memnoc, NULL },
};
static struct qcom_icc_node srvc_memnoc = {
.name = "srvc_memnoc",
- .id = SDM670_SLAVE_SERVICE_MEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns2_mem_noc = {
.name = "qns2_mem_noc",
- .id = SDM670_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SDM670_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SDM670_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SDM670_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SDM670_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = SDM670_SLAVE_SNOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_MASTER_SNOC_CNOC },
+ .link_nodes = { &qnm_snoc, NULL },
};
static struct qcom_icc_node qns_memnoc_gc = {
.name = "qns_memnoc_gc",
- .id = SDM670_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDM670_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_memnoc_sf = {
.name = "qns_memnoc_sf",
- .id = SDM670_SLAVE_SNOC_MEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDM670_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SDM670_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SDM670_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SDM670_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SDM670_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SDM670_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1254,6 +1222,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1280,6 +1249,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1335,6 +1305,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1351,6 +1322,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1369,6 +1341,7 @@ static struct qcom_icc_node * const gladiator_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_gladiator_noc = {
+ .alloc_dyn_id = true,
.nodes = gladiator_noc_nodes,
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
.bcms = gladiator_noc_bcms,
@@ -1404,6 +1377,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_mem_noc = {
+ .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
@@ -1434,6 +1408,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1478,6 +1453,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdm670.h b/drivers/interconnect/qcom/sdm670.h
deleted file mode 100644
index 14155f244c43e87c98037f35f895913666f66a41..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sdm670.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm #define SDM670 interconnect IDs
- *
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H
-#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H
-
-#define SDM670_MASTER_A1NOC_CFG 0
-#define SDM670_MASTER_A1NOC_SNOC 1
-#define SDM670_MASTER_A2NOC_CFG 2
-#define SDM670_MASTER_A2NOC_SNOC 3
-#define SDM670_MASTER_AMPSS_M0 4
-#define SDM670_MASTER_BLSP_1 5
-#define SDM670_MASTER_BLSP_2 6
-#define SDM670_MASTER_CAMNOC_HF0 7
-#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8
-#define SDM670_MASTER_CAMNOC_HF1 9
-#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10
-#define SDM670_MASTER_CAMNOC_SF 11
-#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12
-#define SDM670_MASTER_CNOC_A2NOC 13
-#define SDM670_MASTER_CNOC_DC_NOC 14
-#define SDM670_MASTER_CNOC_MNOC_CFG 15
-#define SDM670_MASTER_CRYPTO_CORE_0 16
-#define SDM670_MASTER_EMMC 17
-#define SDM670_MASTER_GIC 18
-#define SDM670_MASTER_GNOC_CFG 19
-#define SDM670_MASTER_GNOC_MEM_NOC 20
-#define SDM670_MASTER_GNOC_SNOC 21
-#define SDM670_MASTER_GRAPHICS_3D 22
-#define SDM670_MASTER_IPA 23
-#define SDM670_MASTER_LLCC 24
-#define SDM670_MASTER_MDP_PORT0 25
-#define SDM670_MASTER_MDP_PORT1 26
-#define SDM670_MASTER_MEM_NOC_CFG 27
-#define SDM670_MASTER_MEM_NOC_SNOC 28
-#define SDM670_MASTER_MNOC_HF_MEM_NOC 29
-#define SDM670_MASTER_MNOC_SF_MEM_NOC 30
-#define SDM670_MASTER_PIMEM 31
-#define SDM670_MASTER_QDSS_BAM 32
-#define SDM670_MASTER_QDSS_ETR 33
-#define SDM670_MASTER_ROTATOR 34
-#define SDM670_MASTER_SDCC_2 35
-#define SDM670_MASTER_SDCC_4 36
-#define SDM670_MASTER_SNOC_CFG 37
-#define SDM670_MASTER_SNOC_CNOC 38
-#define SDM670_MASTER_SNOC_GC_MEM_NOC 39
-#define SDM670_MASTER_SNOC_SF_MEM_NOC 40
-#define SDM670_MASTER_SPDM 41
-#define SDM670_MASTER_TCU_0 42
-#define SDM670_MASTER_TSIF 43
-#define SDM670_MASTER_UFS_MEM 44
-#define SDM670_MASTER_USB3 45
-#define SDM670_MASTER_VIDEO_P0 46
-#define SDM670_MASTER_VIDEO_P1 47
-#define SDM670_MASTER_VIDEO_PROC 48
-#define SDM670_SLAVE_A1NOC_CFG 49
-#define SDM670_SLAVE_A1NOC_SNOC 50
-#define SDM670_SLAVE_A2NOC_CFG 51
-#define SDM670_SLAVE_A2NOC_SNOC 52
-#define SDM670_SLAVE_AOP 53
-#define SDM670_SLAVE_AOSS 54
-#define SDM670_SLAVE_APPSS 55
-#define SDM670_SLAVE_BLSP_1 56
-#define SDM670_SLAVE_BLSP_2 57
-#define SDM670_SLAVE_CAMERA_CFG 58
-#define SDM670_SLAVE_CAMNOC_UNCOMP 59
-#define SDM670_SLAVE_CDSP_CFG 60
-#define SDM670_SLAVE_CLK_CTL 61
-#define SDM670_SLAVE_CNOC_A2NOC 62
-#define SDM670_SLAVE_CNOC_DDRSS 63
-#define SDM670_SLAVE_CNOC_MNOC_CFG 64
-#define SDM670_SLAVE_CRYPTO_0_CFG 65
-#define SDM670_SLAVE_DCC_CFG 66
-#define SDM670_SLAVE_DISPLAY_CFG 67
-#define SDM670_SLAVE_EBI_CH0 68
-#define SDM670_SLAVE_EMMC_CFG 69
-#define SDM670_SLAVE_GLM 70
-#define SDM670_SLAVE_GNOC_MEM_NOC 71
-#define SDM670_SLAVE_GNOC_SNOC 72
-#define SDM670_SLAVE_GRAPHICS_3D_CFG 73
-#define SDM670_SLAVE_IMEM_CFG 74
-#define SDM670_SLAVE_IPA_CFG 75
-#define SDM670_SLAVE_LLCC 76
-#define SDM670_SLAVE_LLCC_CFG 77
-#define SDM670_SLAVE_MEM_NOC_CFG 78
-#define SDM670_SLAVE_MEM_NOC_GNOC 79
-#define SDM670_SLAVE_MEM_NOC_SNOC 80
-#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81
-#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82
-#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83
-#define SDM670_SLAVE_OCIMEM 84
-#define SDM670_SLAVE_PDM 85
-#define SDM670_SLAVE_PIMEM 86
-#define SDM670_SLAVE_PIMEM_CFG 87
-#define SDM670_SLAVE_PRNG 88
-#define SDM670_SLAVE_QDSS_CFG 89
-#define SDM670_SLAVE_QDSS_STM 90
-#define SDM670_SLAVE_RBCPR_CX_CFG 91
-#define SDM670_SLAVE_SDCC_2 92
-#define SDM670_SLAVE_SDCC_4 93
-#define SDM670_SLAVE_SERVICE_A1NOC 94
-#define SDM670_SLAVE_SERVICE_A2NOC 95
-#define SDM670_SLAVE_SERVICE_CNOC 96
-#define SDM670_SLAVE_SERVICE_GNOC 97
-#define SDM670_SLAVE_SERVICE_MEM_NOC 98
-#define SDM670_SLAVE_SERVICE_MNOC 99
-#define SDM670_SLAVE_SERVICE_SNOC 100
-#define SDM670_SLAVE_SNOC_CFG 101
-#define SDM670_SLAVE_SNOC_CNOC 102
-#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103
-#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104
-#define SDM670_SLAVE_SOUTH_PHY_CFG 105
-#define SDM670_SLAVE_SPDM_WRAPPER 106
-#define SDM670_SLAVE_TCSR 107
-#define SDM670_SLAVE_TCU 108
-#define SDM670_SLAVE_TLMM_NORTH 109
-#define SDM670_SLAVE_TLMM_SOUTH 110
-#define SDM670_SLAVE_TSIF 111
-#define SDM670_SLAVE_UFS_MEM_CFG 112
-#define SDM670_SLAVE_USB3 113
-#define SDM670_SLAVE_VENUS_CFG 114
-#define SDM670_SLAVE_VSENSE_CTRL_CFG 115
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 17/28] interconnect: qcom: sdx55: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (15 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 16/28] interconnect: qcom: sdm670: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 18/28] interconnect: qcom: sdx65: " Dmitry Baryshkov
` (11 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sdx55.c | 554 +++++++++++++++++++-------------------
drivers/interconnect/qcom/sdx55.h | 70 -----
2 files changed, 275 insertions(+), 349 deletions(-)
diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c
index af273e39eef3e90519635d1c310dc108a9f8b708..5d85c1e6ec58d3949b30c143440bb6dd0779a605 100644
--- a/drivers/interconnect/qcom/sdx55.c
+++ b/drivers/interconnect/qcom/sdx55.c
@@ -17,630 +17,623 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sdx55.h"
+
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node acm_tcu;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node xm_apps_rdwr;
+static struct qcom_icc_node qhm_audio;
+static struct qcom_icc_node qhm_blsp1;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qpic;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qhm_spmi_fetcher1;
+static struct qcom_icc_node qnm_aggre_noc;
+static struct qcom_icc_node qnm_ipa;
+static struct qcom_icc_node qnm_memnoc;
+static struct qcom_icc_node qnm_memnoc_pcie;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node xm_emac;
+static struct qcom_icc_node xm_ipa2pcie_slv;
+static struct qcom_icc_node xm_pcie;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_usb3;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_memnoc_snoc;
+static struct qcom_icc_node qns_sys_pcie;
+static struct qcom_icc_node qhs_aop;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qhs_audio;
+static struct qcom_icc_node qhs_blsp1;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_ecc_cfg;
+static struct qcom_icc_node qhs_emac_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_pcie_parf;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qpic;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_spmi_fetcher;
+static struct qcom_icc_node qhs_spmi_vgi_coex;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_usb3;
+static struct qcom_icc_node qhs_usb3_phy;
+static struct qcom_icc_node qns_aggre_noc;
+static struct qcom_icc_node qns_snoc_memnoc;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_pcie;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SDX55_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX55_SLAVE_EBI_CH0 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
- .id = SDX55_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
- .num_links = 3,
- .links = { SDX55_SLAVE_LLCC,
- SDX55_SLAVE_MEM_NOC_SNOC,
- SDX55_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_memnoc_snoc,
+ &qns_sys_pcie, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SDX55_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node xm_apps_rdwr = {
.name = "xm_apps_rdwr",
- .id = SDX55_MASTER_AMPSS_M0,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SDX55_SLAVE_LLCC,
- SDX55_SLAVE_MEM_NOC_SNOC,
- SDX55_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_memnoc_snoc,
+ &qns_sys_pcie, NULL },
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
- .id = SDX55_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX55_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node qhm_blsp1 = {
.name = "qhm_blsp1",
- .id = SDX55_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX55_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SDX55_MASTER_QDSS_BAM,
- .channels = 1,
- .buswidth = 4,
- .num_links = 28,
- .links = { SDX55_SLAVE_SNOC_CFG,
- SDX55_SLAVE_EMAC_CFG,
- SDX55_SLAVE_USB3,
- SDX55_SLAVE_TLMM,
- SDX55_SLAVE_SPMI_FETCHER,
- SDX55_SLAVE_QDSS_CFG,
- SDX55_SLAVE_PDM,
- SDX55_SLAVE_SNOC_MEM_NOC_GC,
- SDX55_SLAVE_TCSR,
- SDX55_SLAVE_CNOC_DDRSS,
- SDX55_SLAVE_SPMI_VGI_COEX,
- SDX55_SLAVE_QPIC,
- SDX55_SLAVE_OCIMEM,
- SDX55_SLAVE_IPA_CFG,
- SDX55_SLAVE_USB3_PHY_CFG,
- SDX55_SLAVE_AOP,
- SDX55_SLAVE_BLSP_1,
- SDX55_SLAVE_SDCC_1,
- SDX55_SLAVE_CNOC_MSS,
- SDX55_SLAVE_PCIE_PARF,
- SDX55_SLAVE_ECC_CFG,
- SDX55_SLAVE_AUDIO,
- SDX55_SLAVE_AOSS,
- SDX55_SLAVE_PRNG,
- SDX55_SLAVE_CRYPTO_0_CFG,
- SDX55_SLAVE_TCU,
- SDX55_SLAVE_CLK_CTL,
- SDX55_SLAVE_IMEM_CFG
- },
+ .channels = 1,
+ .buswidth = 4,
+ .link_nodes = { &qhs_snoc_cfg,
+ &qhs_emac_cfg,
+ &qhs_usb3,
+ &qhs_tlmm,
+ &qhs_spmi_fetcher,
+ &qhs_qdss_cfg,
+ &qhs_pdm,
+ &qns_snoc_memnoc,
+ &qhs_tcsr,
+ &qhs_ddrss_cfg,
+ &qhs_spmi_vgi_coex,
+ &qhs_qpic,
+ &qxs_imem,
+ &qhs_ipa,
+ &qhs_usb3_phy,
+ &qhs_aop,
+ &qhs_blsp1,
+ &qhs_sdc1,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_ecc_cfg,
+ &qhs_audio,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_crypto0_cfg,
+ &xs_sys_tcu_cfg,
+ &qhs_clk_ctl,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
- .id = SDX55_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
- .num_links = 5,
- .links = { SDX55_SLAVE_AOSS,
- SDX55_SLAVE_IPA_CFG,
- SDX55_SLAVE_ANOC_SNOC,
- SDX55_SLAVE_AOP,
- SDX55_SLAVE_AUDIO
- },
+ .link_nodes = { &qhs_aoss,
+ &qhs_ipa,
+ &qns_aggre_noc,
+ &qhs_aop,
+ &qhs_audio, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SDX55_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX55_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qhm_spmi_fetcher1 = {
.name = "qhm_spmi_fetcher1",
- .id = SDX55_MASTER_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
- .num_links = 3,
- .links = { SDX55_SLAVE_AOSS,
- SDX55_SLAVE_ANOC_SNOC,
- SDX55_SLAVE_AOP
- },
+ .link_nodes = { &qhs_aoss,
+ &qns_aggre_noc,
+ &qhs_aop, NULL },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
- .id = SDX55_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 30,
- .links = { SDX55_SLAVE_PCIE_0,
- SDX55_SLAVE_SNOC_CFG,
- SDX55_SLAVE_SDCC_1,
- SDX55_SLAVE_TLMM,
- SDX55_SLAVE_SPMI_FETCHER,
- SDX55_SLAVE_QDSS_CFG,
- SDX55_SLAVE_PDM,
- SDX55_SLAVE_SNOC_MEM_NOC_GC,
- SDX55_SLAVE_TCSR,
- SDX55_SLAVE_CNOC_DDRSS,
- SDX55_SLAVE_SPMI_VGI_COEX,
- SDX55_SLAVE_QDSS_STM,
- SDX55_SLAVE_QPIC,
- SDX55_SLAVE_OCIMEM,
- SDX55_SLAVE_IPA_CFG,
- SDX55_SLAVE_USB3_PHY_CFG,
- SDX55_SLAVE_AOP,
- SDX55_SLAVE_BLSP_1,
- SDX55_SLAVE_USB3,
- SDX55_SLAVE_CNOC_MSS,
- SDX55_SLAVE_PCIE_PARF,
- SDX55_SLAVE_ECC_CFG,
- SDX55_SLAVE_APPSS,
- SDX55_SLAVE_AUDIO,
- SDX55_SLAVE_AOSS,
- SDX55_SLAVE_PRNG,
- SDX55_SLAVE_CRYPTO_0_CFG,
- SDX55_SLAVE_TCU,
- SDX55_SLAVE_CLK_CTL,
- SDX55_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &xs_pcie,
+ &qhs_snoc_cfg,
+ &qhs_sdc1,
+ &qhs_tlmm,
+ &qhs_spmi_fetcher,
+ &qhs_qdss_cfg,
+ &qhs_pdm,
+ &qns_snoc_memnoc,
+ &qhs_tcsr,
+ &qhs_ddrss_cfg,
+ &qhs_spmi_vgi_coex,
+ &xs_qdss_stm,
+ &qhs_qpic,
+ &qxs_imem,
+ &qhs_ipa,
+ &qhs_usb3_phy,
+ &qhs_aop,
+ &qhs_blsp1,
+ &qhs_usb3,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_ecc_cfg,
+ &qhs_apss,
+ &qhs_audio,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_crypto0_cfg,
+ &xs_sys_tcu_cfg,
+ &qhs_clk_ctl,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node qnm_ipa = {
.name = "qnm_ipa",
- .id = SDX55_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 27,
- .links = { SDX55_SLAVE_SNOC_CFG,
- SDX55_SLAVE_EMAC_CFG,
- SDX55_SLAVE_USB3,
- SDX55_SLAVE_AOSS,
- SDX55_SLAVE_SPMI_FETCHER,
- SDX55_SLAVE_QDSS_CFG,
- SDX55_SLAVE_PDM,
- SDX55_SLAVE_SNOC_MEM_NOC_GC,
- SDX55_SLAVE_TCSR,
- SDX55_SLAVE_CNOC_DDRSS,
- SDX55_SLAVE_QDSS_STM,
- SDX55_SLAVE_QPIC,
- SDX55_SLAVE_OCIMEM,
- SDX55_SLAVE_IPA_CFG,
- SDX55_SLAVE_USB3_PHY_CFG,
- SDX55_SLAVE_AOP,
- SDX55_SLAVE_BLSP_1,
- SDX55_SLAVE_SDCC_1,
- SDX55_SLAVE_CNOC_MSS,
- SDX55_SLAVE_PCIE_PARF,
- SDX55_SLAVE_ECC_CFG,
- SDX55_SLAVE_AUDIO,
- SDX55_SLAVE_TLMM,
- SDX55_SLAVE_PRNG,
- SDX55_SLAVE_CRYPTO_0_CFG,
- SDX55_SLAVE_CLK_CTL,
- SDX55_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_snoc_cfg,
+ &qhs_emac_cfg,
+ &qhs_usb3,
+ &qhs_aoss,
+ &qhs_spmi_fetcher,
+ &qhs_qdss_cfg,
+ &qhs_pdm,
+ &qns_snoc_memnoc,
+ &qhs_tcsr,
+ &qhs_ddrss_cfg,
+ &xs_qdss_stm,
+ &qhs_qpic,
+ &qxs_imem,
+ &qhs_ipa,
+ &qhs_usb3_phy,
+ &qhs_aop,
+ &qhs_blsp1,
+ &qhs_sdc1,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_ecc_cfg,
+ &qhs_audio,
+ &qhs_tlmm,
+ &qhs_prng,
+ &qhs_crypto0_cfg,
+ &qhs_clk_ctl,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node qnm_memnoc = {
.name = "qnm_memnoc",
- .id = SDX55_MASTER_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 29,
- .links = { SDX55_SLAVE_SNOC_CFG,
- SDX55_SLAVE_EMAC_CFG,
- SDX55_SLAVE_USB3,
- SDX55_SLAVE_TLMM,
- SDX55_SLAVE_SPMI_FETCHER,
- SDX55_SLAVE_QDSS_CFG,
- SDX55_SLAVE_PDM,
- SDX55_SLAVE_TCSR,
- SDX55_SLAVE_CNOC_DDRSS,
- SDX55_SLAVE_SPMI_VGI_COEX,
- SDX55_SLAVE_QDSS_STM,
- SDX55_SLAVE_QPIC,
- SDX55_SLAVE_OCIMEM,
- SDX55_SLAVE_IPA_CFG,
- SDX55_SLAVE_USB3_PHY_CFG,
- SDX55_SLAVE_AOP,
- SDX55_SLAVE_BLSP_1,
- SDX55_SLAVE_SDCC_1,
- SDX55_SLAVE_CNOC_MSS,
- SDX55_SLAVE_PCIE_PARF,
- SDX55_SLAVE_ECC_CFG,
- SDX55_SLAVE_APPSS,
- SDX55_SLAVE_AUDIO,
- SDX55_SLAVE_AOSS,
- SDX55_SLAVE_PRNG,
- SDX55_SLAVE_CRYPTO_0_CFG,
- SDX55_SLAVE_TCU,
- SDX55_SLAVE_CLK_CTL,
- SDX55_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_snoc_cfg,
+ &qhs_emac_cfg,
+ &qhs_usb3,
+ &qhs_tlmm,
+ &qhs_spmi_fetcher,
+ &qhs_qdss_cfg,
+ &qhs_pdm,
+ &qhs_tcsr,
+ &qhs_ddrss_cfg,
+ &qhs_spmi_vgi_coex,
+ &xs_qdss_stm,
+ &qhs_qpic,
+ &qxs_imem,
+ &qhs_ipa,
+ &qhs_usb3_phy,
+ &qhs_aop,
+ &qhs_blsp1,
+ &qhs_sdc1,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_ecc_cfg,
+ &qhs_apss,
+ &qhs_audio,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_crypto0_cfg,
+ &xs_sys_tcu_cfg,
+ &qhs_clk_ctl,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node qnm_memnoc_pcie = {
.name = "qnm_memnoc_pcie",
- .id = SDX55_MASTER_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_SLAVE_PCIE_0 },
+ .link_nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SDX55_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 3,
- .links = { SDX55_SLAVE_AOSS,
- SDX55_SLAVE_ANOC_SNOC,
- SDX55_SLAVE_AOP
- },
+ .link_nodes = { &qhs_aoss,
+ &qns_aggre_noc,
+ &qhs_aop, NULL },
};
static struct qcom_icc_node xm_emac = {
.name = "xm_emac",
- .id = SDX55_MASTER_EMAC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node xm_ipa2pcie_slv = {
.name = "xm_ipa2pcie_slv",
- .id = SDX55_MASTER_IPA_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_SLAVE_PCIE_0 },
+ .link_nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
- .id = SDX55_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SDX55_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 28,
- .links = { SDX55_SLAVE_SNOC_CFG,
- SDX55_SLAVE_EMAC_CFG,
- SDX55_SLAVE_USB3,
- SDX55_SLAVE_AOSS,
- SDX55_SLAVE_SPMI_FETCHER,
- SDX55_SLAVE_QDSS_CFG,
- SDX55_SLAVE_PDM,
- SDX55_SLAVE_SNOC_MEM_NOC_GC,
- SDX55_SLAVE_TCSR,
- SDX55_SLAVE_CNOC_DDRSS,
- SDX55_SLAVE_SPMI_VGI_COEX,
- SDX55_SLAVE_QPIC,
- SDX55_SLAVE_OCIMEM,
- SDX55_SLAVE_IPA_CFG,
- SDX55_SLAVE_USB3_PHY_CFG,
- SDX55_SLAVE_AOP,
- SDX55_SLAVE_BLSP_1,
- SDX55_SLAVE_SDCC_1,
- SDX55_SLAVE_CNOC_MSS,
- SDX55_SLAVE_PCIE_PARF,
- SDX55_SLAVE_ECC_CFG,
- SDX55_SLAVE_AUDIO,
- SDX55_SLAVE_AOSS,
- SDX55_SLAVE_PRNG,
- SDX55_SLAVE_CRYPTO_0_CFG,
- SDX55_SLAVE_TCU,
- SDX55_SLAVE_CLK_CTL,
- SDX55_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_snoc_cfg,
+ &qhs_emac_cfg,
+ &qhs_usb3,
+ &qhs_aoss,
+ &qhs_spmi_fetcher,
+ &qhs_qdss_cfg,
+ &qhs_pdm,
+ &qns_snoc_memnoc,
+ &qhs_tcsr,
+ &qhs_ddrss_cfg,
+ &qhs_spmi_vgi_coex,
+ &qhs_qpic,
+ &qxs_imem,
+ &qhs_ipa,
+ &qhs_usb3_phy,
+ &qhs_aop,
+ &qhs_blsp1,
+ &qhs_sdc1,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_ecc_cfg,
+ &qhs_audio,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_crypto0_cfg,
+ &xs_sys_tcu_cfg,
+ &qhs_clk_ctl,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = SDX55_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
- .num_links = 5,
- .links = { SDX55_SLAVE_AOSS,
- SDX55_SLAVE_IPA_CFG,
- SDX55_SLAVE_ANOC_SNOC,
- SDX55_SLAVE_AOP,
- SDX55_SLAVE_AUDIO
- },
+ .link_nodes = { &qhs_aoss,
+ &qhs_ipa,
+ &qns_aggre_noc,
+ &qhs_aop,
+ &qhs_audio, NULL },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
- .id = SDX55_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SDX55_SLAVE_EBI_CH0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SDX55_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDX55_SLAVE_EBI_CH0 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qns_memnoc_snoc = {
.name = "qns_memnoc_snoc",
- .id = SDX55_SLAVE_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_MASTER_MEM_NOC_SNOC },
+ .link_nodes = { &qnm_memnoc, NULL },
};
static struct qcom_icc_node qns_sys_pcie = {
.name = "qns_sys_pcie",
- .id = SDX55_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_MASTER_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_memnoc_pcie, NULL },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
- .id = SDX55_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SDX55_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SDX55_SLAVE_APPSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
- .id = SDX55_SLAVE_AUDIO,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_blsp1 = {
.name = "qhs_blsp1",
- .id = SDX55_SLAVE_BLSP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SDX55_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SDX55_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SDX55_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ecc_cfg = {
.name = "qhs_ecc_cfg",
- .id = SDX55_SLAVE_ECC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emac_cfg = {
.name = "qhs_emac_cfg",
- .id = SDX55_SLAVE_EMAC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SDX55_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SDX55_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SDX55_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_parf = {
.name = "qhs_pcie_parf",
- .id = SDX55_SLAVE_PCIE_PARF,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SDX55_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SDX55_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SDX55_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
- .id = SDX55_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = SDX55_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SDX55_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX55_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_spmi_fetcher = {
.name = "qhs_spmi_fetcher",
- .id = SDX55_SLAVE_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
- .id = SDX55_SLAVE_SPMI_VGI_COEX,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SDX55_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SDX55_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
- .id = SDX55_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_phy = {
.name = "qhs_usb3_phy",
- .id = SDX55_SLAVE_USB3_PHY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_aggre_noc = {
.name = "qns_aggre_noc",
- .id = SDX55_SLAVE_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_MASTER_ANOC_SNOC },
+ .link_nodes = { &qnm_aggre_noc, NULL },
};
static struct qcom_icc_node qns_snoc_memnoc = {
.name = "qns_snoc_memnoc",
- .id = SDX55_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX55_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SDX55_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SDX55_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
- .id = SDX55_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SDX55_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SDX55_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_mc0 = {
@@ -773,6 +766,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sdx55_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -795,6 +789,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx55_mem_noc = {
+ .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
@@ -874,6 +869,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx55_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdx55.h b/drivers/interconnect/qcom/sdx55.h
deleted file mode 100644
index 46cbabec8aa1f95be840e50618efd04bcbf89f10..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sdx55.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2021, Linaro Ltd.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H
-#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H
-
-/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */
-#define SDX55_MASTER_LLCC 1
-#define SDX55_MASTER_TCU_0 2
-#define SDX55_MASTER_SNOC_GC_MEM_NOC 3
-#define SDX55_MASTER_AMPSS_M0 4
-#define SDX55_MASTER_AUDIO 5
-#define SDX55_MASTER_BLSP_1 6
-#define SDX55_MASTER_QDSS_BAM 7
-#define SDX55_MASTER_QPIC 8
-#define SDX55_MASTER_SNOC_CFG 9
-#define SDX55_MASTER_SPMI_FETCHER 10
-#define SDX55_MASTER_ANOC_SNOC 11
-#define SDX55_MASTER_IPA 12
-#define SDX55_MASTER_MEM_NOC_SNOC 13
-#define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14
-#define SDX55_MASTER_CRYPTO_CORE_0 15
-#define SDX55_MASTER_EMAC 16
-#define SDX55_MASTER_IPA_PCIE 17
-#define SDX55_MASTER_PCIE 18
-#define SDX55_MASTER_QDSS_ETR 19
-#define SDX55_MASTER_SDCC_1 20
-#define SDX55_MASTER_USB3 21
-/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
-#define SDX55_SLAVE_EBI_CH0 23
-#define SDX55_SLAVE_LLCC 24
-#define SDX55_SLAVE_MEM_NOC_SNOC 25
-#define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26
-#define SDX55_SLAVE_ANOC_SNOC 27
-#define SDX55_SLAVE_SNOC_CFG 28
-#define SDX55_SLAVE_EMAC_CFG 29
-#define SDX55_SLAVE_USB3 30
-#define SDX55_SLAVE_TLMM 31
-#define SDX55_SLAVE_SPMI_FETCHER 32
-#define SDX55_SLAVE_QDSS_CFG 33
-#define SDX55_SLAVE_PDM 34
-#define SDX55_SLAVE_SNOC_MEM_NOC_GC 35
-#define SDX55_SLAVE_TCSR 36
-#define SDX55_SLAVE_CNOC_DDRSS 37
-#define SDX55_SLAVE_SPMI_VGI_COEX 38
-#define SDX55_SLAVE_QPIC 39
-#define SDX55_SLAVE_OCIMEM 40
-#define SDX55_SLAVE_IPA_CFG 41
-#define SDX55_SLAVE_USB3_PHY_CFG 42
-#define SDX55_SLAVE_AOP 43
-#define SDX55_SLAVE_BLSP_1 44
-#define SDX55_SLAVE_SDCC_1 45
-#define SDX55_SLAVE_CNOC_MSS 46
-#define SDX55_SLAVE_PCIE_PARF 47
-#define SDX55_SLAVE_ECC_CFG 48
-#define SDX55_SLAVE_AUDIO 49
-#define SDX55_SLAVE_AOSS 51
-#define SDX55_SLAVE_PRNG 52
-#define SDX55_SLAVE_CRYPTO_0_CFG 53
-#define SDX55_SLAVE_TCU 54
-#define SDX55_SLAVE_CLK_CTL 55
-#define SDX55_SLAVE_IMEM_CFG 56
-#define SDX55_SLAVE_SERVICE_SNOC 57
-#define SDX55_SLAVE_PCIE_0 58
-#define SDX55_SLAVE_QDSS_STM 59
-#define SDX55_SLAVE_APPSS 60
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 18/28] interconnect: qcom: sdx65: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (16 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 17/28] interconnect: qcom: sdx55: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 19/28] interconnect: qcom: sdx75: " Dmitry Baryshkov
` (10 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sdx65.c | 519 +++++++++++++++++++-------------------
drivers/interconnect/qcom/sdx65.h | 65 -----
2 files changed, 257 insertions(+), 327 deletions(-)
diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c
index cf24f94eef6e0e1a7c1e957e07a316803942d174..267eeeec0e655e13c9643c432139f4b94542d959 100644
--- a/drivers/interconnect/qcom/sdx65.c
+++ b/drivers/interconnect/qcom/sdx65.c
@@ -13,595 +13,587 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sdx65.h"
+
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node acm_tcu;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node xm_apps_rdwr;
+static struct qcom_icc_node qhm_audio;
+static struct qcom_icc_node qhm_blsp1;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qpic;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qhm_spmi_fetcher1;
+static struct qcom_icc_node qnm_aggre_noc;
+static struct qcom_icc_node qnm_ipa;
+static struct qcom_icc_node qnm_memnoc;
+static struct qcom_icc_node qnm_memnoc_pcie;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node xm_ipa2pcie_slv;
+static struct qcom_icc_node xm_pcie;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_usb3;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_memnoc_snoc;
+static struct qcom_icc_node qns_sys_pcie;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qhs_audio;
+static struct qcom_icc_node qhs_blsp1;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_ecc_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_pcie_parf;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qpic;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_spmi_fetcher;
+static struct qcom_icc_node qhs_spmi_vgi_coex;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_usb3;
+static struct qcom_icc_node qhs_usb3_phy;
+static struct qcom_icc_node qns_aggre_noc;
+static struct qcom_icc_node qns_snoc_memnoc;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_pcie;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SDX65_MASTER_LLCC,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX65_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
- .id = SDX65_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
- .num_links = 3,
- .links = { SDX65_SLAVE_LLCC,
- SDX65_SLAVE_MEM_NOC_SNOC,
- SDX65_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_memnoc_snoc,
+ &qns_sys_pcie, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SDX65_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDX65_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node xm_apps_rdwr = {
.name = "xm_apps_rdwr",
- .id = SDX65_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SDX65_SLAVE_LLCC,
- SDX65_SLAVE_MEM_NOC_SNOC,
- SDX65_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_memnoc_snoc,
+ &qns_sys_pcie, NULL },
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
- .id = SDX65_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX65_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node qhm_blsp1 = {
.name = "qhm_blsp1",
- .id = SDX65_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX65_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SDX65_MASTER_QDSS_BAM,
- .channels = 1,
- .buswidth = 4,
- .num_links = 26,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_AUDIO,
- SDX65_SLAVE_BLSP_1,
- SDX65_SLAVE_CLK_CTL,
- SDX65_SLAVE_CRYPTO_0_CFG,
- SDX65_SLAVE_CNOC_DDRSS,
- SDX65_SLAVE_ECC_CFG,
- SDX65_SLAVE_IMEM_CFG,
- SDX65_SLAVE_IPA_CFG,
- SDX65_SLAVE_CNOC_MSS,
- SDX65_SLAVE_PCIE_PARF,
- SDX65_SLAVE_PDM,
- SDX65_SLAVE_PRNG,
- SDX65_SLAVE_QDSS_CFG,
- SDX65_SLAVE_QPIC,
- SDX65_SLAVE_SDCC_1,
- SDX65_SLAVE_SNOC_CFG,
- SDX65_SLAVE_SPMI_FETCHER,
- SDX65_SLAVE_SPMI_VGI_COEX,
- SDX65_SLAVE_TCSR,
- SDX65_SLAVE_TLMM,
- SDX65_SLAVE_USB3,
- SDX65_SLAVE_USB3_PHY_CFG,
- SDX65_SLAVE_SNOC_MEM_NOC_GC,
- SDX65_SLAVE_IMEM,
- SDX65_SLAVE_TCU
- },
+ .channels = 1,
+ .buswidth = 4,
+ .link_nodes = { &qhs_aoss,
+ &qhs_audio,
+ &qhs_blsp1,
+ &qhs_clk_ctl,
+ &qhs_crypto0_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ecc_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_pdm,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qpic,
+ &qhs_sdc1,
+ &qhs_snoc_cfg,
+ &qhs_spmi_fetcher,
+ &qhs_spmi_vgi_coex,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_usb3,
+ &qhs_usb3_phy,
+ &qns_snoc_memnoc,
+ &qxs_imem,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
- .id = SDX65_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
- .num_links = 4,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_AUDIO,
- SDX65_SLAVE_IPA_CFG,
- SDX65_SLAVE_ANOC_SNOC
- },
+ .link_nodes = { &qhs_aoss,
+ &qhs_audio,
+ &qhs_ipa,
+ &qns_aggre_noc, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SDX65_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX65_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qhm_spmi_fetcher1 = {
.name = "qhm_spmi_fetcher1",
- .id = SDX65_MASTER_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_ANOC_SNOC
- },
+ .link_nodes = { &qhs_aoss,
+ &qns_aggre_noc, NULL },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
- .id = SDX65_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 29,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_APPSS,
- SDX65_SLAVE_AUDIO,
- SDX65_SLAVE_BLSP_1,
- SDX65_SLAVE_CLK_CTL,
- SDX65_SLAVE_CRYPTO_0_CFG,
- SDX65_SLAVE_CNOC_DDRSS,
- SDX65_SLAVE_ECC_CFG,
- SDX65_SLAVE_IMEM_CFG,
- SDX65_SLAVE_IPA_CFG,
- SDX65_SLAVE_CNOC_MSS,
- SDX65_SLAVE_PCIE_PARF,
- SDX65_SLAVE_PDM,
- SDX65_SLAVE_PRNG,
- SDX65_SLAVE_QDSS_CFG,
- SDX65_SLAVE_QPIC,
- SDX65_SLAVE_SDCC_1,
- SDX65_SLAVE_SNOC_CFG,
- SDX65_SLAVE_SPMI_FETCHER,
- SDX65_SLAVE_SPMI_VGI_COEX,
- SDX65_SLAVE_TCSR,
- SDX65_SLAVE_TLMM,
- SDX65_SLAVE_USB3,
- SDX65_SLAVE_USB3_PHY_CFG,
- SDX65_SLAVE_SNOC_MEM_NOC_GC,
- SDX65_SLAVE_IMEM,
- SDX65_SLAVE_PCIE_0,
- SDX65_SLAVE_QDSS_STM,
- SDX65_SLAVE_TCU
- },
+ .link_nodes = { &qhs_aoss,
+ &qhs_apss,
+ &qhs_audio,
+ &qhs_blsp1,
+ &qhs_clk_ctl,
+ &qhs_crypto0_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ecc_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_pdm,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qpic,
+ &qhs_sdc1,
+ &qhs_snoc_cfg,
+ &qhs_spmi_fetcher,
+ &qhs_spmi_vgi_coex,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_usb3,
+ &qhs_usb3_phy,
+ &qns_snoc_memnoc,
+ &qxs_imem,
+ &xs_pcie,
+ &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_ipa = {
.name = "qnm_ipa",
- .id = SDX65_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 26,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_AUDIO,
- SDX65_SLAVE_BLSP_1,
- SDX65_SLAVE_CLK_CTL,
- SDX65_SLAVE_CRYPTO_0_CFG,
- SDX65_SLAVE_CNOC_DDRSS,
- SDX65_SLAVE_ECC_CFG,
- SDX65_SLAVE_IMEM_CFG,
- SDX65_SLAVE_IPA_CFG,
- SDX65_SLAVE_CNOC_MSS,
- SDX65_SLAVE_PCIE_PARF,
- SDX65_SLAVE_PDM,
- SDX65_SLAVE_PRNG,
- SDX65_SLAVE_QDSS_CFG,
- SDX65_SLAVE_QPIC,
- SDX65_SLAVE_SDCC_1,
- SDX65_SLAVE_SNOC_CFG,
- SDX65_SLAVE_SPMI_FETCHER,
- SDX65_SLAVE_TCSR,
- SDX65_SLAVE_TLMM,
- SDX65_SLAVE_USB3,
- SDX65_SLAVE_USB3_PHY_CFG,
- SDX65_SLAVE_SNOC_MEM_NOC_GC,
- SDX65_SLAVE_IMEM,
- SDX65_SLAVE_PCIE_0,
- SDX65_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qhs_aoss,
+ &qhs_audio,
+ &qhs_blsp1,
+ &qhs_clk_ctl,
+ &qhs_crypto0_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ecc_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_pdm,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qpic,
+ &qhs_sdc1,
+ &qhs_snoc_cfg,
+ &qhs_spmi_fetcher,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_usb3,
+ &qhs_usb3_phy,
+ &qns_snoc_memnoc,
+ &qxs_imem,
+ &xs_pcie,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_memnoc = {
.name = "qnm_memnoc",
- .id = SDX65_MASTER_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 27,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_APPSS,
- SDX65_SLAVE_AUDIO,
- SDX65_SLAVE_BLSP_1,
- SDX65_SLAVE_CLK_CTL,
- SDX65_SLAVE_CRYPTO_0_CFG,
- SDX65_SLAVE_CNOC_DDRSS,
- SDX65_SLAVE_ECC_CFG,
- SDX65_SLAVE_IMEM_CFG,
- SDX65_SLAVE_IPA_CFG,
- SDX65_SLAVE_CNOC_MSS,
- SDX65_SLAVE_PCIE_PARF,
- SDX65_SLAVE_PDM,
- SDX65_SLAVE_PRNG,
- SDX65_SLAVE_QDSS_CFG,
- SDX65_SLAVE_QPIC,
- SDX65_SLAVE_SDCC_1,
- SDX65_SLAVE_SNOC_CFG,
- SDX65_SLAVE_SPMI_FETCHER,
- SDX65_SLAVE_SPMI_VGI_COEX,
- SDX65_SLAVE_TCSR,
- SDX65_SLAVE_TLMM,
- SDX65_SLAVE_USB3,
- SDX65_SLAVE_USB3_PHY_CFG,
- SDX65_SLAVE_IMEM,
- SDX65_SLAVE_QDSS_STM,
- SDX65_SLAVE_TCU
- },
+ .link_nodes = { &qhs_aoss,
+ &qhs_apss,
+ &qhs_audio,
+ &qhs_blsp1,
+ &qhs_clk_ctl,
+ &qhs_crypto0_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ecc_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_pdm,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qpic,
+ &qhs_sdc1,
+ &qhs_snoc_cfg,
+ &qhs_spmi_fetcher,
+ &qhs_spmi_vgi_coex,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_usb3,
+ &qhs_usb3_phy,
+ &qxs_imem,
+ &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_memnoc_pcie = {
.name = "qnm_memnoc_pcie",
- .id = SDX65_MASTER_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX65_SLAVE_PCIE_0 },
+ .link_nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SDX65_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_ANOC_SNOC
- },
+ .link_nodes = { &qhs_aoss,
+ &qns_aggre_noc, NULL },
};
static struct qcom_icc_node xm_ipa2pcie_slv = {
.name = "xm_ipa2pcie_slv",
- .id = SDX65_MASTER_IPA_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX65_SLAVE_PCIE_0 },
+ .link_nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
- .id = SDX65_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX65_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SDX65_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 26,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_AUDIO,
- SDX65_SLAVE_BLSP_1,
- SDX65_SLAVE_CLK_CTL,
- SDX65_SLAVE_CRYPTO_0_CFG,
- SDX65_SLAVE_CNOC_DDRSS,
- SDX65_SLAVE_ECC_CFG,
- SDX65_SLAVE_IMEM_CFG,
- SDX65_SLAVE_IPA_CFG,
- SDX65_SLAVE_CNOC_MSS,
- SDX65_SLAVE_PCIE_PARF,
- SDX65_SLAVE_PDM,
- SDX65_SLAVE_PRNG,
- SDX65_SLAVE_QDSS_CFG,
- SDX65_SLAVE_QPIC,
- SDX65_SLAVE_SDCC_1,
- SDX65_SLAVE_SNOC_CFG,
- SDX65_SLAVE_SPMI_FETCHER,
- SDX65_SLAVE_SPMI_VGI_COEX,
- SDX65_SLAVE_TCSR,
- SDX65_SLAVE_TLMM,
- SDX65_SLAVE_USB3,
- SDX65_SLAVE_USB3_PHY_CFG,
- SDX65_SLAVE_SNOC_MEM_NOC_GC,
- SDX65_SLAVE_IMEM,
- SDX65_SLAVE_TCU
- },
+ .link_nodes = { &qhs_aoss,
+ &qhs_audio,
+ &qhs_blsp1,
+ &qhs_clk_ctl,
+ &qhs_crypto0_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ecc_cfg,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_mss_cfg,
+ &qhs_pcie_parf,
+ &qhs_pdm,
+ &qhs_prng,
+ &qhs_qdss_cfg,
+ &qhs_qpic,
+ &qhs_sdc1,
+ &qhs_snoc_cfg,
+ &qhs_spmi_fetcher,
+ &qhs_spmi_vgi_coex,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_usb3,
+ &qhs_usb3_phy,
+ &qns_snoc_memnoc,
+ &qxs_imem,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = SDX65_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
- .num_links = 4,
- .links = { SDX65_SLAVE_AOSS,
- SDX65_SLAVE_AUDIO,
- SDX65_SLAVE_IPA_CFG,
- SDX65_SLAVE_ANOC_SNOC
- },
+ .link_nodes = { &qhs_aoss,
+ &qhs_audio,
+ &qhs_ipa,
+ &qns_aggre_noc, NULL },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
- .id = SDX65_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX65_SLAVE_ANOC_SNOC },
+ .link_nodes = { &qns_aggre_noc, NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SDX65_SLAVE_EBI1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SDX65_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDX65_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_memnoc_snoc = {
.name = "qns_memnoc_snoc",
- .id = SDX65_SLAVE_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX65_MASTER_MEM_NOC_SNOC },
+ .link_nodes = { &qnm_memnoc, NULL },
};
static struct qcom_icc_node qns_sys_pcie = {
.name = "qns_sys_pcie",
- .id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_memnoc_pcie, NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SDX65_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SDX65_SLAVE_APPSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
- .id = SDX65_SLAVE_AUDIO,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_blsp1 = {
.name = "qhs_blsp1",
- .id = SDX65_SLAVE_BLSP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SDX65_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SDX65_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SDX65_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ecc_cfg = {
.name = "qhs_ecc_cfg",
- .id = SDX65_SLAVE_ECC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SDX65_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SDX65_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SDX65_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_parf = {
.name = "qhs_pcie_parf",
- .id = SDX65_SLAVE_PCIE_PARF,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SDX65_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SDX65_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SDX65_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
- .id = SDX65_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = SDX65_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SDX65_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX65_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_spmi_fetcher = {
.name = "qhs_spmi_fetcher",
- .id = SDX65_SLAVE_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
- .id = SDX65_SLAVE_SPMI_VGI_COEX,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SDX65_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SDX65_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
- .id = SDX65_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_phy = {
.name = "qhs_usb3_phy",
- .id = SDX65_SLAVE_USB3_PHY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_aggre_noc = {
.name = "qns_aggre_noc",
- .id = SDX65_SLAVE_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX65_MASTER_ANOC_SNOC },
+ .link_nodes = { &qnm_aggre_noc, NULL },
};
static struct qcom_icc_node qns_snoc_memnoc = {
.name = "qns_snoc_memnoc",
- .id = SDX65_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDX65_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SDX65_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SDX65_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
- .id = SDX65_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SDX65_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SDX65_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
@@ -759,6 +751,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sdx65_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -781,6 +774,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx65_mem_noc = {
+ .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
@@ -857,6 +851,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx65_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdx65.h b/drivers/interconnect/qcom/sdx65.h
deleted file mode 100644
index 5dca6e8b32c99942e4a4f474999bc72ea2fb4fb6..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sdx65.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX65_H
-#define __DRIVERS_INTERCONNECT_QCOM_SDX65_H
-
-#define SDX65_MASTER_TCU_0 0
-#define SDX65_MASTER_LLCC 1
-#define SDX65_MASTER_AUDIO 2
-#define SDX65_MASTER_BLSP_1 3
-#define SDX65_MASTER_QDSS_BAM 4
-#define SDX65_MASTER_QPIC 5
-#define SDX65_MASTER_SNOC_CFG 6
-#define SDX65_MASTER_SPMI_FETCHER 7
-#define SDX65_MASTER_ANOC_SNOC 8
-#define SDX65_MASTER_IPA 9
-#define SDX65_MASTER_MEM_NOC_SNOC 10
-#define SDX65_MASTER_MEM_NOC_PCIE_SNOC 11
-#define SDX65_MASTER_SNOC_GC_MEM_NOC 12
-#define SDX65_MASTER_CRYPTO 13
-#define SDX65_MASTER_APPSS_PROC 14
-#define SDX65_MASTER_IPA_PCIE 15
-#define SDX65_MASTER_PCIE_0 16
-#define SDX65_MASTER_QDSS_ETR 17
-#define SDX65_MASTER_SDCC_1 18
-#define SDX65_MASTER_USB3 19
-#define SDX65_SLAVE_EBI1 512
-#define SDX65_SLAVE_AOSS 513
-#define SDX65_SLAVE_APPSS 514
-#define SDX65_SLAVE_AUDIO 515
-#define SDX65_SLAVE_BLSP_1 516
-#define SDX65_SLAVE_CLK_CTL 517
-#define SDX65_SLAVE_CRYPTO_0_CFG 518
-#define SDX65_SLAVE_CNOC_DDRSS 519
-#define SDX65_SLAVE_ECC_CFG 520
-#define SDX65_SLAVE_IMEM_CFG 521
-#define SDX65_SLAVE_IPA_CFG 522
-#define SDX65_SLAVE_CNOC_MSS 523
-#define SDX65_SLAVE_PCIE_PARF 524
-#define SDX65_SLAVE_PDM 525
-#define SDX65_SLAVE_PRNG 526
-#define SDX65_SLAVE_QDSS_CFG 527
-#define SDX65_SLAVE_QPIC 528
-#define SDX65_SLAVE_SDCC_1 529
-#define SDX65_SLAVE_SNOC_CFG 530
-#define SDX65_SLAVE_SPMI_FETCHER 531
-#define SDX65_SLAVE_SPMI_VGI_COEX 532
-#define SDX65_SLAVE_TCSR 533
-#define SDX65_SLAVE_TLMM 534
-#define SDX65_SLAVE_USB3 535
-#define SDX65_SLAVE_USB3_PHY_CFG 536
-#define SDX65_SLAVE_ANOC_SNOC 537
-#define SDX65_SLAVE_LLCC 538
-#define SDX65_SLAVE_MEM_NOC_SNOC 539
-#define SDX65_SLAVE_SNOC_MEM_NOC_GC 540
-#define SDX65_SLAVE_MEM_NOC_PCIE_SNOC 541
-#define SDX65_SLAVE_IMEM 542
-#define SDX65_SLAVE_SERVICE_SNOC 543
-#define SDX65_SLAVE_PCIE_0 544
-#define SDX65_SLAVE_QDSS_STM 545
-#define SDX65_SLAVE_TCU 546
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 19/28] interconnect: qcom: sdx75: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (17 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 18/28] interconnect: qcom: sdx65: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 20/28] interconnect: qcom: sm6350: " Dmitry Baryshkov
` (9 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sdx75.c | 471 +++++++++++++++++---------------------
drivers/interconnect/qcom/sdx75.h | 97 --------
2 files changed, 216 insertions(+), 352 deletions(-)
diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c
index ea799f7ec0c5a7e87bf6243471120c917d100ff6..bfd0ec87f68020ea1e832c405237d29054117f70 100644
--- a/drivers/interconnect/qcom/sdx75.c
+++ b/drivers/interconnect/qcom/sdx75.c
@@ -14,782 +14,737 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
-#include "sdx75.h"
+
+static struct qcom_icc_node qpic_core_master;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qnm_cnoc;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_gemnoc_cfg;
+static struct qcom_icc_node qnm_mdsp;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node xm_ipa2pcie;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node xm_pcie3_2;
+static struct qcom_icc_node qhm_audio;
+static struct qcom_icc_node qhm_gic;
+static struct qcom_icc_node qhm_pcie_rscc;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qpic;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qnm_aggre_noc;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qnm_system_noc_cfg;
+static struct qcom_icc_node qnm_system_noc_pcie_cfg;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node qxm_mvmss;
+static struct qcom_icc_node xm_emac_0;
+static struct qcom_icc_node xm_emac_1;
+static struct qcom_icc_node xm_qdss_etr0;
+static struct qcom_icc_node xm_qdss_etr1;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_usb3;
+static struct qcom_icc_node qpic_core_slave;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qhs_lagg;
+static struct qcom_icc_node qhs_mccc_master;
+static struct qcom_icc_node qns_gemnoc;
+static struct qcom_icc_node qss_snoop_bwmon;
+static struct qcom_icc_node qns_gemnoc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node srvc_gemnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_pcie_gemnoc;
+static struct qcom_icc_node ps_eth0_cfg;
+static struct qcom_icc_node ps_eth1_cfg;
+static struct qcom_icc_node qhs_audio;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_crypto_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_mvmss_cfg;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pcie2_cfg;
+static struct qcom_icc_node qhs_pcie_rscc;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qpic;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_spmi_vgi_coex;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_usb3;
+static struct qcom_icc_node qhs_usb3_phy;
+static struct qcom_icc_node qns_a1noc;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qns_system_noc_cfg;
+static struct qcom_icc_node qns_system_noc_pcie_cfg;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node srvc_pcie_system_noc;
+static struct qcom_icc_node srvc_system_noc;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_pcie_2;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qpic_core_master = {
.name = "qpic_core_master",
- .id = SDX75_MASTER_QPIC_CORE,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_QPIC_CORE },
+ .link_nodes = { &qpic_core_slave, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SDX75_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
- .id = SDX75_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 4,
- .links = { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER,
- SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON },
+ .link_nodes = { &qhs_lagg, &qhs_mccc_master,
+ &qns_gemnoc, &qss_snoop_bwmon, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SDX75_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC },
+ .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SDX75_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
- SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
- .id = SDX75_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_SERVICE_GEM_NOC },
+ .link_nodes = { &srvc_gemnoc, NULL },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
- .id = SDX75_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
- SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SDX75_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC },
+ .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SDX75_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
- SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SDX75_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node xm_ipa2pcie = {
.name = "xm_ipa2pcie",
- .id = SDX75_MASTER_IPA_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_pcie, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SDX75_MASTER_LLCC,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SDX75_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gemnoc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SDX75_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gemnoc, NULL },
};
static struct qcom_icc_node xm_pcie3_2 = {
.name = "xm_pcie3_2",
- .id = SDX75_MASTER_PCIE_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gemnoc, NULL },
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
- .id = SDX75_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
- .id = SDX75_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qhm_pcie_rscc = {
.name = "qhm_pcie_rscc",
- .id = SDX75_MASTER_PCIE_RSCC,
.channels = 1,
.buswidth = 4,
- .num_links = 31,
- .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG,
- SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL,
- SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG,
- SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG,
- SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG,
- SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG,
- SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM,
- SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG,
- SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0,
- SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4,
- SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR,
- SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3,
- SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG,
- SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG,
- SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM,
- SDX75_SLAVE_TCU },
+ .link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg,
+ &qhs_audio, &qhs_clk_ctl,
+ &qhs_crypto_cfg, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_mss_cfg, &qhs_mvmss_cfg,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pcie2_cfg, &qhs_pdm,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qpic, &qhs_qup0,
+ &qhs_sdc1, &qhs_sdc4,
+ &qhs_spmi_vgi_coex, &qhs_tcsr,
+ &qhs_tlmm, &qhs_usb3,
+ &qhs_usb3_phy, &qns_ddrss_cfg,
+ &qns_system_noc_cfg, &qns_system_noc_pcie_cfg,
+ &qxs_imem, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SDX75_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
- .id = SDX75_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SDX75_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
- .id = SDX75_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SDX75_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 32,
- .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG,
- SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL,
- SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG,
- SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG,
- SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG,
- SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG,
- SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG,
- SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG,
- SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC,
- SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1,
- SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX,
- SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM,
- SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG,
- SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG,
- SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM,
- SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU },
+ .link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg,
+ &qhs_audio, &qhs_clk_ctl,
+ &qhs_crypto_cfg, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_mss_cfg, &qhs_mvmss_cfg,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pcie2_cfg, &qhs_pcie_rscc,
+ &qhs_pdm, &qhs_prng,
+ &qhs_qdss_cfg, &qhs_qpic,
+ &qhs_qup0, &qhs_sdc1,
+ &qhs_sdc4, &qhs_spmi_vgi_coex,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_usb3, &qhs_usb3_phy,
+ &qns_ddrss_cfg, &qns_system_noc_cfg,
+ &qns_system_noc_pcie_cfg, &qxs_imem,
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SDX75_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1,
- SDX75_SLAVE_PCIE_2 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1,
+ &xs_pcie_2, NULL },
};
static struct qcom_icc_node qnm_system_noc_cfg = {
.name = "qnm_system_noc_cfg",
- .id = SDX75_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_system_noc, NULL },
};
static struct qcom_icc_node qnm_system_noc_pcie_cfg = {
.name = "qnm_system_noc_pcie_cfg",
- .id = SDX75_MASTER_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_SERVICE_PCIE_ANOC },
+ .link_nodes = { &srvc_pcie_system_noc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SDX75_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SDX75_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qxm_mvmss = {
.name = "qxm_mvmss",
- .id = SDX75_MASTER_MVMSS,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
- .id = SDX75_MASTER_EMAC_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node xm_emac_1 = {
.name = "xm_emac_1",
- .id = SDX75_MASTER_EMAC_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr0 = {
.name = "xm_qdss_etr0",
- .id = SDX75_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr1 = {
.name = "xm_qdss_etr1",
- .id = SDX75_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = SDX75_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SDX75_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
- .id = SDX75_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_SLAVE_A1NOC_CFG },
+ .link_nodes = { &qns_a1noc, NULL },
};
static struct qcom_icc_node qpic_core_slave = {
.name = "qpic_core_slave",
- .id = SDX75_SLAVE_QPIC_CORE,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SDX75_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lagg = {
.name = "qhs_lagg",
- .id = SDX75_SLAVE_LAGG_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mccc_master = {
.name = "qhs_mccc_master",
- .id = SDX75_SLAVE_MCCC_MASTER,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
- .id = SDX75_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_snoop_bwmon = {
.name = "qss_snoop_bwmon",
- .id = SDX75_SLAVE_SNOOP_BWMON,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_cnoc = {
.name = "qns_gemnoc_cnoc",
- .id = SDX75_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SDX75_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDX75_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SDX75_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDX75_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node srvc_gemnoc = {
.name = "srvc_gemnoc",
- .id = SDX75_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SDX75_SLAVE_EBI1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_pcie_gemnoc = {
.name = "qns_pcie_gemnoc",
- .id = SDX75_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDX75_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node ps_eth0_cfg = {
.name = "ps_eth0_cfg",
- .id = SDX75_SLAVE_ETH0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ps_eth1_cfg = {
.name = "ps_eth1_cfg",
- .id = SDX75_SLAVE_ETH1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
- .id = SDX75_SLAVE_AUDIO,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SDX75_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto_cfg = {
.name = "qhs_crypto_cfg",
- .id = SDX75_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SDX75_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SDX75_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SDX75_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SDX75_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mvmss_cfg = {
.name = "qhs_mvmss_cfg",
- .id = SDX75_SLAVE_ICBDI_MVMSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SDX75_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SDX75_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie2_cfg = {
.name = "qhs_pcie2_cfg",
- .id = SDX75_SLAVE_PCIE_2_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_rscc = {
.name = "qhs_pcie_rscc",
- .id = SDX75_SLAVE_PCIE_RSC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SDX75_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SDX75_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SDX75_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
- .id = SDX75_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SDX75_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = SDX75_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SDX75_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
- .id = SDX75_SLAVE_SPMI_VGI_COEX,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SDX75_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SDX75_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
- .id = SDX75_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_phy = {
.name = "qhs_usb3_phy",
- .id = SDX75_SLAVE_USB3_PHY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a1noc = {
.name = "qns_a1noc",
- .id = SDX75_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SDX75_MASTER_ANOC_SNOC },
+ .link_nodes = { &qnm_aggre_noc, NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = SDX75_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qnm_cnoc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SDX75_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SDX75_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qns_system_noc_cfg = {
.name = "qns_system_noc_cfg",
- .id = SDX75_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_MASTER_SNOC_CFG },
+ .link_nodes = { &qnm_system_noc_cfg, NULL },
};
static struct qcom_icc_node qns_system_noc_pcie_cfg = {
.name = "qns_system_noc_pcie_cfg",
- .id = SDX75_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SDX75_MASTER_PCIE_ANOC_CFG },
+ .link_nodes = { &qnm_system_noc_pcie_cfg, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SDX75_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_pcie_system_noc = {
.name = "srvc_pcie_system_noc",
- .id = SDX75_SLAVE_SERVICE_PCIE_ANOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_system_noc = {
.name = "srvc_system_noc",
- .id = SDX75_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SDX75_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SDX75_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_2 = {
.name = "xs_pcie_2",
- .id = SDX75_SLAVE_PCIE_2,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SDX75_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SDX75_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_ce0 = {
@@ -899,6 +854,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sdx75_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -914,6 +870,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx75_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@@ -940,6 +897,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx75_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -956,6 +914,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sdx75_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -975,6 +934,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sdx75_pcie_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1053,6 +1013,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx75_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/sdx75.h
deleted file mode 100644
index 24e88715992010d934a1a630979f864af3a8426c..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sdx75.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H
-#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H
-
-#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0
-#define SDX75_MASTER_ANOC_SNOC 1
-#define SDX75_MASTER_APPSS_PROC 2
-#define SDX75_MASTER_AUDIO 3
-#define SDX75_MASTER_CNOC_DC_NOC 4
-#define SDX75_MASTER_CRYPTO 5
-#define SDX75_MASTER_EMAC_0 6
-#define SDX75_MASTER_EMAC_1 7
-#define SDX75_MASTER_GEM_NOC_CFG 8
-#define SDX75_MASTER_GEM_NOC_CNOC 9
-#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10
-#define SDX75_MASTER_GIC 11
-#define SDX75_MASTER_GIC_AHB 12
-#define SDX75_MASTER_IPA 13
-#define SDX75_MASTER_IPA_PCIE 14
-#define SDX75_MASTER_LLCC 15
-#define SDX75_MASTER_MSS_PROC 16
-#define SDX75_MASTER_MVMSS 17
-#define SDX75_MASTER_PCIE_0 18
-#define SDX75_MASTER_PCIE_1 19
-#define SDX75_MASTER_PCIE_2 20
-#define SDX75_MASTER_PCIE_ANOC_CFG 21
-#define SDX75_MASTER_PCIE_RSCC 22
-#define SDX75_MASTER_QDSS_BAM 23
-#define SDX75_MASTER_QDSS_ETR 24
-#define SDX75_MASTER_QDSS_ETR_1 25
-#define SDX75_MASTER_QPIC 26
-#define SDX75_MASTER_QPIC_CORE 27
-#define SDX75_MASTER_QUP_0 28
-#define SDX75_MASTER_QUP_CORE_0 29
-#define SDX75_MASTER_SDCC_1 30
-#define SDX75_MASTER_SDCC_4 31
-#define SDX75_MASTER_SNOC_CFG 32
-#define SDX75_MASTER_SNOC_SF_MEM_NOC 33
-#define SDX75_MASTER_SYS_TCU 34
-#define SDX75_MASTER_USB3_0 35
-#define SDX75_SLAVE_A1NOC_CFG 36
-#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37
-#define SDX75_SLAVE_AUDIO 38
-#define SDX75_SLAVE_CLK_CTL 39
-#define SDX75_SLAVE_CRYPTO_0_CFG 40
-#define SDX75_SLAVE_CNOC_MSS 41
-#define SDX75_SLAVE_DDRSS_CFG 42
-#define SDX75_SLAVE_EBI1 43
-#define SDX75_SLAVE_ETH0_CFG 44
-#define SDX75_SLAVE_ETH1_CFG 45
-#define SDX75_SLAVE_GEM_NOC_CFG 46
-#define SDX75_SLAVE_GEM_NOC_CNOC 47
-#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48
-#define SDX75_SLAVE_IMEM 49
-#define SDX75_SLAVE_IMEM_CFG 50
-#define SDX75_SLAVE_IPA_CFG 51
-#define SDX75_SLAVE_IPC_ROUTER_CFG 52
-#define SDX75_SLAVE_LAGG_CFG 53
-#define SDX75_SLAVE_LLCC 54
-#define SDX75_SLAVE_MCCC_MASTER 55
-#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56
-#define SDX75_SLAVE_PCIE_0 57
-#define SDX75_SLAVE_PCIE_1 58
-#define SDX75_SLAVE_PCIE_2 59
-#define SDX75_SLAVE_PCIE_0_CFG 60
-#define SDX75_SLAVE_PCIE_1_CFG 61
-#define SDX75_SLAVE_PCIE_2_CFG 62
-#define SDX75_SLAVE_PCIE_ANOC_CFG 63
-#define SDX75_SLAVE_PCIE_RSC_CFG 64
-#define SDX75_SLAVE_PDM 65
-#define SDX75_SLAVE_PRNG 66
-#define SDX75_SLAVE_QDSS_CFG 67
-#define SDX75_SLAVE_QDSS_STM 68
-#define SDX75_SLAVE_QPIC 69
-#define SDX75_SLAVE_QPIC_CORE 70
-#define SDX75_SLAVE_QUP_0 71
-#define SDX75_SLAVE_QUP_CORE_0 72
-#define SDX75_SLAVE_SDCC_1 73
-#define SDX75_SLAVE_SDCC_4 74
-#define SDX75_SLAVE_SERVICE_GEM_NOC 75
-#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76
-#define SDX75_SLAVE_SERVICE_SNOC 77
-#define SDX75_SLAVE_SNOC_CFG 78
-#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79
-#define SDX75_SLAVE_SNOOP_BWMON 80
-#define SDX75_SLAVE_SPMI_VGI_COEX 81
-#define SDX75_SLAVE_TCSR 82
-#define SDX75_SLAVE_TCU 83
-#define SDX75_SLAVE_TLMM 84
-#define SDX75_SLAVE_USB3 85
-#define SDX75_SLAVE_USB3_PHY_CFG 86
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 20/28] interconnect: qcom: sm6350: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (18 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 19/28] interconnect: qcom: sdx75: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 21/28] interconnect: qcom: sm7150: " Dmitry Baryshkov
` (8 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm6350.c | 770 ++++++++++++++++++-------------------
drivers/interconnect/qcom/sm6350.h | 139 -------
2 files changed, 382 insertions(+), 527 deletions(-)
diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c
index 016f75ef970648b00a87483a6dee04dd8208726f..92a33c307c960157bf537bc5fe28b0348fbb9918 100644
--- a/drivers/interconnect/qcom/sm6350.c
+++ b/drivers/interconnect/qcom/sm6350.c
@@ -13,1153 +13,1137 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sm6350.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qup_0;
+static struct qcom_icc_node xm_emmc;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node qhm_a2noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup_1;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node qxm_camnoc_icp_uncomp;
+static struct qcom_icc_node qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qnm_npu;
+static struct qcom_icc_node qxm_npu_dsp;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qhm_cnoc_dc_noc;
+static struct qcom_icc_node acm_apps;
+static struct qcom_icc_node acm_sys_tcu;
+static struct qcom_icc_node qhm_gemnoc_cfg;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_gpu;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qnm_video0;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qxm_camnoc_hf;
+static struct qcom_icc_node qxm_camnoc_icp;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node amm_npu_sys;
+static struct qcom_icc_node qhm_npu_cfg;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gemnoc;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_camnoc_uncomp;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qns_cdsp_gemnoc;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_a2_noc_cfg;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy2;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_boot_rom;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_camera_nrt_thrott_cfg;
+static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_display_throttle_cfg;
+static struct qcom_icc_node qhs_emmc_cfg;
+static struct qcom_icc_node qhs_glm;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_npu_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qm_cfg;
+static struct qcom_icc_node qhs_qm_mpu_cfg;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_security;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_venus_throttle_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_gemnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qns_gem_noc_snoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node srvc_gemnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_cal_dp0;
+static struct qcom_icc_node qhs_cp;
+static struct qcom_icc_node qhs_dma_bwmon;
+static struct qcom_icc_node qhs_dpm;
+static struct qcom_icc_node qhs_isense;
+static struct qcom_icc_node qhs_llm;
+static struct qcom_icc_node qhs_tcm;
+static struct qcom_icc_node qns_npu_sys;
+static struct qcom_icc_node srvc_noc;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qhm_a1noc_cfg = {
.name = "qhm_a1noc_cfg",
- .id = SM6350_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node qhm_qup_0 = {
.name = "qhm_qup_0",
- .id = SM6350_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emmc = {
.name = "xm_emmc",
- .id = SM6350_MASTER_EMMC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM6350_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_a2noc_cfg = {
.name = "qhm_a2noc_cfg",
- .id = SM6350_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM6350_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup_1 = {
.name = "qhm_qup_1",
- .id = SM6350_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM6350_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM6350_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SM6350_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM6350_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM6350_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
.name = "qxm_camnoc_hf0_uncomp",
- .id = SM6350_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_icp_uncomp = {
.name = "qxm_camnoc_icp_uncomp",
- .id = SM6350_MASTER_CAMNOC_ICP_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
.name = "qxm_camnoc_sf_uncomp",
- .id = SM6350_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SM6350_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SM6350_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qnm_npu = {
.name = "qnm_npu",
- .id = SM6350_MASTER_NPU,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_CDSP_GEM_NOC },
+ .link_nodes = { &qns_cdsp_gemnoc, NULL },
};
static struct qcom_icc_node qxm_npu_dsp = {
.name = "qxm_npu_dsp",
- .id = SM6350_MASTER_NPU_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_SLAVE_CDSP_GEM_NOC },
+ .link_nodes = { &qns_cdsp_gemnoc, NULL },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = SM6350_SNOC_CNOC_MAS,
.channels = 1,
.buswidth = 8,
- .num_links = 42,
- .links = { SM6350_SLAVE_CAMERA_CFG,
- SM6350_SLAVE_SDCC_2,
- SM6350_SLAVE_CNOC_MNOC_CFG,
- SM6350_SLAVE_UFS_MEM_CFG,
- SM6350_SLAVE_QM_CFG,
- SM6350_SLAVE_SNOC_CFG,
- SM6350_SLAVE_QM_MPU_CFG,
- SM6350_SLAVE_GLM,
- SM6350_SLAVE_PDM,
- SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SM6350_SLAVE_A2NOC_CFG,
- SM6350_SLAVE_QDSS_CFG,
- SM6350_SLAVE_VSENSE_CTRL_CFG,
- SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SM6350_SLAVE_DISPLAY_CFG,
- SM6350_SLAVE_TCSR,
- SM6350_SLAVE_DCC_CFG,
- SM6350_SLAVE_CNOC_DDRSS,
- SM6350_SLAVE_DISPLAY_THROTTLE_CFG,
- SM6350_SLAVE_NPU_CFG,
- SM6350_SLAVE_AHB2PHY,
- SM6350_SLAVE_GRAPHICS_3D_CFG,
- SM6350_SLAVE_BOOT_ROM,
- SM6350_SLAVE_VENUS_CFG,
- SM6350_SLAVE_IPA_CFG,
- SM6350_SLAVE_SECURITY,
- SM6350_SLAVE_IMEM_CFG,
- SM6350_SLAVE_CNOC_MSS,
- SM6350_SLAVE_SERVICE_CNOC,
- SM6350_SLAVE_USB3,
- SM6350_SLAVE_VENUS_THROTTLE_CFG,
- SM6350_SLAVE_RBCPR_CX_CFG,
- SM6350_SLAVE_A1NOC_CFG,
- SM6350_SLAVE_AOSS,
- SM6350_SLAVE_PRNG,
- SM6350_SLAVE_EMMC_CFG,
- SM6350_SLAVE_CRYPTO_0_CFG,
- SM6350_SLAVE_PIMEM_CFG,
- SM6350_SLAVE_RBCPR_MX_CFG,
- SM6350_SLAVE_QUP_0,
- SM6350_SLAVE_QUP_1,
- SM6350_SLAVE_CLK_CTL
- },
+ .link_nodes = { &qhs_camera_cfg,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_qm_cfg,
+ &qhs_snoc_cfg,
+ &qhs_qm_mpu_cfg,
+ &qhs_glm,
+ &qhs_pdm,
+ &qhs_camera_nrt_thrott_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_camera_rt_throttle_cfg,
+ &qhs_display_cfg,
+ &qhs_tcsr,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_display_throttle_cfg,
+ &qhs_npu_cfg,
+ &qhs_ahb2phy0,
+ &qhs_gpuss_cfg,
+ &qhs_boot_rom,
+ &qhs_venus_cfg,
+ &qhs_ipa,
+ &qhs_security,
+ &qhs_imem_cfg,
+ &qhs_mss_cfg,
+ &srvc_cnoc,
+ &qhs_usb3_0,
+ &qhs_venus_throttle_cfg,
+ &qhs_cpr_cx,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_emmc_cfg,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_cpr_mx,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_clk_ctl, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SM6350_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 42,
- .links = { SM6350_SLAVE_CAMERA_CFG,
- SM6350_SLAVE_SDCC_2,
- SM6350_SLAVE_CNOC_MNOC_CFG,
- SM6350_SLAVE_UFS_MEM_CFG,
- SM6350_SLAVE_QM_CFG,
- SM6350_SLAVE_SNOC_CFG,
- SM6350_SLAVE_QM_MPU_CFG,
- SM6350_SLAVE_GLM,
- SM6350_SLAVE_PDM,
- SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SM6350_SLAVE_A2NOC_CFG,
- SM6350_SLAVE_QDSS_CFG,
- SM6350_SLAVE_VSENSE_CTRL_CFG,
- SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SM6350_SLAVE_DISPLAY_CFG,
- SM6350_SLAVE_TCSR,
- SM6350_SLAVE_DCC_CFG,
- SM6350_SLAVE_CNOC_DDRSS,
- SM6350_SLAVE_DISPLAY_THROTTLE_CFG,
- SM6350_SLAVE_NPU_CFG,
- SM6350_SLAVE_AHB2PHY,
- SM6350_SLAVE_GRAPHICS_3D_CFG,
- SM6350_SLAVE_BOOT_ROM,
- SM6350_SLAVE_VENUS_CFG,
- SM6350_SLAVE_IPA_CFG,
- SM6350_SLAVE_SECURITY,
- SM6350_SLAVE_IMEM_CFG,
- SM6350_SLAVE_CNOC_MSS,
- SM6350_SLAVE_SERVICE_CNOC,
- SM6350_SLAVE_USB3,
- SM6350_SLAVE_VENUS_THROTTLE_CFG,
- SM6350_SLAVE_RBCPR_CX_CFG,
- SM6350_SLAVE_A1NOC_CFG,
- SM6350_SLAVE_AOSS,
- SM6350_SLAVE_PRNG,
- SM6350_SLAVE_EMMC_CFG,
- SM6350_SLAVE_CRYPTO_0_CFG,
- SM6350_SLAVE_PIMEM_CFG,
- SM6350_SLAVE_RBCPR_MX_CFG,
- SM6350_SLAVE_QUP_0,
- SM6350_SLAVE_QUP_1,
- SM6350_SLAVE_CLK_CTL
- },
+ .link_nodes = { &qhs_camera_cfg,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_qm_cfg,
+ &qhs_snoc_cfg,
+ &qhs_qm_mpu_cfg,
+ &qhs_glm,
+ &qhs_pdm,
+ &qhs_camera_nrt_thrott_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_camera_rt_throttle_cfg,
+ &qhs_display_cfg,
+ &qhs_tcsr,
+ &qhs_dcc_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_display_throttle_cfg,
+ &qhs_npu_cfg,
+ &qhs_ahb2phy0,
+ &qhs_gpuss_cfg,
+ &qhs_boot_rom,
+ &qhs_venus_cfg,
+ &qhs_ipa,
+ &qhs_security,
+ &qhs_imem_cfg,
+ &qhs_mss_cfg,
+ &srvc_cnoc,
+ &qhs_usb3_0,
+ &qhs_venus_throttle_cfg,
+ &qhs_cpr_cx,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_emmc_cfg,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_cpr_mx,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_clk_ctl, NULL },
};
static struct qcom_icc_node qhm_cnoc_dc_noc = {
.name = "qhm_cnoc_dc_noc",
- .id = SM6350_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SM6350_SLAVE_LLCC_CFG,
- SM6350_SLAVE_GEM_NOC_CFG
- },
+ .link_nodes = { &qhs_llcc,
+ &qhs_gemnoc, NULL },
};
static struct qcom_icc_node acm_apps = {
.name = "acm_apps",
- .id = SM6350_MASTER_AMPSS_M0,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM6350_SLAVE_LLCC,
- SM6350_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node acm_sys_tcu = {
.name = "acm_sys_tcu",
- .id = SM6350_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM6350_SLAVE_LLCC,
- SM6350_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qhm_gemnoc_cfg = {
.name = "qhm_gemnoc_cfg",
- .id = SM6350_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 3,
- .links = { SM6350_SLAVE_MCDMA_MS_MPU_CFG,
- SM6350_SLAVE_SERVICE_GEM_NOC,
- SM6350_SLAVE_MSS_PROC_MS_MPU_CFG
- },
+ .link_nodes = { &qhs_mcdma_ms_mpu_cfg,
+ &srvc_gemnoc,
+ &qhs_mdsp_ms_mpu_cfg, NULL },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SM6350_MASTER_COMPUTE_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SM6350_SLAVE_LLCC,
- SM6350_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM6350_MASTER_MNOC_HF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SM6350_SLAVE_LLCC,
- SM6350_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM6350_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SM6350_SLAVE_LLCC,
- SM6350_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM6350_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM6350_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM6350_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qxm_gpu = {
.name = "qxm_gpu",
- .id = SM6350_MASTER_GRAPHICS_3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM6350_SLAVE_LLCC,
- SM6350_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM6350_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_SLAVE_EBI_CH0 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = SM6350_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
- .id = SM6350_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SM6350_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf = {
.name = "qxm_camnoc_hf",
- .id = SM6350_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_icp = {
.name = "qxm_camnoc_icp",
- .id = SM6350_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SM6350_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SM6350_MASTER_MDP_PORT0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node amm_npu_sys = {
.name = "amm_npu_sys",
- .id = SM6350_MASTER_NPU_SYS,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_SLAVE_NPU_COMPUTE_NOC },
+ .link_nodes = { &qns_npu_sys, NULL },
};
static struct qcom_icc_node qhm_npu_cfg = {
.name = "qhm_npu_cfg",
- .id = SM6350_MASTER_NPU_NOC_CFG,
- .channels = 1,
- .buswidth = 4,
- .num_links = 8,
- .links = { SM6350_SLAVE_SERVICE_NPU_NOC,
- SM6350_SLAVE_ISENSE_CFG,
- SM6350_SLAVE_NPU_LLM_CFG,
- SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG,
- SM6350_SLAVE_NPU_CP,
- SM6350_SLAVE_NPU_TCM,
- SM6350_SLAVE_NPU_CAL_DP0,
- SM6350_SLAVE_NPU_DPM
- },
+ .channels = 1,
+ .buswidth = 4,
+ .link_nodes = { &srvc_noc,
+ &qhs_isense,
+ &qhs_llm,
+ &qhs_dma_bwmon,
+ &qhs_cp,
+ &qhs_tcm,
+ &qhs_cal_dp0,
+ &qhs_dpm, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SM6350_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM6350_A1NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF,
- SM6350_SLAVE_PIMEM,
- SM6350_SLAVE_OCIMEM,
- SM6350_SLAVE_APPSS,
- SM6350_SNOC_CNOC_SLV,
- SM6350_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qns_gemnoc_sf,
+ &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM6350_A2NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 7,
- .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF,
- SM6350_SLAVE_PIMEM,
- SM6350_SLAVE_OCIMEM,
- SM6350_SLAVE_APPSS,
- SM6350_SNOC_CNOC_SLV,
- SM6350_SLAVE_TCU,
- SM6350_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qns_gemnoc_sf,
+ &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_gemnoc = {
.name = "qnm_gemnoc",
- .id = SM6350_MASTER_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 6,
- .links = { SM6350_SLAVE_PIMEM,
- SM6350_SLAVE_OCIMEM,
- SM6350_SLAVE_APPSS,
- SM6350_SNOC_CNOC_SLV,
- SM6350_SLAVE_TCU,
- SM6350_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SM6350_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC,
- SM6350_SLAVE_OCIMEM
- },
+ .link_nodes = { &qns_gemnoc_gc,
+ &qxs_imem, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM6350_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM6350_A1NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM6350_A1NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SM6350_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM6350_A2NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM6350_A2NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SM6350_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_camnoc_uncomp = {
.name = "qns_camnoc_uncomp",
- .id = SM6350_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SM6350_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SM6350_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cdsp_gemnoc = {
.name = "qns_cdsp_gemnoc",
- .id = SM6350_SLAVE_CDSP_GEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = SM6350_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qhs_a2_noc_cfg = {
.name = "qhs_a2_noc_cfg",
- .id = SM6350_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_MASTER_A2NOC_CFG },
+ .link_nodes = { &qhm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SM6350_SLAVE_AHB2PHY,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy2 = {
.name = "qhs_ahb2phy2",
- .id = SM6350_SLAVE_AHB2PHY_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM6350_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_boot_rom = {
.name = "qhs_boot_rom",
- .id = SM6350_SLAVE_BOOT_ROM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM6350_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = {
.name = "qhs_camera_nrt_thrott_cfg",
- .id = SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
.name = "qhs_camera_rt_throttle_cfg",
- .id = SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM6350_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM6350_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SM6350_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM6350_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SM6350_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SM6350_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM6350_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_throttle_cfg = {
.name = "qhs_display_throttle_cfg",
- .id = SM6350_SLAVE_DISPLAY_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emmc_cfg = {
.name = "qhs_emmc_cfg",
- .id = SM6350_SLAVE_EMMC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_glm = {
.name = "qhs_glm",
- .id = SM6350_SLAVE_GLM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM6350_SLAVE_GRAPHICS_3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM6350_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM6350_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = SM6350_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SM6350_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_npu_cfg = {
.name = "qhs_npu_cfg",
- .id = SM6350_SLAVE_NPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_MASTER_NPU_NOC_CFG },
+ .link_nodes = { &qhm_npu_cfg, NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM6350_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM6350_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM6350_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM6350_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qm_cfg = {
.name = "qhs_qm_cfg",
- .id = SM6350_SLAVE_QM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qm_mpu_cfg = {
.name = "qhs_qm_mpu_cfg",
- .id = SM6350_SLAVE_QM_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SM6350_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SM6350_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM6350_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
- .id = SM6350_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SM6350_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM6350_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM6350_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM6350_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM6350_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_throttle_cfg = {
.name = "qhs_venus_throttle_cfg",
- .id = SM6350_SLAVE_VENUS_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM6350_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SM6350_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gemnoc = {
.name = "qhs_gemnoc",
- .id = SM6350_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM6350_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qhm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SM6350_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg = {
.name = "qhs_mcdma_ms_mpu_cfg",
- .id = SM6350_SLAVE_MCDMA_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SM6350_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_snoc = {
.name = "qns_gem_noc_snoc",
- .id = SM6350_SLAVE_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_MASTER_GEM_NOC_SNOC },
+ .link_nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM6350_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM6350_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node srvc_gemnoc = {
.name = "srvc_gemnoc",
- .id = SM6350_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM6350_SLAVE_EBI_CH0,
.channels = 2,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM6350_SLAVE_MNOC_HF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SM6350_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM6350_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM6350_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cal_dp0 = {
.name = "qhs_cal_dp0",
- .id = SM6350_SLAVE_NPU_CAL_DP0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cp = {
.name = "qhs_cp",
- .id = SM6350_SLAVE_NPU_CP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dma_bwmon = {
.name = "qhs_dma_bwmon",
- .id = SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dpm = {
.name = "qhs_dpm",
- .id = SM6350_SLAVE_NPU_DPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_isense = {
.name = "qhs_isense",
- .id = SM6350_SLAVE_ISENSE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llm = {
.name = "qhs_llm",
- .id = SM6350_SLAVE_NPU_LLM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcm = {
.name = "qhs_tcm",
- .id = SM6350_SLAVE_NPU_TCM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_npu_sys = {
.name = "qns_npu_sys",
- .id = SM6350_SLAVE_NPU_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_noc = {
.name = "srvc_noc",
- .id = SM6350_SLAVE_SERVICE_NPU_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SM6350_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = SM6350_SNOC_CNOC_SLV,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_SNOC_CNOC_MAS },
+ .link_nodes = { &qnm_snoc, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM6350_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM6350_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM6350_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM6350_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM6350_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SM6350_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SM6350_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM6350_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM6350_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1376,6 +1360,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1401,6 +1386,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1428,6 +1414,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm6350_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1447,6 +1434,7 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_compute_noc = {
+ .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1507,6 +1495,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1523,6 +1512,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1554,6 +1544,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1581,6 +1572,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1605,6 +1597,7 @@ static struct qcom_icc_node * const npu_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_npu_noc = {
+ .alloc_dyn_id = true,
.nodes = npu_noc_nodes,
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
.bcms = npu_noc_bcms,
@@ -1641,6 +1634,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm6350.h b/drivers/interconnect/qcom/sm6350.h
deleted file mode 100644
index 43cf2930c88a5ae1bc36600ab2b3661a4d11ca71..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm6350.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm #define SM6350 interconnect IDs
- *
- * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM6350_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM6350_H
-
-#define SM6350_A1NOC_SNOC_MAS 0
-#define SM6350_A1NOC_SNOC_SLV 1
-#define SM6350_A2NOC_SNOC_MAS 2
-#define SM6350_A2NOC_SNOC_SLV 3
-#define SM6350_MASTER_A1NOC_CFG 4
-#define SM6350_MASTER_A2NOC_CFG 5
-#define SM6350_MASTER_AMPSS_M0 6
-#define SM6350_MASTER_CAMNOC_HF 7
-#define SM6350_MASTER_CAMNOC_HF0_UNCOMP 8
-#define SM6350_MASTER_CAMNOC_ICP 9
-#define SM6350_MASTER_CAMNOC_ICP_UNCOMP 10
-#define SM6350_MASTER_CAMNOC_SF 11
-#define SM6350_MASTER_CAMNOC_SF_UNCOMP 12
-#define SM6350_MASTER_CNOC_DC_NOC 13
-#define SM6350_MASTER_CNOC_MNOC_CFG 14
-#define SM6350_MASTER_COMPUTE_NOC 15
-#define SM6350_MASTER_CRYPTO_CORE_0 16
-#define SM6350_MASTER_EMMC 17
-#define SM6350_MASTER_GEM_NOC_CFG 18
-#define SM6350_MASTER_GEM_NOC_SNOC 19
-#define SM6350_MASTER_GIC 20
-#define SM6350_MASTER_GRAPHICS_3D 21
-#define SM6350_MASTER_IPA 22
-#define SM6350_MASTER_LLCC 23
-#define SM6350_MASTER_MDP_PORT0 24
-#define SM6350_MASTER_MNOC_HF_MEM_NOC 25
-#define SM6350_MASTER_MNOC_SF_MEM_NOC 26
-#define SM6350_MASTER_NPU 27
-#define SM6350_MASTER_NPU_NOC_CFG 28
-#define SM6350_MASTER_NPU_PROC 29
-#define SM6350_MASTER_NPU_SYS 30
-#define SM6350_MASTER_PIMEM 31
-#define SM6350_MASTER_QDSS_BAM 32
-#define SM6350_MASTER_QDSS_DAP 33
-#define SM6350_MASTER_QDSS_ETR 34
-#define SM6350_MASTER_QUP_0 35
-#define SM6350_MASTER_QUP_1 36
-#define SM6350_MASTER_QUP_CORE_0 37
-#define SM6350_MASTER_QUP_CORE_1 38
-#define SM6350_MASTER_SDCC_2 39
-#define SM6350_MASTER_SNOC_CFG 40
-#define SM6350_MASTER_SNOC_GC_MEM_NOC 41
-#define SM6350_MASTER_SNOC_SF_MEM_NOC 42
-#define SM6350_MASTER_SYS_TCU 43
-#define SM6350_MASTER_UFS_MEM 44
-#define SM6350_MASTER_USB3 45
-#define SM6350_MASTER_VIDEO_P0 46
-#define SM6350_MASTER_VIDEO_PROC 47
-#define SM6350_SLAVE_A1NOC_CFG 48
-#define SM6350_SLAVE_A2NOC_CFG 49
-#define SM6350_SLAVE_AHB2PHY 50
-#define SM6350_SLAVE_AHB2PHY_2 51
-#define SM6350_SLAVE_AOSS 52
-#define SM6350_SLAVE_APPSS 53
-#define SM6350_SLAVE_BOOT_ROM 54
-#define SM6350_SLAVE_CAMERA_CFG 55
-#define SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG 56
-#define SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG 57
-#define SM6350_SLAVE_CAMNOC_UNCOMP 58
-#define SM6350_SLAVE_CDSP_GEM_NOC 59
-#define SM6350_SLAVE_CLK_CTL 60
-#define SM6350_SLAVE_CNOC_DDRSS 61
-#define SM6350_SLAVE_CNOC_MNOC_CFG 62
-#define SM6350_SLAVE_CNOC_MSS 63
-#define SM6350_SLAVE_CRYPTO_0_CFG 64
-#define SM6350_SLAVE_DCC_CFG 65
-#define SM6350_SLAVE_DISPLAY_CFG 66
-#define SM6350_SLAVE_DISPLAY_THROTTLE_CFG 67
-#define SM6350_SLAVE_EBI_CH0 68
-#define SM6350_SLAVE_EMMC_CFG 69
-#define SM6350_SLAVE_GEM_NOC_CFG 70
-#define SM6350_SLAVE_GEM_NOC_SNOC 71
-#define SM6350_SLAVE_GLM 72
-#define SM6350_SLAVE_GRAPHICS_3D_CFG 73
-#define SM6350_SLAVE_IMEM_CFG 74
-#define SM6350_SLAVE_IPA_CFG 75
-#define SM6350_SLAVE_ISENSE_CFG 76
-#define SM6350_SLAVE_LLCC 77
-#define SM6350_SLAVE_LLCC_CFG 78
-#define SM6350_SLAVE_MCDMA_MS_MPU_CFG 79
-#define SM6350_SLAVE_MNOC_HF_MEM_NOC 80
-#define SM6350_SLAVE_MNOC_SF_MEM_NOC 81
-#define SM6350_SLAVE_MSS_PROC_MS_MPU_CFG 82
-#define SM6350_SLAVE_NPU_CAL_DP0 83
-#define SM6350_SLAVE_NPU_CFG 84
-#define SM6350_SLAVE_NPU_COMPUTE_NOC 85
-#define SM6350_SLAVE_NPU_CP 86
-#define SM6350_SLAVE_NPU_DPM 87
-#define SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG 88
-#define SM6350_SLAVE_NPU_LLM_CFG 89
-#define SM6350_SLAVE_NPU_TCM 90
-#define SM6350_SLAVE_OCIMEM 91
-#define SM6350_SLAVE_PDM 92
-#define SM6350_SLAVE_PIMEM 93
-#define SM6350_SLAVE_PIMEM_CFG 94
-#define SM6350_SLAVE_PRNG 95
-#define SM6350_SLAVE_QDSS_CFG 96
-#define SM6350_SLAVE_QDSS_STM 97
-#define SM6350_SLAVE_QM_CFG 98
-#define SM6350_SLAVE_QM_MPU_CFG 99
-#define SM6350_SLAVE_QUP_0 100
-#define SM6350_SLAVE_QUP_1 101
-#define SM6350_SLAVE_QUP_CORE_0 102
-#define SM6350_SLAVE_QUP_CORE_1 103
-#define SM6350_SLAVE_RBCPR_CX_CFG 104
-#define SM6350_SLAVE_RBCPR_MX_CFG 105
-#define SM6350_SLAVE_SDCC_2 106
-#define SM6350_SLAVE_SECURITY 107
-#define SM6350_SLAVE_SERVICE_A1NOC 108
-#define SM6350_SLAVE_SERVICE_A2NOC 109
-#define SM6350_SLAVE_SERVICE_CNOC 110
-#define SM6350_SLAVE_SERVICE_GEM_NOC 111
-#define SM6350_SLAVE_SERVICE_MNOC 112
-#define SM6350_SLAVE_SERVICE_NPU_NOC 113
-#define SM6350_SLAVE_SERVICE_SNOC 114
-#define SM6350_SLAVE_SNOC_CFG 115
-#define SM6350_SLAVE_SNOC_GEM_NOC_GC 116
-#define SM6350_SLAVE_SNOC_GEM_NOC_SF 117
-#define SM6350_SLAVE_TCSR 118
-#define SM6350_SLAVE_TCU 119
-#define SM6350_SLAVE_UFS_MEM_CFG 120
-#define SM6350_SLAVE_USB3 121
-#define SM6350_SLAVE_VENUS_CFG 122
-#define SM6350_SLAVE_VENUS_THROTTLE_CFG 123
-#define SM6350_SLAVE_VSENSE_CTRL_CFG 124
-#define SM6350_SNOC_CNOC_MAS 125
-#define SM6350_SNOC_CNOC_SLV 126
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 21/28] interconnect: qcom: sm7150: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (19 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 20/28] interconnect: qcom: sm6350: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 22/28] interconnect: qcom: sm8150: " Dmitry Baryshkov
` (7 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm7150.c | 790 ++++++++++++++++++-------------------
drivers/interconnect/qcom/sm7150.h | 140 -------
2 files changed, 385 insertions(+), 545 deletions(-)
diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom/sm7150.c
index 3892e49e614ba189d29d9bb6f278835283bfaac0..5e2b77f3e1d2245ded149add1548e603a1358295 100644
--- a/drivers/interconnect/qcom/sm7150.c
+++ b/drivers/interconnect/qcom/sm7150.c
@@ -14,1171 +14,1141 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sm7150.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qup_center;
+static struct qcom_icc_node qhm_tsif;
+static struct qcom_icc_node xm_emmc;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node qhm_a2noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup_north;
+static struct qcom_icc_node qnm_cnoc;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node qxm_camnoc_rt_uncomp;
+static struct qcom_icc_node qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node qxm_camnoc_nrt_uncomp;
+static struct qcom_icc_node qnm_npu;
+static struct qcom_icc_node qhm_spdm;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qhm_cnoc_dc_noc;
+static struct qcom_icc_node acm_apps;
+static struct qcom_icc_node acm_sys_tcu;
+static struct qcom_icc_node qhm_gemnoc_cfg;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_gpu;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qxm_camnoc_hf;
+static struct qcom_icc_node qxm_camnoc_nrt;
+static struct qcom_icc_node qxm_camnoc_rt;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_mdp1;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node qxm_venus0;
+static struct qcom_icc_node qxm_venus1;
+static struct qcom_icc_node qxm_venus_arm9;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gemnoc;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_gemnoc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_camnoc_uncomp;
+static struct qcom_icc_node qns_cdsp_gemnoc;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_a2_noc_cfg;
+static struct qcom_icc_node qhs_ahb2phy_north;
+static struct qcom_icc_node qhs_ahb2phy_south;
+static struct qcom_icc_node qhs_ahb2phy_west;
+static struct qcom_icc_node qhs_aop;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_camera_nrt_thrott_cfg;
+static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_dsp_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_display_throttle_cfg;
+static struct qcom_icc_node qhs_emmc_cfg;
+static struct qcom_icc_node qhs_glm;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_pcie_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qupv3_center;
+static struct qcom_icc_node qhs_qupv3_north;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_spdm;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm_north;
+static struct qcom_icc_node qhs_tlmm_south;
+static struct qcom_icc_node qhs_tlmm_west;
+static struct qcom_icc_node qhs_tsif;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_venus_cvp_throttle_cfg;
+static struct qcom_icc_node qhs_venus_throttle_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_gemnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qns_gem_noc_snoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node srvc_gemnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns2_mem_noc;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qhm_a1noc_cfg = {
- .name = "qhm-a1noc-cfg",
- .id = SM7150_MASTER_A1NOC_CFG,
+ .name = "qhm_a1noc_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node qhm_qup_center = {
.name = "qhm_qup_center",
- .id = SM7150_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_tsif = {
.name = "qhm_tsif",
- .id = SM7150_MASTER_TSIF,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emmc = {
.name = "xm_emmc",
- .id = SM7150_MASTER_EMMC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM7150_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM7150_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM7150_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_a2noc_cfg = {
.name = "qhm_a2noc_cfg",
- .id = SM7150_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM7150_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup_north = {
.name = "qhm_qup_north",
- .id = SM7150_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
- .id = SM7150_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM7150_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM7150_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM7150_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gemnoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SM7150_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM7150_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
.name = "qxm_camnoc_hf0_uncomp",
- .id = SM7150_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_rt_uncomp = {
.name = "qxm_camnoc_rt_uncomp",
- .id = SM7150_MASTER_CAMNOC_RT_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
.name = "qxm_camnoc_sf_uncomp",
- .id = SM7150_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_nrt_uncomp = {
.name = "qxm_camnoc_nrt_uncomp",
- .id = SM7150_MASTER_CAMNOC_NRT_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qnm_npu = {
.name = "qnm_npu",
- .id = SM7150_MASTER_NPU,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_CDSP_GEM_NOC },
+ .link_nodes = { &qns_cdsp_gemnoc, NULL },
};
static struct qcom_icc_node qhm_spdm = {
.name = "qhm_spdm",
- .id = SM7150_MASTER_SPDM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_SLAVE_CNOC_A2NOC },
+ .link_nodes = { &qns_cnoc_a2noc, NULL },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = SM7150_SNOC_CNOC_MAS,
.channels = 1,
.buswidth = 8,
- .num_links = 47,
- .links = { SM7150_SLAVE_TLMM_SOUTH,
- SM7150_SLAVE_CAMERA_CFG,
- SM7150_SLAVE_SDCC_4,
- SM7150_SLAVE_SDCC_2,
- SM7150_SLAVE_CNOC_MNOC_CFG,
- SM7150_SLAVE_UFS_MEM_CFG,
- SM7150_SLAVE_QUP_0,
- SM7150_SLAVE_GLM,
- SM7150_SLAVE_PDM,
- SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SM7150_SLAVE_A2NOC_CFG,
- SM7150_SLAVE_QDSS_CFG,
- SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SM7150_SLAVE_DISPLAY_CFG,
- SM7150_SLAVE_PCIE_CFG,
- SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
- SM7150_SLAVE_TCSR,
- SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
- SM7150_SLAVE_CNOC_DDRSS,
- SM7150_SLAVE_AHB2PHY_NORTH,
- SM7150_SLAVE_SNOC_CFG,
- SM7150_SLAVE_GRAPHICS_3D_CFG,
- SM7150_SLAVE_VENUS_CFG,
- SM7150_SLAVE_TSIF,
- SM7150_SLAVE_CDSP_CFG,
- SM7150_SLAVE_CLK_CTL,
- SM7150_SLAVE_AOP,
- SM7150_SLAVE_QUP_1,
- SM7150_SLAVE_AHB2PHY_SOUTH,
- SM7150_SLAVE_SERVICE_CNOC,
- SM7150_SLAVE_AHB2PHY_WEST,
- SM7150_SLAVE_USB3,
- SM7150_SLAVE_VENUS_THROTTLE_CFG,
- SM7150_SLAVE_IPA_CFG,
- SM7150_SLAVE_RBCPR_CX_CFG,
- SM7150_SLAVE_TLMM_WEST,
- SM7150_SLAVE_A1NOC_CFG,
- SM7150_SLAVE_AOSS,
- SM7150_SLAVE_PRNG,
- SM7150_SLAVE_VSENSE_CTRL_CFG,
- SM7150_SLAVE_EMMC_CFG,
- SM7150_SLAVE_SPDM_WRAPPER,
- SM7150_SLAVE_CRYPTO_0_CFG,
- SM7150_SLAVE_PIMEM_CFG,
- SM7150_SLAVE_TLMM_NORTH,
- SM7150_SLAVE_RBCPR_MX_CFG,
- SM7150_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_tlmm_south,
+ &qhs_camera_cfg,
+ &qhs_sdc4,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_qupv3_center,
+ &qhs_glm,
+ &qhs_pdm,
+ &qhs_camera_nrt_thrott_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_camera_rt_throttle_cfg,
+ &qhs_display_cfg,
+ &qhs_pcie_cfg,
+ &qhs_display_throttle_cfg,
+ &qhs_tcsr,
+ &qhs_venus_cvp_throttle_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ahb2phy_north,
+ &qhs_snoc_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_compute_dsp_cfg,
+ &qhs_clk_ctl,
+ &qhs_aop,
+ &qhs_qupv3_north,
+ &qhs_ahb2phy_south,
+ &srvc_cnoc,
+ &qhs_ahb2phy_west,
+ &qhs_usb3_0,
+ &qhs_venus_throttle_cfg,
+ &qhs_ipa,
+ &qhs_cpr_cx,
+ &qhs_tlmm_west,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_emmc_cfg,
+ &qhs_spdm,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_tlmm_north,
+ &qhs_cpr_mx,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SM7150_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 48,
- .links = { SM7150_SLAVE_TLMM_SOUTH,
- SM7150_SLAVE_CAMERA_CFG,
- SM7150_SLAVE_SDCC_4,
- SM7150_SLAVE_SDCC_2,
- SM7150_SLAVE_CNOC_MNOC_CFG,
- SM7150_SLAVE_UFS_MEM_CFG,
- SM7150_SLAVE_QUP_0,
- SM7150_SLAVE_GLM,
- SM7150_SLAVE_PDM,
- SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SM7150_SLAVE_A2NOC_CFG,
- SM7150_SLAVE_QDSS_CFG,
- SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SM7150_SLAVE_DISPLAY_CFG,
- SM7150_SLAVE_PCIE_CFG,
- SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
- SM7150_SLAVE_TCSR,
- SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
- SM7150_SLAVE_CNOC_DDRSS,
- SM7150_SLAVE_CNOC_A2NOC,
- SM7150_SLAVE_AHB2PHY_NORTH,
- SM7150_SLAVE_SNOC_CFG,
- SM7150_SLAVE_GRAPHICS_3D_CFG,
- SM7150_SLAVE_VENUS_CFG,
- SM7150_SLAVE_TSIF,
- SM7150_SLAVE_CDSP_CFG,
- SM7150_SLAVE_CLK_CTL,
- SM7150_SLAVE_AOP,
- SM7150_SLAVE_QUP_1,
- SM7150_SLAVE_AHB2PHY_SOUTH,
- SM7150_SLAVE_SERVICE_CNOC,
- SM7150_SLAVE_AHB2PHY_WEST,
- SM7150_SLAVE_USB3,
- SM7150_SLAVE_VENUS_THROTTLE_CFG,
- SM7150_SLAVE_IPA_CFG,
- SM7150_SLAVE_RBCPR_CX_CFG,
- SM7150_SLAVE_TLMM_WEST,
- SM7150_SLAVE_A1NOC_CFG,
- SM7150_SLAVE_AOSS,
- SM7150_SLAVE_PRNG,
- SM7150_SLAVE_VSENSE_CTRL_CFG,
- SM7150_SLAVE_EMMC_CFG,
- SM7150_SLAVE_SPDM_WRAPPER,
- SM7150_SLAVE_CRYPTO_0_CFG,
- SM7150_SLAVE_PIMEM_CFG,
- SM7150_SLAVE_TLMM_NORTH,
- SM7150_SLAVE_RBCPR_MX_CFG,
- SM7150_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_tlmm_south,
+ &qhs_camera_cfg,
+ &qhs_sdc4,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_qupv3_center,
+ &qhs_glm,
+ &qhs_pdm,
+ &qhs_camera_nrt_thrott_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_camera_rt_throttle_cfg,
+ &qhs_display_cfg,
+ &qhs_pcie_cfg,
+ &qhs_display_throttle_cfg,
+ &qhs_tcsr,
+ &qhs_venus_cvp_throttle_cfg,
+ &qhs_ddrss_cfg,
+ &qns_cnoc_a2noc,
+ &qhs_ahb2phy_north,
+ &qhs_snoc_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_compute_dsp_cfg,
+ &qhs_clk_ctl,
+ &qhs_aop,
+ &qhs_qupv3_north,
+ &qhs_ahb2phy_south,
+ &srvc_cnoc,
+ &qhs_ahb2phy_west,
+ &qhs_usb3_0,
+ &qhs_venus_throttle_cfg,
+ &qhs_ipa,
+ &qhs_cpr_cx,
+ &qhs_tlmm_west,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_emmc_cfg,
+ &qhs_spdm,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_tlmm_north,
+ &qhs_cpr_mx,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node qhm_cnoc_dc_noc = {
.name = "qhm_cnoc_dc_noc",
- .id = SM7150_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SM7150_SLAVE_LLCC_CFG,
- SM7150_SLAVE_GEM_NOC_CFG
- },
+ .link_nodes = { &qhs_llcc,
+ &qhs_gemnoc, NULL },
};
static struct qcom_icc_node acm_apps = {
.name = "acm_apps",
- .id = SM7150_MASTER_AMPSS_M0,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node acm_sys_tcu = {
.name = "acm_sys_tcu",
- .id = SM7150_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qhm_gemnoc_cfg = {
.name = "qhm_gemnoc_cfg",
- .id = SM7150_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SM7150_SLAVE_SERVICE_GEM_NOC,
- SM7150_SLAVE_MSS_PROC_MS_MPU_CFG
- },
+ .link_nodes = { &srvc_gemnoc,
+ &qhs_mdsp_ms_mpu_cfg, NULL },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SM7150_MASTER_COMPUTE_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM7150_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM7150_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM7150_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM7150_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM7150_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM7150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qxm_gpu = {
.name = "qxm_gpu",
- .id = SM7150_MASTER_GRAPHICS_3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM7150_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_SLAVE_EBI_CH0 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = SM7150_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf = {
.name = "qxm_camnoc_hf",
- .id = SM7150_MASTER_CAMNOC_HF0,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_nrt = {
.name = "qxm_camnoc_nrt",
- .id = SM7150_MASTER_CAMNOC_NRT,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_camnoc_rt = {
.name = "qxm_camnoc_rt",
- .id = SM7150_MASTER_CAMNOC_RT,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SM7150_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SM7150_MASTER_MDP_PORT0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_mdp1 = {
.name = "qxm_mdp1",
- .id = SM7150_MASTER_MDP_PORT1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = SM7150_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus0 = {
.name = "qxm_venus0",
- .id = SM7150_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus1 = {
.name = "qxm_venus1",
- .id = SM7150_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus_arm9 = {
.name = "qxm_venus_arm9",
- .id = SM7150_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SM7150_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM7150_A1NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF,
- SM7150_SLAVE_PIMEM,
- SM7150_SLAVE_OCIMEM,
- SM7150_SLAVE_APPSS,
- SM7150_SNOC_CNOC_SLV,
- SM7150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qns_gemnoc_sf,
+ &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM7150_A2NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 7,
- .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF,
- SM7150_SLAVE_PIMEM,
- SM7150_SLAVE_OCIMEM,
- SM7150_SLAVE_APPSS,
- SM7150_SNOC_CNOC_SLV,
- SM7150_SLAVE_TCU,
- SM7150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qns_gemnoc_sf,
+ &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_gemnoc = {
.name = "qnm_gemnoc",
- .id = SM7150_MASTER_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 6,
- .links = { SM7150_SLAVE_PIMEM,
- SM7150_SLAVE_OCIMEM,
- SM7150_SLAVE_APPSS,
- SM7150_SNOC_CNOC_SLV,
- SM7150_SLAVE_TCU,
- SM7150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SM7150_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC,
- SM7150_SLAVE_OCIMEM
- },
+ .link_nodes = { &qns_gemnoc_gc,
+ &qxs_imem, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM7150_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC,
- SM7150_SLAVE_OCIMEM
- },
+ .link_nodes = { &qns_gemnoc_gc,
+ &qxs_imem, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM7150_A1NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM7150_A1NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SM7150_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM7150_A2NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM7150_A2NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qns_pcie_gemnoc = {
.name = "qns_pcie_gemnoc",
- .id = SM7150_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SM7150_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_camnoc_uncomp = {
.name = "qns_camnoc_uncomp",
- .id = SM7150_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cdsp_gemnoc = {
.name = "qns_cdsp_gemnoc",
- .id = SM7150_SLAVE_CDSP_GEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = SM7150_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qhs_a2_noc_cfg = {
.name = "qhs_a2_noc_cfg",
- .id = SM7150_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_MASTER_A2NOC_CFG },
+ .link_nodes = { &qhm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qhs_ahb2phy_north = {
.name = "qhs_ahb2phy_north",
- .id = SM7150_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy_south = {
.name = "qhs_ahb2phy_south",
- .id = SM7150_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy_west = {
.name = "qhs_ahb2phy_west",
- .id = SM7150_SLAVE_AHB2PHY_WEST,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
- .id = SM7150_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM7150_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM7150_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = {
.name = "qhs_camera_nrt_thrott_cfg",
- .id = SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
.name = "qhs_camera_rt_throttle_cfg",
- .id = SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM7150_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_dsp_cfg = {
.name = "qhs_compute_dsp_cfg",
- .id = SM7150_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM7150_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SM7150_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM7150_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SM7150_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM7150_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_throttle_cfg = {
.name = "qhs_display_throttle_cfg",
- .id = SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emmc_cfg = {
.name = "qhs_emmc_cfg",
- .id = SM7150_SLAVE_EMMC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_glm = {
.name = "qhs_glm",
- .id = SM7150_SLAVE_GLM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM7150_SLAVE_GRAPHICS_3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM7150_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM7150_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = SM7150_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_pcie_cfg = {
.name = "qhs_pcie_cfg",
- .id = SM7150_SLAVE_PCIE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM7150_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM7150_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM7150_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM7150_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_center = {
.name = "qhs_qupv3_center",
- .id = SM7150_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_north = {
.name = "qhs_qupv3_north",
- .id = SM7150_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM7150_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM7150_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SM7150_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_spdm = {
.name = "qhs_spdm",
- .id = SM7150_SLAVE_SPDM_WRAPPER,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM7150_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_north = {
.name = "qhs_tlmm_north",
- .id = SM7150_SLAVE_TLMM_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_south = {
.name = "qhs_tlmm_south",
- .id = SM7150_SLAVE_TLMM_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_west = {
.name = "qhs_tlmm_west",
- .id = SM7150_SLAVE_TLMM_WEST,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tsif = {
.name = "qhs_tsif",
- .id = SM7150_SLAVE_TSIF,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM7150_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM7150_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM7150_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
.name = "qhs_venus_cvp_throttle_cfg",
- .id = SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_throttle_cfg = {
.name = "qhs_venus_throttle_cfg",
- .id = SM7150_SLAVE_VENUS_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM7150_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = SM7150_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc, NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SM7150_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gemnoc = {
.name = "qhs_gemnoc",
- .id = SM7150_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM7150_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qhm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SM7150_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SM7150_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_snoc = {
.name = "qns_gem_noc_snoc",
- .id = SM7150_SLAVE_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_MASTER_GEM_NOC_SNOC },
+ .link_nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM7150_SLAVE_LLCC,
.channels = 2,
.buswidth = 16,
- .num_links = 1,
- .links = { SM7150_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node srvc_gemnoc = {
.name = "srvc_gemnoc",
- .id = SM7150_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM7150_SLAVE_EBI_CH0,
.channels = 2,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns2_mem_noc = {
.name = "qns2_mem_noc",
- .id = SM7150_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM7150_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM7150_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM7150_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SM7150_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = SM7150_SNOC_CNOC_SLV,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_SNOC_CNOC_MAS },
+ .link_nodes = { &qnm_snoc, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM7150_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM7150_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM7150_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM7150_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM7150_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SM7150_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SM7150_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM7150_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM7150_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1414,6 +1384,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1443,6 +1414,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1462,6 +1434,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm7150_camnoc_virt = {
+ .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1479,6 +1452,7 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_compute_noc = {
+ .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1544,6 +1518,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1560,6 +1535,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1591,6 +1567,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1608,6 +1585,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm7150_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1639,6 +1617,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1675,6 +1654,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm7150.h b/drivers/interconnect/qcom/sm7150.h
deleted file mode 100644
index e00a9b0c1279367890e01e2a4108aef7c5cd7580..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm7150.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Qualcomm #define SM7150 interconnect IDs
- *
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7150_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM7150_H
-
-#define SM7150_A1NOC_SNOC_MAS 0
-#define SM7150_A1NOC_SNOC_SLV 1
-#define SM7150_A2NOC_SNOC_MAS 2
-#define SM7150_A2NOC_SNOC_SLV 3
-#define SM7150_MASTER_A1NOC_CFG 4
-#define SM7150_MASTER_A2NOC_CFG 5
-#define SM7150_MASTER_AMPSS_M0 6
-#define SM7150_MASTER_CAMNOC_HF0 7
-#define SM7150_MASTER_CAMNOC_HF0_UNCOMP 8
-#define SM7150_MASTER_CAMNOC_NRT 9
-#define SM7150_MASTER_CAMNOC_NRT_UNCOMP 10
-#define SM7150_MASTER_CAMNOC_RT 11
-#define SM7150_MASTER_CAMNOC_RT_UNCOMP 12
-#define SM7150_MASTER_CAMNOC_SF 13
-#define SM7150_MASTER_CAMNOC_SF_UNCOMP 14
-#define SM7150_MASTER_CNOC_A2NOC 15
-#define SM7150_MASTER_CNOC_DC_NOC 16
-#define SM7150_MASTER_CNOC_MNOC_CFG 17
-#define SM7150_MASTER_COMPUTE_NOC 18
-#define SM7150_MASTER_CRYPTO_CORE_0 19
-#define SM7150_MASTER_EMMC 20
-#define SM7150_MASTER_GEM_NOC_CFG 21
-#define SM7150_MASTER_GEM_NOC_PCIE_SNOC 22
-#define SM7150_MASTER_GEM_NOC_SNOC 23
-#define SM7150_MASTER_GIC 24
-#define SM7150_MASTER_GRAPHICS_3D 25
-#define SM7150_MASTER_IPA 26
-#define SM7150_MASTER_LLCC 27
-#define SM7150_MASTER_MDP_PORT0 28
-#define SM7150_MASTER_MDP_PORT1 29
-#define SM7150_MASTER_MNOC_HF_MEM_NOC 30
-#define SM7150_MASTER_MNOC_SF_MEM_NOC 31
-#define SM7150_MASTER_NPU 32
-#define SM7150_MASTER_PCIE 33
-#define SM7150_MASTER_PIMEM 34
-#define SM7150_MASTER_QDSS_BAM 35
-#define SM7150_MASTER_QDSS_DAP 36
-#define SM7150_MASTER_QDSS_ETR 37
-#define SM7150_MASTER_QUP_0 38
-#define SM7150_MASTER_QUP_1 39
-#define SM7150_MASTER_ROTATOR 40
-#define SM7150_MASTER_SDCC_2 41
-#define SM7150_MASTER_SDCC_4 42
-#define SM7150_MASTER_SNOC_CFG 43
-#define SM7150_MASTER_SNOC_GC_MEM_NOC 44
-#define SM7150_MASTER_SNOC_SF_MEM_NOC 45
-#define SM7150_MASTER_SPDM 46
-#define SM7150_MASTER_SYS_TCU 47
-#define SM7150_MASTER_TSIF 48
-#define SM7150_MASTER_UFS_MEM 49
-#define SM7150_MASTER_USB3 50
-#define SM7150_MASTER_VIDEO_P0 51
-#define SM7150_MASTER_VIDEO_P1 52
-#define SM7150_MASTER_VIDEO_PROC 53
-#define SM7150_SLAVE_A1NOC_CFG 54
-#define SM7150_SLAVE_A2NOC_CFG 55
-#define SM7150_SLAVE_AHB2PHY_NORTH 56
-#define SM7150_SLAVE_AHB2PHY_SOUTH 57
-#define SM7150_SLAVE_AHB2PHY_WEST 58
-#define SM7150_SLAVE_ANOC_PCIE_GEM_NOC 59
-#define SM7150_SLAVE_AOP 60
-#define SM7150_SLAVE_AOSS 61
-#define SM7150_SLAVE_APPSS 62
-#define SM7150_SLAVE_CAMERA_CFG 63
-#define SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG 64
-#define SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG 65
-#define SM7150_SLAVE_CAMNOC_UNCOMP 66
-#define SM7150_SLAVE_CDSP_CFG 67
-#define SM7150_SLAVE_CDSP_GEM_NOC 68
-#define SM7150_SLAVE_CLK_CTL 69
-#define SM7150_SLAVE_CNOC_A2NOC 70
-#define SM7150_SLAVE_CNOC_DDRSS 71
-#define SM7150_SLAVE_CNOC_MNOC_CFG 72
-#define SM7150_SLAVE_CRYPTO_0_CFG 73
-#define SM7150_SLAVE_DISPLAY_CFG 74
-#define SM7150_SLAVE_DISPLAY_THROTTLE_CFG 75
-#define SM7150_SLAVE_EBI_CH0 76
-#define SM7150_SLAVE_EMMC_CFG 77
-#define SM7150_SLAVE_GEM_NOC_CFG 78
-#define SM7150_SLAVE_GEM_NOC_SNOC 79
-#define SM7150_SLAVE_GLM 80
-#define SM7150_SLAVE_GRAPHICS_3D_CFG 81
-#define SM7150_SLAVE_IMEM_CFG 82
-#define SM7150_SLAVE_IPA_CFG 83
-#define SM7150_SLAVE_LLCC 84
-#define SM7150_SLAVE_LLCC_CFG 85
-#define SM7150_SLAVE_MNOC_HF_MEM_NOC 86
-#define SM7150_SLAVE_MNOC_SF_MEM_NOC 87
-#define SM7150_SLAVE_MSS_PROC_MS_MPU_CFG 88
-#define SM7150_SLAVE_OCIMEM 89
-#define SM7150_SLAVE_PCIE_CFG 90
-#define SM7150_SLAVE_PDM 91
-#define SM7150_SLAVE_PIMEM 92
-#define SM7150_SLAVE_PIMEM_CFG 93
-#define SM7150_SLAVE_PRNG 94
-#define SM7150_SLAVE_QDSS_CFG 95
-#define SM7150_SLAVE_QDSS_STM 96
-#define SM7150_SLAVE_QUP_0 97
-#define SM7150_SLAVE_QUP_1 98
-#define SM7150_SLAVE_RBCPR_CX_CFG 99
-#define SM7150_SLAVE_RBCPR_MX_CFG 100
-#define SM7150_SLAVE_SDCC_2 101
-#define SM7150_SLAVE_SDCC_4 102
-#define SM7150_SLAVE_SERVICE_A1NOC 103
-#define SM7150_SLAVE_SERVICE_A2NOC 104
-#define SM7150_SLAVE_SERVICE_CNOC 105
-#define SM7150_SLAVE_SERVICE_GEM_NOC 106
-#define SM7150_SLAVE_SERVICE_MNOC 107
-#define SM7150_SLAVE_SERVICE_SNOC 108
-#define SM7150_SLAVE_SNOC_CFG 109
-#define SM7150_SLAVE_SNOC_GEM_NOC_GC 110
-#define SM7150_SLAVE_SNOC_GEM_NOC_SF 111
-#define SM7150_SLAVE_SPDM_WRAPPER 112
-#define SM7150_SLAVE_TCSR 113
-#define SM7150_SLAVE_TCU 114
-#define SM7150_SLAVE_TLMM_NORTH 115
-#define SM7150_SLAVE_TLMM_SOUTH 116
-#define SM7150_SLAVE_TLMM_WEST 117
-#define SM7150_SLAVE_TSIF 118
-#define SM7150_SLAVE_UFS_MEM_CFG 119
-#define SM7150_SLAVE_USB3 120
-#define SM7150_SLAVE_VENUS_CFG 121
-#define SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG 122
-#define SM7150_SLAVE_VENUS_THROTTLE_CFG 123
-#define SM7150_SLAVE_VSENSE_CTRL_CFG 124
-#define SM7150_SNOC_CNOC_MAS 125
-#define SM7150_SNOC_CNOC_SLV 126
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 22/28] interconnect: qcom: sm8150: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (20 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 21/28] interconnect: qcom: sm7150: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 23/28] interconnect: qcom: sm8350: " Dmitry Baryshkov
` (6 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm8150.c | 854 ++++++++++++++++++-------------------
drivers/interconnect/qcom/sm8150.h | 152 -------
2 files changed, 417 insertions(+), 589 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c
index c5dc5b55ae564683dd169de621fffcd7449a70f5..a545e780cacd77b0e8834c879d62c1fc1b3a433d 100644
--- a/drivers/interconnect/qcom/sm8150.c
+++ b/drivers/interconnect/qcom/sm8150.c
@@ -14,1270 +14,1240 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sm8150.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node xm_emac;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node xm_usb3_1;
+static struct qcom_icc_node qhm_a2noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qhm_sensorss_ahb;
+static struct qcom_icc_node qhm_tsif;
+static struct qcom_icc_node qnm_cnoc;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node qxm_camnoc_hf1_uncomp;
+static struct qcom_icc_node qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node qnm_npu;
+static struct qcom_icc_node qhm_spdm;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qhm_cnoc_dc_noc;
+static struct qcom_icc_node acm_apps;
+static struct qcom_icc_node acm_gpu_tcu;
+static struct qcom_icc_node acm_sys_tcu;
+static struct qcom_icc_node qhm_gemnoc_cfg;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_ecc;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qxm_camnoc_hf0;
+static struct qcom_icc_node qxm_camnoc_hf1;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_mdp1;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node qxm_venus0;
+static struct qcom_icc_node qxm_venus1;
+static struct qcom_icc_node qxm_venus_arm9;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gemnoc;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_camnoc_uncomp;
+static struct qcom_icc_node qns_cdsp_mem_noc;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_a2_noc_cfg;
+static struct qcom_icc_node qhs_ahb2phy_south;
+static struct qcom_icc_node qhs_aop;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_dsp;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_emac_cfg;
+static struct qcom_icc_node qhs_glm;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_npu_cfg;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_phy_refgen_north;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qupv3_east;
+static struct qcom_icc_node qhs_qupv3_north;
+static struct qcom_icc_node qhs_qupv3_south;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_spdm;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_ssc_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm_east;
+static struct qcom_icc_node qhs_tlmm_north;
+static struct qcom_icc_node qhs_tlmm_south;
+static struct qcom_icc_node qhs_tlmm_west;
+static struct qcom_icc_node qhs_tsif;
+static struct qcom_icc_node qhs_ufs_card_cfg;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_usb3_1;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_memnoc;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qns_ecc;
+static struct qcom_icc_node qns_gem_noc_snoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node srvc_gemnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns2_mem_noc;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qhm_a1noc_cfg = {
.name = "qhm_a1noc_cfg",
- .id = SM8150_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SM8150_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_emac = {
.name = "xm_emac",
- .id = SM8150_MASTER_EMAC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM8150_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM8150_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
- .id = SM8150_MASTER_USB3_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_a2noc_cfg = {
.name = "qhm_a2noc_cfg",
- .id = SM8150_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM8150_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SM8150_MASTER_QSPI,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SM8150_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SM8150_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_sensorss_ahb = {
.name = "qhm_sensorss_ahb",
- .id = SM8150_MASTER_SENSORS_AHB,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_tsif = {
.name = "qhm_tsif",
- .id = SM8150_MASTER_TSIF,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
- .id = SM8150_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM8150_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM8150_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM8150_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SM8150_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SM8150_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM8150_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM8150_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
.name = "qxm_camnoc_hf0_uncomp",
- .id = SM8150_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
.name = "qxm_camnoc_hf1_uncomp",
- .id = SM8150_MASTER_CAMNOC_HF1_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
.name = "qxm_camnoc_sf_uncomp",
- .id = SM8150_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp, NULL },
};
static struct qcom_icc_node qnm_npu = {
.name = "qnm_npu",
- .id = SM8150_MASTER_NPU,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_cdsp_mem_noc, NULL },
};
static struct qcom_icc_node qhm_spdm = {
.name = "qhm_spdm",
- .id = SM8150_MASTER_SPDM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_SLAVE_CNOC_A2NOC },
+ .link_nodes = { &qns_cnoc_a2noc, NULL },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = SM8150_SNOC_CNOC_MAS,
.channels = 1,
.buswidth = 8,
- .num_links = 50,
- .links = { SM8150_SLAVE_TLMM_SOUTH,
- SM8150_SLAVE_CDSP_CFG,
- SM8150_SLAVE_SPSS_CFG,
- SM8150_SLAVE_CAMERA_CFG,
- SM8150_SLAVE_SDCC_4,
- SM8150_SLAVE_SDCC_2,
- SM8150_SLAVE_CNOC_MNOC_CFG,
- SM8150_SLAVE_EMAC_CFG,
- SM8150_SLAVE_UFS_MEM_CFG,
- SM8150_SLAVE_TLMM_EAST,
- SM8150_SLAVE_SSC_CFG,
- SM8150_SLAVE_SNOC_CFG,
- SM8150_SLAVE_NORTH_PHY_CFG,
- SM8150_SLAVE_QUP_0,
- SM8150_SLAVE_GLM,
- SM8150_SLAVE_PCIE_1_CFG,
- SM8150_SLAVE_A2NOC_CFG,
- SM8150_SLAVE_QDSS_CFG,
- SM8150_SLAVE_DISPLAY_CFG,
- SM8150_SLAVE_TCSR,
- SM8150_SLAVE_CNOC_DDRSS,
- SM8150_SLAVE_RBCPR_MMCX_CFG,
- SM8150_SLAVE_NPU_CFG,
- SM8150_SLAVE_PCIE_0_CFG,
- SM8150_SLAVE_GRAPHICS_3D_CFG,
- SM8150_SLAVE_VENUS_CFG,
- SM8150_SLAVE_TSIF,
- SM8150_SLAVE_IPA_CFG,
- SM8150_SLAVE_CLK_CTL,
- SM8150_SLAVE_AOP,
- SM8150_SLAVE_QUP_1,
- SM8150_SLAVE_AHB2PHY_SOUTH,
- SM8150_SLAVE_USB3_1,
- SM8150_SLAVE_SERVICE_CNOC,
- SM8150_SLAVE_UFS_CARD_CFG,
- SM8150_SLAVE_QUP_2,
- SM8150_SLAVE_RBCPR_CX_CFG,
- SM8150_SLAVE_TLMM_WEST,
- SM8150_SLAVE_A1NOC_CFG,
- SM8150_SLAVE_AOSS,
- SM8150_SLAVE_PRNG,
- SM8150_SLAVE_VSENSE_CTRL_CFG,
- SM8150_SLAVE_QSPI,
- SM8150_SLAVE_USB3,
- SM8150_SLAVE_SPDM_WRAPPER,
- SM8150_SLAVE_CRYPTO_0_CFG,
- SM8150_SLAVE_PIMEM_CFG,
- SM8150_SLAVE_TLMM_NORTH,
- SM8150_SLAVE_RBCPR_MX_CFG,
- SM8150_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_tlmm_south,
+ &qhs_compute_dsp,
+ &qhs_spss_cfg,
+ &qhs_camera_cfg,
+ &qhs_sdc4,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_emac_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_tlmm_east,
+ &qhs_ssc_cfg,
+ &qhs_snoc_cfg,
+ &qhs_phy_refgen_north,
+ &qhs_qupv3_south,
+ &qhs_glm,
+ &qhs_pcie1_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_display_cfg,
+ &qhs_tcsr,
+ &qhs_ddrss_cfg,
+ &qhs_cpr_mmcx,
+ &qhs_npu_cfg,
+ &qhs_pcie0_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_ipa,
+ &qhs_clk_ctl,
+ &qhs_aop,
+ &qhs_qupv3_north,
+ &qhs_ahb2phy_south,
+ &qhs_usb3_1,
+ &srvc_cnoc,
+ &qhs_ufs_card_cfg,
+ &qhs_qupv3_east,
+ &qhs_cpr_cx,
+ &qhs_tlmm_west,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_qspi,
+ &qhs_usb3_0,
+ &qhs_spdm,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_tlmm_north,
+ &qhs_cpr_mx,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SM8150_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 51,
- .links = { SM8150_SLAVE_TLMM_SOUTH,
- SM8150_SLAVE_CDSP_CFG,
- SM8150_SLAVE_SPSS_CFG,
- SM8150_SLAVE_CAMERA_CFG,
- SM8150_SLAVE_SDCC_4,
- SM8150_SLAVE_SDCC_2,
- SM8150_SLAVE_CNOC_MNOC_CFG,
- SM8150_SLAVE_EMAC_CFG,
- SM8150_SLAVE_UFS_MEM_CFG,
- SM8150_SLAVE_TLMM_EAST,
- SM8150_SLAVE_SSC_CFG,
- SM8150_SLAVE_SNOC_CFG,
- SM8150_SLAVE_NORTH_PHY_CFG,
- SM8150_SLAVE_QUP_0,
- SM8150_SLAVE_GLM,
- SM8150_SLAVE_PCIE_1_CFG,
- SM8150_SLAVE_A2NOC_CFG,
- SM8150_SLAVE_QDSS_CFG,
- SM8150_SLAVE_DISPLAY_CFG,
- SM8150_SLAVE_TCSR,
- SM8150_SLAVE_CNOC_DDRSS,
- SM8150_SLAVE_CNOC_A2NOC,
- SM8150_SLAVE_RBCPR_MMCX_CFG,
- SM8150_SLAVE_NPU_CFG,
- SM8150_SLAVE_PCIE_0_CFG,
- SM8150_SLAVE_GRAPHICS_3D_CFG,
- SM8150_SLAVE_VENUS_CFG,
- SM8150_SLAVE_TSIF,
- SM8150_SLAVE_IPA_CFG,
- SM8150_SLAVE_CLK_CTL,
- SM8150_SLAVE_AOP,
- SM8150_SLAVE_QUP_1,
- SM8150_SLAVE_AHB2PHY_SOUTH,
- SM8150_SLAVE_USB3_1,
- SM8150_SLAVE_SERVICE_CNOC,
- SM8150_SLAVE_UFS_CARD_CFG,
- SM8150_SLAVE_QUP_2,
- SM8150_SLAVE_RBCPR_CX_CFG,
- SM8150_SLAVE_TLMM_WEST,
- SM8150_SLAVE_A1NOC_CFG,
- SM8150_SLAVE_AOSS,
- SM8150_SLAVE_PRNG,
- SM8150_SLAVE_VSENSE_CTRL_CFG,
- SM8150_SLAVE_QSPI,
- SM8150_SLAVE_USB3,
- SM8150_SLAVE_SPDM_WRAPPER,
- SM8150_SLAVE_CRYPTO_0_CFG,
- SM8150_SLAVE_PIMEM_CFG,
- SM8150_SLAVE_TLMM_NORTH,
- SM8150_SLAVE_RBCPR_MX_CFG,
- SM8150_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_tlmm_south,
+ &qhs_compute_dsp,
+ &qhs_spss_cfg,
+ &qhs_camera_cfg,
+ &qhs_sdc4,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_emac_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_tlmm_east,
+ &qhs_ssc_cfg,
+ &qhs_snoc_cfg,
+ &qhs_phy_refgen_north,
+ &qhs_qupv3_south,
+ &qhs_glm,
+ &qhs_pcie1_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_display_cfg,
+ &qhs_tcsr,
+ &qhs_ddrss_cfg,
+ &qns_cnoc_a2noc,
+ &qhs_cpr_mmcx,
+ &qhs_npu_cfg,
+ &qhs_pcie0_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_ipa,
+ &qhs_clk_ctl,
+ &qhs_aop,
+ &qhs_qupv3_north,
+ &qhs_ahb2phy_south,
+ &qhs_usb3_1,
+ &srvc_cnoc,
+ &qhs_ufs_card_cfg,
+ &qhs_qupv3_east,
+ &qhs_cpr_cx,
+ &qhs_tlmm_west,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_qspi,
+ &qhs_usb3_0,
+ &qhs_spdm,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_tlmm_north,
+ &qhs_cpr_mx,
+ &qhs_imem_cfg, NULL },
};
static struct qcom_icc_node qhm_cnoc_dc_noc = {
.name = "qhm_cnoc_dc_noc",
- .id = SM8150_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SM8150_SLAVE_GEM_NOC_CFG,
- SM8150_SLAVE_LLCC_CFG
- },
+ .link_nodes = { &qhs_memnoc,
+ &qhs_llcc, NULL },
};
static struct qcom_icc_node acm_apps = {
.name = "acm_apps",
- .id = SM8150_MASTER_AMPSS_M0,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8150_SLAVE_ECC,
- SM8150_SLAVE_LLCC,
- SM8150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_ecc,
+ &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node acm_gpu_tcu = {
.name = "acm_gpu_tcu",
- .id = SM8150_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8150_SLAVE_LLCC,
- SM8150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node acm_sys_tcu = {
.name = "acm_sys_tcu",
- .id = SM8150_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8150_SLAVE_LLCC,
- SM8150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qhm_gemnoc_cfg = {
.name = "qhm_gemnoc_cfg",
- .id = SM8150_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SM8150_SLAVE_SERVICE_GEM_NOC,
- SM8150_SLAVE_MSS_PROC_MS_MPU_CFG
- },
+ .link_nodes = { &srvc_gemnoc,
+ &qhs_mdsp_ms_mpu_cfg, NULL },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SM8150_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8150_SLAVE_ECC,
- SM8150_SLAVE_LLCC,
- SM8150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_ecc,
+ &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SM8150_MASTER_GRAPHICS_3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8150_SLAVE_LLCC,
- SM8150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM8150_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM8150_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8150_SLAVE_LLCC,
- SM8150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM8150_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM8150_SLAVE_LLCC,
- SM8150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM8150_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM8150_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qxm_ecc = {
.name = "qxm_ecc",
- .id = SM8150_MASTER_ECC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM8150_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_SLAVE_EBI_CH0 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = SM8150_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf0 = {
.name = "qxm_camnoc_hf0",
- .id = SM8150_MASTER_CAMNOC_HF0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_hf1 = {
.name = "qxm_camnoc_hf1",
- .id = SM8150_MASTER_CAMNOC_HF1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SM8150_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SM8150_MASTER_MDP_PORT0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_mdp1 = {
.name = "qxm_mdp1",
- .id = SM8150_MASTER_MDP_PORT1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = SM8150_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus0 = {
.name = "qxm_venus0",
- .id = SM8150_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus1 = {
.name = "qxm_venus1",
- .id = SM8150_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qxm_venus_arm9 = {
.name = "qxm_venus_arm9",
- .id = SM8150_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc, NULL },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SM8150_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM8150_A1NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF,
- SM8150_SLAVE_PIMEM,
- SM8150_SLAVE_OCIMEM,
- SM8150_SLAVE_APPSS,
- SM8150_SNOC_CNOC_SLV,
- SM8150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qns_gemnoc_sf,
+ &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM8150_A2NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
- .num_links = 9,
- .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF,
- SM8150_SLAVE_PIMEM,
- SM8150_SLAVE_OCIMEM,
- SM8150_SLAVE_APPSS,
- SM8150_SNOC_CNOC_SLV,
- SM8150_SLAVE_PCIE_0,
- SM8150_SLAVE_PCIE_1,
- SM8150_SLAVE_TCU,
- SM8150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qns_gemnoc_sf,
+ &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_pcie_0,
+ &xs_pcie_1,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qnm_gemnoc = {
.name = "qnm_gemnoc",
- .id = SM8150_MASTER_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 6,
- .links = { SM8150_SLAVE_PIMEM,
- SM8150_SLAVE_OCIMEM,
- SM8150_SLAVE_APPSS,
- SM8150_SNOC_CNOC_SLV,
- SM8150_SLAVE_TCU,
- SM8150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SM8150_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC,
- SM8150_SLAVE_OCIMEM
- },
+ .link_nodes = { &qns_gemnoc_gc,
+ &qxs_imem, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM8150_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC,
- SM8150_SLAVE_OCIMEM
- },
+ .link_nodes = { &qns_gemnoc_gc,
+ &qxs_imem, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM8150_A1NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8150_A1NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SM8150_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM8150_A2NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8150_A2NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SM8150_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8150_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SM8150_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_camnoc_uncomp = {
.name = "qns_camnoc_uncomp",
- .id = SM8150_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cdsp_mem_noc = {
.name = "qns_cdsp_mem_noc",
- .id = SM8150_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = SM8150_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qhs_a2_noc_cfg = {
.name = "qhs_a2_noc_cfg",
- .id = SM8150_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_MASTER_A2NOC_CFG },
+ .link_nodes = { &qhm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qhs_ahb2phy_south = {
.name = "qhs_ahb2phy_south",
- .id = SM8150_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
- .id = SM8150_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM8150_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM8150_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM8150_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_dsp = {
.name = "qhs_compute_dsp",
- .id = SM8150_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM8150_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SM8150_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SM8150_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM8150_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SM8150_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc_dc_noc, NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM8150_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_emac_cfg = {
.name = "qhs_emac_cfg",
- .id = SM8150_SLAVE_EMAC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_glm = {
.name = "qhs_glm",
- .id = SM8150_SLAVE_GLM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM8150_SLAVE_GRAPHICS_3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM8150_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM8150_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = SM8150_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_npu_cfg = {
.name = "qhs_npu_cfg",
- .id = SM8150_SLAVE_NPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SM8150_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SM8150_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_phy_refgen_north = {
.name = "qhs_phy_refgen_north",
- .id = SM8150_SLAVE_NORTH_PHY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM8150_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM8150_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM8150_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SM8150_SLAVE_QSPI,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_east = {
.name = "qhs_qupv3_east",
- .id = SM8150_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_north = {
.name = "qhs_qupv3_north",
- .id = SM8150_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qupv3_south = {
.name = "qhs_qupv3_south",
- .id = SM8150_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM8150_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM8150_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SM8150_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg, NULL },
};
static struct qcom_icc_node qhs_spdm = {
.name = "qhs_spdm",
- .id = SM8150_SLAVE_SPDM_WRAPPER,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SM8150_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ssc_cfg = {
.name = "qhs_ssc_cfg",
- .id = SM8150_SLAVE_SSC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM8150_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_east = {
.name = "qhs_tlmm_east",
- .id = SM8150_SLAVE_TLMM_EAST,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_north = {
.name = "qhs_tlmm_north",
- .id = SM8150_SLAVE_TLMM_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_south = {
.name = "qhs_tlmm_south",
- .id = SM8150_SLAVE_TLMM_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm_west = {
.name = "qhs_tlmm_west",
- .id = SM8150_SLAVE_TLMM_WEST,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tsif = {
.name = "qhs_tsif",
- .id = SM8150_SLAVE_TSIF,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_card_cfg = {
.name = "qhs_ufs_card_cfg",
- .id = SM8150_SLAVE_UFS_CARD_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM8150_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM8150_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_1 = {
.name = "qhs_usb3_1",
- .id = SM8150_SLAVE_USB3_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM8150_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM8150_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = SM8150_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc, NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SM8150_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SM8150_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_memnoc = {
.name = "qhs_memnoc",
- .id = SM8150_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8150_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qhm_gemnoc_cfg, NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SM8150_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_ecc = {
.name = "qns_ecc",
- .id = SM8150_SLAVE_ECC,
.channels = 1,
.buswidth = 32,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_snoc = {
.name = "qns_gem_noc_snoc",
- .id = SM8150_SLAVE_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_MASTER_GEM_NOC_SNOC },
+ .link_nodes = { &qnm_gemnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM8150_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8150_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node srvc_gemnoc = {
.name = "srvc_gemnoc",
- .id = SM8150_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM8150_SLAVE_EBI_CH0,
.channels = 4,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns2_mem_noc = {
.name = "qns2_mem_noc",
- .id = SM8150_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM8150_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8150_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM8150_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SM8150_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = SM8150_SNOC_CNOC_SLV,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_SNOC_CNOC_MAS },
+ .link_nodes = { &qnm_snoc, NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM8150_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8150_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM8150_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8150_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM8150_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SM8150_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SM8150_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SM8150_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SM8150_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM8150_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM8150_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1524,6 +1494,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1559,6 +1530,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1577,6 +1549,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8150_camnoc_virt = {
+ .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1594,6 +1567,7 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_compute_noc = {
+ .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1662,6 +1636,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1678,6 +1653,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1713,6 +1689,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1730,6 +1707,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8150_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1760,6 +1738,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1801,6 +1780,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom/sm8150.h
deleted file mode 100644
index 1d587c94eb06e1b06b0dcd582807b87aa59af075..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm8150.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm #define SM8250 interconnect IDs
- *
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8150_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM8150_H
-
-#define SM8150_A1NOC_SNOC_MAS 0
-#define SM8150_A1NOC_SNOC_SLV 1
-#define SM8150_A2NOC_SNOC_MAS 2
-#define SM8150_A2NOC_SNOC_SLV 3
-#define SM8150_MASTER_A1NOC_CFG 4
-#define SM8150_MASTER_A2NOC_CFG 5
-#define SM8150_MASTER_AMPSS_M0 6
-#define SM8150_MASTER_CAMNOC_HF0 7
-#define SM8150_MASTER_CAMNOC_HF0_UNCOMP 8
-#define SM8150_MASTER_CAMNOC_HF1 9
-#define SM8150_MASTER_CAMNOC_HF1_UNCOMP 10
-#define SM8150_MASTER_CAMNOC_SF 11
-#define SM8150_MASTER_CAMNOC_SF_UNCOMP 12
-#define SM8150_MASTER_CNOC_A2NOC 13
-#define SM8150_MASTER_CNOC_DC_NOC 14
-#define SM8150_MASTER_CNOC_MNOC_CFG 15
-#define SM8150_MASTER_COMPUTE_NOC 16
-#define SM8150_MASTER_CRYPTO_CORE_0 17
-#define SM8150_MASTER_ECC 18
-#define SM8150_MASTER_EMAC 19
-#define SM8150_MASTER_GEM_NOC_CFG 20
-#define SM8150_MASTER_GEM_NOC_PCIE_SNOC 21
-#define SM8150_MASTER_GEM_NOC_SNOC 22
-#define SM8150_MASTER_GIC 23
-#define SM8150_MASTER_GPU_TCU 24
-#define SM8150_MASTER_GRAPHICS_3D 25
-#define SM8150_MASTER_IPA 26
-/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
-#define SM8150_MASTER_LLCC 28
-#define SM8150_MASTER_MDP_PORT0 29
-#define SM8150_MASTER_MDP_PORT1 30
-#define SM8150_MASTER_MNOC_HF_MEM_NOC 31
-#define SM8150_MASTER_MNOC_SF_MEM_NOC 32
-#define SM8150_MASTER_NPU 33
-#define SM8150_MASTER_PCIE 34
-#define SM8150_MASTER_PCIE_1 35
-#define SM8150_MASTER_PIMEM 36
-#define SM8150_MASTER_QDSS_BAM 37
-#define SM8150_MASTER_QDSS_DAP 38
-#define SM8150_MASTER_QDSS_ETR 39
-#define SM8150_MASTER_QSPI 40
-#define SM8150_MASTER_QUP_0 41
-#define SM8150_MASTER_QUP_1 42
-#define SM8150_MASTER_QUP_2 43
-#define SM8150_MASTER_ROTATOR 44
-#define SM8150_MASTER_SDCC_2 45
-#define SM8150_MASTER_SDCC_4 46
-#define SM8150_MASTER_SENSORS_AHB 47
-#define SM8150_MASTER_SNOC_CFG 48
-#define SM8150_MASTER_SNOC_GC_MEM_NOC 49
-#define SM8150_MASTER_SNOC_SF_MEM_NOC 50
-#define SM8150_MASTER_SPDM 51
-#define SM8150_MASTER_SYS_TCU 52
-#define SM8150_MASTER_TSIF 53
-#define SM8150_MASTER_UFS_MEM 54
-#define SM8150_MASTER_USB3 55
-#define SM8150_MASTER_USB3_1 56
-#define SM8150_MASTER_VIDEO_P0 57
-#define SM8150_MASTER_VIDEO_P1 58
-#define SM8150_MASTER_VIDEO_PROC 59
-#define SM8150_SLAVE_A1NOC_CFG 60
-#define SM8150_SLAVE_A2NOC_CFG 61
-#define SM8150_SLAVE_AHB2PHY_SOUTH 62
-#define SM8150_SLAVE_ANOC_PCIE_GEM_NOC 63
-#define SM8150_SLAVE_AOP 64
-#define SM8150_SLAVE_AOSS 65
-#define SM8150_SLAVE_APPSS 66
-#define SM8150_SLAVE_CAMERA_CFG 67
-#define SM8150_SLAVE_CAMNOC_UNCOMP 68
-#define SM8150_SLAVE_CDSP_CFG 69
-#define SM8150_SLAVE_CDSP_MEM_NOC 70
-#define SM8150_SLAVE_CLK_CTL 71
-#define SM8150_SLAVE_CNOC_A2NOC 72
-#define SM8150_SLAVE_CNOC_DDRSS 73
-#define SM8150_SLAVE_CNOC_MNOC_CFG 74
-#define SM8150_SLAVE_CRYPTO_0_CFG 75
-#define SM8150_SLAVE_DISPLAY_CFG 76
-#define SM8150_SLAVE_EBI_CH0 77
-#define SM8150_SLAVE_ECC 78
-#define SM8150_SLAVE_EMAC_CFG 79
-#define SM8150_SLAVE_GEM_NOC_CFG 80
-#define SM8150_SLAVE_GEM_NOC_SNOC 81
-#define SM8150_SLAVE_GLM 82
-#define SM8150_SLAVE_GRAPHICS_3D_CFG 83
-#define SM8150_SLAVE_IMEM_CFG 84
-#define SM8150_SLAVE_IPA_CFG 85
-/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
-#define SM8150_SLAVE_LLCC 87
-#define SM8150_SLAVE_LLCC_CFG 88
-#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89
-#define SM8150_SLAVE_MNOC_SF_MEM_NOC 90
-#define SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 91
-#define SM8150_SLAVE_NORTH_PHY_CFG 92
-#define SM8150_SLAVE_NPU_CFG 93
-#define SM8150_SLAVE_OCIMEM 94
-#define SM8150_SLAVE_PCIE_0 95
-#define SM8150_SLAVE_PCIE_0_CFG 96
-#define SM8150_SLAVE_PCIE_1 97
-#define SM8150_SLAVE_PCIE_1_CFG 98
-#define SM8150_SLAVE_PIMEM 99
-#define SM8150_SLAVE_PIMEM_CFG 100
-#define SM8150_SLAVE_PRNG 101
-#define SM8150_SLAVE_QDSS_CFG 102
-#define SM8150_SLAVE_QDSS_STM 103
-#define SM8150_SLAVE_QSPI 104
-#define SM8150_SLAVE_QUP_0 105
-#define SM8150_SLAVE_QUP_1 106
-#define SM8150_SLAVE_QUP_2 107
-#define SM8150_SLAVE_RBCPR_CX_CFG 108
-#define SM8150_SLAVE_RBCPR_MMCX_CFG 109
-#define SM8150_SLAVE_RBCPR_MX_CFG 110
-#define SM8150_SLAVE_SDCC_2 111
-#define SM8150_SLAVE_SDCC_4 112
-#define SM8150_SLAVE_SERVICE_A1NOC 113
-#define SM8150_SLAVE_SERVICE_A2NOC 114
-#define SM8150_SLAVE_SERVICE_CNOC 115
-#define SM8150_SLAVE_SERVICE_GEM_NOC 116
-#define SM8150_SLAVE_SERVICE_MNOC 117
-#define SM8150_SLAVE_SERVICE_SNOC 118
-#define SM8150_SLAVE_SNOC_CFG 119
-#define SM8150_SLAVE_SNOC_GEM_NOC_GC 120
-#define SM8150_SLAVE_SNOC_GEM_NOC_SF 121
-#define SM8150_SLAVE_SPDM_WRAPPER 122
-#define SM8150_SLAVE_SPSS_CFG 123
-#define SM8150_SLAVE_SSC_CFG 124
-#define SM8150_SLAVE_TCSR 125
-#define SM8150_SLAVE_TCU 126
-#define SM8150_SLAVE_TLMM_EAST 127
-#define SM8150_SLAVE_TLMM_NORTH 128
-#define SM8150_SLAVE_TLMM_SOUTH 129
-#define SM8150_SLAVE_TLMM_WEST 130
-#define SM8150_SLAVE_TSIF 131
-#define SM8150_SLAVE_UFS_CARD_CFG 132
-#define SM8150_SLAVE_UFS_MEM_CFG 133
-#define SM8150_SLAVE_USB3 134
-#define SM8150_SLAVE_USB3_1 135
-#define SM8150_SLAVE_VENUS_CFG 136
-#define SM8150_SLAVE_VSENSE_CTRL_CFG 137
-#define SM8150_SNOC_CNOC_MAS 138
-#define SM8150_SNOC_CNOC_SLV 139
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 23/28] interconnect: qcom: sm8350: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (21 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 22/28] interconnect: qcom: sm8150: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 24/28] interconnect: qcom: sm8450: " Dmitry Baryshkov
` (5 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm8350.c | 834 +++++++++++++++++++------------------
drivers/interconnect/qcom/sm8350.h | 158 -------
2 files changed, 422 insertions(+), 570 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c
index 3fa17b5786b726a8a61c347f9e2bb61dc0709546..d268bb68b18cd7e9b06bd060f905b4f22e565e5e 100644
--- a/drivers/interconnect/qcom/sm8350.c
+++ b/drivers/interconnect/qcom/sm8350.c
@@ -13,1257 +13,1257 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sm8350.h"
+
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qnm_a1noc_cfg;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node xm_usb3_1;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qnm_a2noc_cfg;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_ufs_card;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qnm_cnoc_dc_noc;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_gemnoc_cfg;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qhm_config_noc;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_mnoc_cfg;
+static struct qcom_icc_node qnm_video0;
+static struct qcom_icc_node qnm_video1;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_mdp1;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node qhm_nsp_noc_config;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_snoc_cfg;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_hwkm;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_pka_wrapper_cfg;
+static struct qcom_icc_node qhs_pmu_wrapper_cfg;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_security;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_card_cfg;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_usb3_1;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_a1_noc_cfg;
+static struct qcom_icc_node qns_a2_noc_cfg;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qns_mnoc_cfg;
+static struct qcom_icc_node qns_snoc_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qns_gemnoc;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qhs_modem_ms_mpu_cfg;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node srvc_even_gemnoc;
+static struct qcom_icc_node srvc_odd_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc;
+static struct qcom_icc_node qhs_lpass_core;
+static struct qcom_icc_node qhs_lpass_lpi;
+static struct qcom_icc_node qhs_lpass_mpu;
+static struct qcom_icc_node qhs_lpass_top;
+static struct qcom_icc_node srvc_niu_aml_noc;
+static struct qcom_icc_node srvc_niu_lpass_agnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node service_nsp_noc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node srvc_snoc;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SM8350_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SM8350_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SM8350_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SM8350_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_a1noc_cfg = {
.name = "qnm_a1noc_cfg",
- .id = SM8350_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM8350_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM8350_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM8350_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
- .id = SM8350_MASTER_USB3_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM8350_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_a2noc_cfg = {
.name = "qnm_a2noc_cfg",
- .id = SM8350_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM8350_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM8350_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM8350_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SM8350_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SM8350_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM8350_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_card = {
.name = "xm_ufs_card",
- .id = SM8350_MASTER_UFS_CARD,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SM8350_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 56,
- .links = { SM8350_SLAVE_AHB2PHY_SOUTH,
- SM8350_SLAVE_AHB2PHY_NORTH,
- SM8350_SLAVE_AOSS,
- SM8350_SLAVE_APPSS,
- SM8350_SLAVE_CAMERA_CFG,
- SM8350_SLAVE_CLK_CTL,
- SM8350_SLAVE_CDSP_CFG,
- SM8350_SLAVE_RBCPR_CX_CFG,
- SM8350_SLAVE_RBCPR_MMCX_CFG,
- SM8350_SLAVE_RBCPR_MX_CFG,
- SM8350_SLAVE_CRYPTO_0_CFG,
- SM8350_SLAVE_CX_RDPM,
- SM8350_SLAVE_DCC_CFG,
- SM8350_SLAVE_DISPLAY_CFG,
- SM8350_SLAVE_GFX3D_CFG,
- SM8350_SLAVE_HWKM,
- SM8350_SLAVE_IMEM_CFG,
- SM8350_SLAVE_IPA_CFG,
- SM8350_SLAVE_IPC_ROUTER_CFG,
- SM8350_SLAVE_LPASS,
- SM8350_SLAVE_CNOC_MSS,
- SM8350_SLAVE_MX_RDPM,
- SM8350_SLAVE_PCIE_0_CFG,
- SM8350_SLAVE_PCIE_1_CFG,
- SM8350_SLAVE_PDM,
- SM8350_SLAVE_PIMEM_CFG,
- SM8350_SLAVE_PKA_WRAPPER_CFG,
- SM8350_SLAVE_PMU_WRAPPER_CFG,
- SM8350_SLAVE_QDSS_CFG,
- SM8350_SLAVE_QSPI_0,
- SM8350_SLAVE_QUP_0,
- SM8350_SLAVE_QUP_1,
- SM8350_SLAVE_QUP_2,
- SM8350_SLAVE_SDCC_2,
- SM8350_SLAVE_SDCC_4,
- SM8350_SLAVE_SECURITY,
- SM8350_SLAVE_SPSS_CFG,
- SM8350_SLAVE_TCSR,
- SM8350_SLAVE_TLMM,
- SM8350_SLAVE_UFS_CARD_CFG,
- SM8350_SLAVE_UFS_MEM_CFG,
- SM8350_SLAVE_USB3_0,
- SM8350_SLAVE_USB3_1,
- SM8350_SLAVE_VENUS_CFG,
- SM8350_SLAVE_VSENSE_CTRL_CFG,
- SM8350_SLAVE_A1NOC_CFG,
- SM8350_SLAVE_A2NOC_CFG,
- SM8350_SLAVE_DDRSS_CFG,
- SM8350_SLAVE_CNOC_MNOC_CFG,
- SM8350_SLAVE_SNOC_CFG,
- SM8350_SLAVE_BOOT_IMEM,
- SM8350_SLAVE_IMEM,
- SM8350_SLAVE_PIMEM,
- SM8350_SLAVE_SERVICE_CNOC,
- SM8350_SLAVE_QDSS_STM,
- SM8350_SLAVE_TCU
- },
+ .link_nodes = { &qhs_ahb2phy0,
+ &qhs_ahb2phy1,
+ &qhs_aoss,
+ &qhs_apss,
+ &qhs_camera_cfg,
+ &qhs_clk_ctl,
+ &qhs_compute_cfg,
+ &qhs_cpr_cx,
+ &qhs_cpr_mmcx,
+ &qhs_cpr_mx,
+ &qhs_crypto0_cfg,
+ &qhs_cx_rdpm,
+ &qhs_dcc_cfg,
+ &qhs_display_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_hwkm,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_ipc_router,
+ &qhs_lpass_cfg,
+ &qhs_mss_cfg,
+ &qhs_mx_rdpm,
+ &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg,
+ &qhs_pdm,
+ &qhs_pimem_cfg,
+ &qhs_pka_wrapper_cfg,
+ &qhs_pmu_wrapper_cfg,
+ &qhs_qdss_cfg,
+ &qhs_qspi,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_qup2,
+ &qhs_sdc2,
+ &qhs_sdc4,
+ &qhs_security,
+ &qhs_spss_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_ufs_card_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3_0,
+ &qhs_usb3_1,
+ &qhs_venus_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &qns_a1_noc_cfg,
+ &qns_a2_noc_cfg,
+ &qns_ddrss_cfg,
+ &qns_mnoc_cfg,
+ &qns_snoc_cfg,
+ &qxs_boot_imem,
+ &qxs_imem,
+ &qxs_pimem,
+ &srvc_cnoc,
+ &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SM8350_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8350_SLAVE_PCIE_0,
- SM8350_SLAVE_PCIE_1
- },
+ .link_nodes = { &xs_pcie_0,
+ &xs_pcie_1, NULL },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SM8350_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
- .num_links = 56,
- .links = { SM8350_SLAVE_AHB2PHY_SOUTH,
- SM8350_SLAVE_AHB2PHY_NORTH,
- SM8350_SLAVE_AOSS,
- SM8350_SLAVE_APPSS,
- SM8350_SLAVE_CAMERA_CFG,
- SM8350_SLAVE_CLK_CTL,
- SM8350_SLAVE_CDSP_CFG,
- SM8350_SLAVE_RBCPR_CX_CFG,
- SM8350_SLAVE_RBCPR_MMCX_CFG,
- SM8350_SLAVE_RBCPR_MX_CFG,
- SM8350_SLAVE_CRYPTO_0_CFG,
- SM8350_SLAVE_CX_RDPM,
- SM8350_SLAVE_DCC_CFG,
- SM8350_SLAVE_DISPLAY_CFG,
- SM8350_SLAVE_GFX3D_CFG,
- SM8350_SLAVE_HWKM,
- SM8350_SLAVE_IMEM_CFG,
- SM8350_SLAVE_IPA_CFG,
- SM8350_SLAVE_IPC_ROUTER_CFG,
- SM8350_SLAVE_LPASS,
- SM8350_SLAVE_CNOC_MSS,
- SM8350_SLAVE_MX_RDPM,
- SM8350_SLAVE_PCIE_0_CFG,
- SM8350_SLAVE_PCIE_1_CFG,
- SM8350_SLAVE_PDM,
- SM8350_SLAVE_PIMEM_CFG,
- SM8350_SLAVE_PKA_WRAPPER_CFG,
- SM8350_SLAVE_PMU_WRAPPER_CFG,
- SM8350_SLAVE_QDSS_CFG,
- SM8350_SLAVE_QSPI_0,
- SM8350_SLAVE_QUP_0,
- SM8350_SLAVE_QUP_1,
- SM8350_SLAVE_QUP_2,
- SM8350_SLAVE_SDCC_2,
- SM8350_SLAVE_SDCC_4,
- SM8350_SLAVE_SECURITY,
- SM8350_SLAVE_SPSS_CFG,
- SM8350_SLAVE_TCSR,
- SM8350_SLAVE_TLMM,
- SM8350_SLAVE_UFS_CARD_CFG,
- SM8350_SLAVE_UFS_MEM_CFG,
- SM8350_SLAVE_USB3_0,
- SM8350_SLAVE_USB3_1,
- SM8350_SLAVE_VENUS_CFG,
- SM8350_SLAVE_VSENSE_CTRL_CFG,
- SM8350_SLAVE_A1NOC_CFG,
- SM8350_SLAVE_A2NOC_CFG,
- SM8350_SLAVE_DDRSS_CFG,
- SM8350_SLAVE_CNOC_MNOC_CFG,
- SM8350_SLAVE_SNOC_CFG,
- SM8350_SLAVE_BOOT_IMEM,
- SM8350_SLAVE_IMEM,
- SM8350_SLAVE_PIMEM,
- SM8350_SLAVE_SERVICE_CNOC,
- SM8350_SLAVE_QDSS_STM,
- SM8350_SLAVE_TCU
- },
+ .link_nodes = { &qhs_ahb2phy0,
+ &qhs_ahb2phy1,
+ &qhs_aoss,
+ &qhs_apss,
+ &qhs_camera_cfg,
+ &qhs_clk_ctl,
+ &qhs_compute_cfg,
+ &qhs_cpr_cx,
+ &qhs_cpr_mmcx,
+ &qhs_cpr_mx,
+ &qhs_crypto0_cfg,
+ &qhs_cx_rdpm,
+ &qhs_dcc_cfg,
+ &qhs_display_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_hwkm,
+ &qhs_imem_cfg,
+ &qhs_ipa,
+ &qhs_ipc_router,
+ &qhs_lpass_cfg,
+ &qhs_mss_cfg,
+ &qhs_mx_rdpm,
+ &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg,
+ &qhs_pdm,
+ &qhs_pimem_cfg,
+ &qhs_pka_wrapper_cfg,
+ &qhs_pmu_wrapper_cfg,
+ &qhs_qdss_cfg,
+ &qhs_qspi,
+ &qhs_qup0,
+ &qhs_qup1,
+ &qhs_qup2,
+ &qhs_sdc2,
+ &qhs_sdc4,
+ &qhs_security,
+ &qhs_spss_cfg,
+ &qhs_tcsr,
+ &qhs_tlmm,
+ &qhs_ufs_card_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_usb3_0,
+ &qhs_usb3_1,
+ &qhs_venus_cfg,
+ &qhs_vsense_ctrl_cfg,
+ &qns_a1_noc_cfg,
+ &qns_a2_noc_cfg,
+ &qns_ddrss_cfg,
+ &qns_mnoc_cfg,
+ &qns_snoc_cfg,
+ &qxs_boot_imem,
+ &qxs_imem,
+ &qxs_pimem,
+ &srvc_cnoc,
+ &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_cnoc_dc_noc = {
.name = "qnm_cnoc_dc_noc",
- .id = SM8350_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 2,
- .links = { SM8350_SLAVE_LLCC_CFG,
- SM8350_SLAVE_GEM_NOC_CFG
- },
+ .link_nodes = { &qhs_llcc,
+ &qns_gemnoc, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SM8350_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8350_SLAVE_GEM_NOC_CNOC,
- SM8350_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SM8350_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8350_SLAVE_GEM_NOC_CNOC,
- SM8350_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SM8350_MASTER_APPSS_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8350_SLAVE_GEM_NOC_CNOC,
- SM8350_SLAVE_LLCC,
- SM8350_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SM8350_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8350_SLAVE_GEM_NOC_CNOC,
- SM8350_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
- .id = SM8350_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 5,
- .links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG,
- SM8350_SLAVE_MCDMA_MS_MPU_CFG,
- SM8350_SLAVE_SERVICE_GEM_NOC_1,
- SM8350_SLAVE_SERVICE_GEM_NOC_2,
- SM8350_SLAVE_SERVICE_GEM_NOC
- },
+ .link_nodes = { &qhs_mdsp_ms_mpu_cfg,
+ &qhs_modem_ms_mpu_cfg,
+ &srvc_even_gemnoc,
+ &srvc_odd_gemnoc,
+ &srvc_sys_gemnoc, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SM8350_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8350_SLAVE_GEM_NOC_CNOC,
- SM8350_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM8350_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM8350_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8350_SLAVE_GEM_NOC_CNOC,
- SM8350_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM8350_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM8350_SLAVE_GEM_NOC_CNOC,
- SM8350_SLAVE_LLCC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM8350_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM8350_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8350_SLAVE_GEM_NOC_CNOC,
- SM8350_SLAVE_LLCC,
- SM8350_SLAVE_MEM_NOC_PCIE_SNOC
- },
+ .link_nodes = { &qns_gem_noc_cnoc,
+ &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
- .id = SM8350_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 6,
- .links = { SM8350_SLAVE_LPASS_CORE_CFG,
- SM8350_SLAVE_LPASS_LPI_CFG,
- SM8350_SLAVE_LPASS_MPU_CFG,
- SM8350_SLAVE_LPASS_TOP_CFG,
- SM8350_SLAVE_SERVICES_LPASS_AML_NOC,
- SM8350_SLAVE_SERVICE_LPASS_AG_NOC
- },
+ .link_nodes = { &qhs_lpass_core,
+ &qhs_lpass_lpi,
+ &qhs_lpass_mpu,
+ &qhs_lpass_top,
+ &srvc_niu_aml_noc,
+ &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM8350_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SM8350_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = SM8350_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SM8350_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_mnoc_cfg = {
.name = "qnm_mnoc_cfg",
- .id = SM8350_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
- .id = SM8350_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video1 = {
.name = "qnm_video1",
- .id = SM8350_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SM8350_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SM8350_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_mdp1 = {
.name = "qxm_mdp1",
- .id = SM8350_MASTER_MDP1,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = SM8350_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
- .id = SM8350_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_SERVICE_NSP_NOC },
+ .link_nodes = { &service_nsp_noc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SM8350_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM8350_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM8350_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
- .id = SM8350_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SM8350_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM8350_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM8350_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8350_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SM8350_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM8350_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8350_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SM8350_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SM8350_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SM8350_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM8350_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SM8350_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM8350_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM8350_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_cfg = {
.name = "qhs_compute_cfg",
- .id = SM8350_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM8350_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SM8350_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SM8350_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM8350_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SM8350_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SM8350_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM8350_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM8350_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_hwkm = {
.name = "qhs_hwkm",
- .id = SM8350_SLAVE_HWKM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM8350_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM8350_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SM8350_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = SM8350_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8350_MASTER_CNOC_LPASS_AG_NOC },
+ .link_nodes = { &qhm_config_noc, NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SM8350_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SM8350_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SM8350_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SM8350_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM8350_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM8350_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pka_wrapper_cfg = {
.name = "qhs_pka_wrapper_cfg",
- .id = SM8350_SLAVE_PKA_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
.name = "qhs_pmu_wrapper_cfg",
- .id = SM8350_SLAVE_PMU_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM8350_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SM8350_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SM8350_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SM8350_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SM8350_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM8350_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM8350_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
- .id = SM8350_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SM8350_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM8350_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SM8350_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_card_cfg = {
.name = "qhs_ufs_card_cfg",
- .id = SM8350_SLAVE_UFS_CARD_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM8350_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM8350_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_1 = {
.name = "qhs_usb3_1",
- .id = SM8350_SLAVE_USB3_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM8350_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM8350_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a1_noc_cfg = {
.name = "qns_a1_noc_cfg",
- .id = SM8350_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2_noc_cfg = {
.name = "qns_a2_noc_cfg",
- .id = SM8350_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = SM8350_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mnoc_cfg = {
.name = "qns_mnoc_cfg",
- .id = SM8350_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
- .id = SM8350_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = SM8350_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM8350_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SM8350_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SM8350_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SM8350_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SM8350_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM8350_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM8350_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SM8350_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
- .id = SM8350_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
.name = "qhs_modem_ms_mpu_cfg",
- .id = SM8350_SLAVE_MCDMA_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SM8350_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8350_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM8350_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8350_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
- .id = SM8350_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
- .id = SM8350_SLAVE_SERVICE_GEM_NOC_2,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
- .id = SM8350_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
- .id = SM8350_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
- .id = SM8350_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
- .id = SM8350_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
- .id = SM8350_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
- .id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
- .id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM8350_SLAVE_EBI1,
.channels = 4,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM8350_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SM8350_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM8350_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SM8350_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8350_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc, NULL },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
- .id = SM8350_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM8350_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8350_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM8350_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8350_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SM8350_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
+ .link_nodes = { NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1484,6 +1484,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1515,6 +1516,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1594,6 +1596,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1610,6 +1613,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_dc_noc = {
+ .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1646,6 +1650,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1666,6 +1671,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1683,6 +1689,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8350_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1713,6 +1720,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1732,6 +1740,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_compute_noc = {
+ .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1757,6 +1766,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8350.h b/drivers/interconnect/qcom/sm8350.h
deleted file mode 100644
index 074c6131ab3674376aa4ebfb79d62a2f655df338..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm8350.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm SM8350 interconnect IDs
- *
- * Copyright (c) 2021, Linaro Limited
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM8350_H
-
-#define SM8350_MASTER_GPU_TCU 0
-#define SM8350_MASTER_SYS_TCU 1
-#define SM8350_MASTER_APPSS_PROC 2
-#define SM8350_MASTER_LLCC 3
-#define SM8350_MASTER_CNOC_LPASS_AG_NOC 4
-#define SM8350_MASTER_CDSP_NOC_CFG 5
-#define SM8350_MASTER_QDSS_BAM 6
-#define SM8350_MASTER_QSPI_0 7
-#define SM8350_MASTER_QUP_0 8
-#define SM8350_MASTER_QUP_1 9
-#define SM8350_MASTER_QUP_2 10
-#define SM8350_MASTER_A1NOC_CFG 11
-#define SM8350_MASTER_A2NOC_CFG 12
-#define SM8350_MASTER_A1NOC_SNOC 13
-#define SM8350_MASTER_A2NOC_SNOC 14
-#define SM8350_MASTER_CAMNOC_HF 15
-#define SM8350_MASTER_CAMNOC_ICP 16
-#define SM8350_MASTER_CAMNOC_SF 17
-#define SM8350_MASTER_COMPUTE_NOC 18
-#define SM8350_MASTER_CNOC_DC_NOC 19
-#define SM8350_MASTER_GEM_NOC_CFG 20
-#define SM8350_MASTER_GEM_NOC_CNOC 21
-#define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22
-#define SM8350_MASTER_GFX3D 23
-#define SM8350_MASTER_CNOC_MNOC_CFG 24
-#define SM8350_MASTER_MNOC_HF_MEM_NOC 25
-#define SM8350_MASTER_MNOC_SF_MEM_NOC 26
-#define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27
-#define SM8350_MASTER_SNOC_CFG 28
-#define SM8350_MASTER_SNOC_GC_MEM_NOC 29
-#define SM8350_MASTER_SNOC_SF_MEM_NOC 30
-#define SM8350_MASTER_VIDEO_P0 31
-#define SM8350_MASTER_VIDEO_P1 32
-#define SM8350_MASTER_VIDEO_PROC 33
-#define SM8350_MASTER_QUP_CORE_0 34
-#define SM8350_MASTER_QUP_CORE_1 35
-#define SM8350_MASTER_QUP_CORE_2 36
-#define SM8350_MASTER_CRYPTO 37
-#define SM8350_MASTER_IPA 38
-#define SM8350_MASTER_MDP0 39
-#define SM8350_MASTER_MDP1 40
-#define SM8350_MASTER_CDSP_PROC 41
-#define SM8350_MASTER_PIMEM 42
-#define SM8350_MASTER_ROTATOR 43
-#define SM8350_MASTER_GIC 44
-#define SM8350_MASTER_PCIE_0 45
-#define SM8350_MASTER_PCIE_1 46
-#define SM8350_MASTER_QDSS_DAP 47
-#define SM8350_MASTER_QDSS_ETR 48
-#define SM8350_MASTER_SDCC_2 49
-#define SM8350_MASTER_SDCC_4 50
-#define SM8350_MASTER_UFS_CARD 51
-#define SM8350_MASTER_UFS_MEM 52
-#define SM8350_MASTER_USB3_0 53
-#define SM8350_MASTER_USB3_1 54
-#define SM8350_SLAVE_EBI1 55
-#define SM8350_SLAVE_AHB2PHY_SOUTH 56
-#define SM8350_SLAVE_AHB2PHY_NORTH 57
-#define SM8350_SLAVE_AOSS 58
-#define SM8350_SLAVE_APPSS 59
-#define SM8350_SLAVE_CAMERA_CFG 60
-#define SM8350_SLAVE_CLK_CTL 61
-#define SM8350_SLAVE_CDSP_CFG 62
-#define SM8350_SLAVE_RBCPR_CX_CFG 63
-#define SM8350_SLAVE_RBCPR_MMCX_CFG 64
-#define SM8350_SLAVE_RBCPR_MX_CFG 65
-#define SM8350_SLAVE_CRYPTO_0_CFG 66
-#define SM8350_SLAVE_CX_RDPM 67
-#define SM8350_SLAVE_DCC_CFG 68
-#define SM8350_SLAVE_DISPLAY_CFG 69
-#define SM8350_SLAVE_GFX3D_CFG 70
-#define SM8350_SLAVE_HWKM 71
-#define SM8350_SLAVE_IMEM_CFG 72
-#define SM8350_SLAVE_IPA_CFG 73
-#define SM8350_SLAVE_IPC_ROUTER_CFG 74
-#define SM8350_SLAVE_LLCC_CFG 75
-#define SM8350_SLAVE_LPASS 76
-#define SM8350_SLAVE_LPASS_CORE_CFG 77
-#define SM8350_SLAVE_LPASS_LPI_CFG 78
-#define SM8350_SLAVE_LPASS_MPU_CFG 79
-#define SM8350_SLAVE_LPASS_TOP_CFG 80
-#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81
-#define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82
-#define SM8350_SLAVE_CNOC_MSS 83
-#define SM8350_SLAVE_MX_RDPM 84
-#define SM8350_SLAVE_PCIE_0_CFG 85
-#define SM8350_SLAVE_PCIE_1_CFG 86
-#define SM8350_SLAVE_PDM 87
-#define SM8350_SLAVE_PIMEM_CFG 88
-#define SM8350_SLAVE_PKA_WRAPPER_CFG 89
-#define SM8350_SLAVE_PMU_WRAPPER_CFG 90
-#define SM8350_SLAVE_QDSS_CFG 91
-#define SM8350_SLAVE_QSPI_0 92
-#define SM8350_SLAVE_QUP_0 93
-#define SM8350_SLAVE_QUP_1 94
-#define SM8350_SLAVE_QUP_2 95
-#define SM8350_SLAVE_SDCC_2 96
-#define SM8350_SLAVE_SDCC_4 97
-#define SM8350_SLAVE_SECURITY 98
-#define SM8350_SLAVE_SPSS_CFG 99
-#define SM8350_SLAVE_TCSR 100
-#define SM8350_SLAVE_TLMM 101
-#define SM8350_SLAVE_UFS_CARD_CFG 102
-#define SM8350_SLAVE_UFS_MEM_CFG 103
-#define SM8350_SLAVE_USB3_0 104
-#define SM8350_SLAVE_USB3_1 105
-#define SM8350_SLAVE_VENUS_CFG 106
-#define SM8350_SLAVE_VSENSE_CTRL_CFG 107
-#define SM8350_SLAVE_A1NOC_CFG 108
-#define SM8350_SLAVE_A1NOC_SNOC 109
-#define SM8350_SLAVE_A2NOC_CFG 110
-#define SM8350_SLAVE_A2NOC_SNOC 111
-#define SM8350_SLAVE_DDRSS_CFG 112
-#define SM8350_SLAVE_GEM_NOC_CNOC 113
-#define SM8350_SLAVE_GEM_NOC_CFG 114
-#define SM8350_SLAVE_SNOC_GEM_NOC_GC 115
-#define SM8350_SLAVE_SNOC_GEM_NOC_SF 116
-#define SM8350_SLAVE_LLCC 117
-#define SM8350_SLAVE_MNOC_HF_MEM_NOC 118
-#define SM8350_SLAVE_MNOC_SF_MEM_NOC 119
-#define SM8350_SLAVE_CNOC_MNOC_CFG 120
-#define SM8350_SLAVE_CDSP_MEM_NOC 121
-#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122
-#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123
-#define SM8350_SLAVE_SNOC_CFG 124
-#define SM8350_SLAVE_QUP_CORE_0 125
-#define SM8350_SLAVE_QUP_CORE_1 126
-#define SM8350_SLAVE_QUP_CORE_2 127
-#define SM8350_SLAVE_BOOT_IMEM 128
-#define SM8350_SLAVE_IMEM 129
-#define SM8350_SLAVE_PIMEM 130
-#define SM8350_SLAVE_SERVICE_NSP_NOC 131
-#define SM8350_SLAVE_SERVICE_A1NOC 132
-#define SM8350_SLAVE_SERVICE_A2NOC 133
-#define SM8350_SLAVE_SERVICE_CNOC 134
-#define SM8350_SLAVE_SERVICE_GEM_NOC_1 135
-#define SM8350_SLAVE_SERVICE_MNOC 136
-#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137
-#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138
-#define SM8350_SLAVE_SERVICE_GEM_NOC_2 139
-#define SM8350_SLAVE_SERVICE_SNOC 140
-#define SM8350_SLAVE_SERVICE_GEM_NOC 141
-#define SM8350_SLAVE_PCIE_0 142
-#define SM8350_SLAVE_PCIE_1 143
-#define SM8350_SLAVE_QDSS_STM 144
-#define SM8350_SLAVE_TCU 145
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 24/28] interconnect: qcom: sm8450: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (22 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 23/28] interconnect: qcom: sm8350: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 25/28] interconnect: qcom: sm8550: " Dmitry Baryshkov
` (4 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm8450.c | 762 +++++++++++++++++--------------------
drivers/interconnect/qcom/sm8450.h | 169 --------
2 files changed, 343 insertions(+), 588 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c
index 94e60b5067625606e2b141fbde1b5d90425386d3..eb3c2bb5499da9aaa6cd84b14d3917ab5e119a5f 100644
--- a/drivers/interconnect/qcom/sm8450.c
+++ b/drivers/interconnect/qcom/sm8450.c
@@ -16,1325 +16,1238 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
-#include "sm8450.h"
+
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qnm_a1noc_cfg;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qnm_a2noc_cfg;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node qxm_sensorss_q6;
+static struct qcom_icc_node qxm_sp;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mdsp;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_nsp_gemnoc;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qhm_config_noc;
+static struct qcom_icc_node qxm_lpass_dsp;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_mdp;
+static struct qcom_icc_node qnm_mnoc_cfg;
+static struct qcom_icc_node qnm_rot;
+static struct qcom_icc_node qnm_vapss_hcp;
+static struct qcom_icc_node qnm_video;
+static struct qcom_icc_node qnm_video_cv_cpu;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qhm_nsp_noc_config;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qnm_pcie_anoc_cfg;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node qhm_gic;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_lpass_noc;
+static struct qcom_icc_node qnm_snoc_cfg;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qnm_mnoc_hf_disp;
+static struct qcom_icc_node qnm_mnoc_sf_disp;
+static struct qcom_icc_node qnm_pcie_disp;
+static struct qcom_icc_node llcc_mc_disp;
+static struct qcom_icc_node qnm_mdp_disp;
+static struct qcom_icc_node qnm_rot_disp;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mxa;
+static struct qcom_icc_node qhs_cpr_mxc;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_tme_cfg;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_a1_noc_cfg;
+static struct qcom_icc_node qns_a2_noc_cfg;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qns_mnoc_cfg;
+static struct qcom_icc_node qns_pcie_anoc_cfg;
+static struct qcom_icc_node qns_snoc_cfg;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node qhs_lpass_core;
+static struct qcom_icc_node qhs_lpass_lpi;
+static struct qcom_icc_node qhs_lpass_mpu;
+static struct qcom_icc_node qhs_lpass_top;
+static struct qcom_icc_node qns_sysnoc;
+static struct qcom_icc_node srvc_niu_aml_noc;
+static struct qcom_icc_node srvc_niu_lpass_agnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node service_nsp_noc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_pcie_aggre_noc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node qns_llcc_disp;
+static struct qcom_icc_node ebi_disp;
+static struct qcom_icc_node qns_mem_noc_hf_disp;
+static struct qcom_icc_node qns_mem_noc_sf_disp;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SM8450_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SM8450_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qnm_a1noc_cfg = {
.name = "qnm_a1noc_cfg",
- .id = SM8450_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM8450_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM8450_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM8450_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM8450_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SM8450_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SM8450_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qnm_a2noc_cfg = {
.name = "qnm_a2noc_cfg",
- .id = SM8450_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM8450_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM8450_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sensorss_q6 = {
.name = "qxm_sensorss_q6",
- .id = SM8450_MASTER_SENSORS_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sp = {
.name = "qxm_sp",
- .id = SM8450_MASTER_SP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = SM8450_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = SM8450_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM8450_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SM8450_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SM8450_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = SM8450_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_QUP_CORE_2 },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SM8450_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 51,
- .links = { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH,
- SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG,
- SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG,
- SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG,
- SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG,
- SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM,
- SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG,
- SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG,
- SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS,
- SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM,
- SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG,
- SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG,
- SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG,
- SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0,
- SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2,
- SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4,
- SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR,
- SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG,
- SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0,
- SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG,
- SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG,
- SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG,
- SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG,
- SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM,
- SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM,
- SM8450_SLAVE_TCU },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_aoss, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_compute_cfg,
+ &qhs_cpr_cx, &qhs_cpr_mmcx,
+ &qhs_cpr_mxa, &qhs_cpr_mxc,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_imem_cfg, &qhs_ipa,
+ &qhs_ipc_router, &qhs_lpass_cfg,
+ &qhs_mss_cfg, &qhs_mx_rdpm,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pdm, &qhs_pimem_cfg,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_qup2,
+ &qhs_sdc2, &qhs_sdc4,
+ &qhs_spss_cfg, &qhs_tcsr,
+ &qhs_tlmm, &qhs_tme_cfg,
+ &qhs_ufs_mem_cfg, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qns_a1_noc_cfg, &qns_a2_noc_cfg,
+ &qns_ddrss_cfg, &qns_mnoc_cfg,
+ &qns_pcie_anoc_cfg, &qns_snoc_cfg,
+ &qxs_imem, &qxs_pimem,
+ &srvc_cnoc, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SM8450_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SM8450_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SM8450_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SM8450_MASTER_APPSS_PROC,
.channels = 3,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
- SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SM8450_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
- .id = SM8450_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
- SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM8450_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM8450_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_nsp_gemnoc = {
.name = "qnm_nsp_gemnoc",
- .id = SM8450_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM8450_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM8450_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
- SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
- .id = SM8450_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 6,
- .links = { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG,
- SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG,
- SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC },
+ .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
+ &qhs_lpass_mpu, &qhs_lpass_top,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node qxm_lpass_dsp = {
.name = "qxm_lpass_dsp",
- .id = SM8450_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 4,
- .links = { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC,
- SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC },
+ .link_nodes = { &qhs_lpass_top, &qns_sysnoc,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM8450_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SM8450_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = SM8450_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SM8450_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_mdp = {
.name = "qnm_mdp",
- .id = SM8450_MASTER_MDP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_mnoc_cfg = {
.name = "qnm_mnoc_cfg",
- .id = SM8450_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qnm_rot = {
.name = "qnm_rot",
- .id = SM8450_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_vapss_hcp = {
.name = "qnm_vapss_hcp",
- .id = SM8450_MASTER_CDSP_HCP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video = {
.name = "qnm_video",
- .id = SM8450_MASTER_VIDEO,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cv_cpu = {
.name = "qnm_video_cv_cpu",
- .id = SM8450_MASTER_VIDEO_CV_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SM8450_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = SM8450_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
- .id = SM8450_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_SERVICE_NSP_NOC },
+ .link_nodes = { &service_nsp_noc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SM8450_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qnm_pcie_anoc_cfg = {
.name = "qnm_pcie_anoc_cfg",
- .id = SM8450_MASTER_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_SERVICE_PCIE_ANOC },
+ .link_nodes = { &srvc_pcie_aggre_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM8450_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SM8450_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
- .id = SM8450_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM8450_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM8450_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_lpass_noc = {
.name = "qnm_lpass_noc",
- .id = SM8450_MASTER_LPASS_ANOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
- .id = SM8450_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc, NULL },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SM8450_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM8450_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf_disp = {
.name = "qnm_mnoc_hf_disp",
- .id = SM8450_MASTER_MNOC_HF_MEM_NOC_DISP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_LLCC_DISP },
+ .link_nodes = { &qns_llcc_disp, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf_disp = {
.name = "qnm_mnoc_sf_disp",
- .id = SM8450_MASTER_MNOC_SF_MEM_NOC_DISP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_LLCC_DISP },
+ .link_nodes = { &qns_llcc_disp, NULL },
};
static struct qcom_icc_node qnm_pcie_disp = {
.name = "qnm_pcie_disp",
- .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_SLAVE_LLCC_DISP },
+ .link_nodes = { &qns_llcc_disp, NULL },
};
static struct qcom_icc_node llcc_mc_disp = {
.name = "llcc_mc_disp",
- .id = SM8450_MASTER_LLCC_DISP,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_SLAVE_EBI1_DISP },
+ .link_nodes = { &ebi_disp, NULL },
};
static struct qcom_icc_node qnm_mdp_disp = {
.name = "qnm_mdp_disp",
- .id = SM8450_MASTER_MDP_DISP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP },
+ .link_nodes = { &qns_mem_noc_hf_disp, NULL },
};
static struct qcom_icc_node qnm_rot_disp = {
.name = "qnm_rot_disp",
- .id = SM8450_MASTER_ROTATOR_DISP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP },
+ .link_nodes = { &qns_mem_noc_sf_disp, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM8450_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SM8450_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM8450_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SM8450_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SM8450_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SM8450_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = SM8450_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SM8450_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SM8450_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM8450_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM8450_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM8450_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_compute_cfg = {
.name = "qhs_compute_cfg",
- .id = SM8450_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { MASTER_CDSP_NOC_CFG },
+ .link_nodes = { MASTER_CDSP_NOC_CFG, NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM8450_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SM8450_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxa = {
.name = "qhs_cpr_mxa",
- .id = SM8450_SLAVE_RBCPR_MXA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxc = {
.name = "qhs_cpr_mxc",
- .id = SM8450_SLAVE_RBCPR_MXC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM8450_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SM8450_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM8450_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM8450_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM8450_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM8450_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SM8450_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = SM8450_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { MASTER_CNOC_LPASS_AG_NOC },
+ .link_nodes = { MASTER_CNOC_LPASS_AG_NOC, NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SM8450_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SM8450_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SM8450_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SM8450_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM8450_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM8450_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM8450_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM8450_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SM8450_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SM8450_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SM8450_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SM8450_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM8450_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM8450_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SM8450_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM8450_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SM8450_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
- .id = SM8450_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM8450_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM8450_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM8450_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM8450_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_a1_noc_cfg = {
.name = "qns_a1_noc_cfg",
- .id = SM8450_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_MASTER_A1NOC_CFG },
+ .link_nodes = { &qnm_a1noc_cfg, NULL },
};
static struct qcom_icc_node qns_a2_noc_cfg = {
.name = "qns_a2_noc_cfg",
- .id = SM8450_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_MASTER_A2NOC_CFG },
+ .link_nodes = { &qnm_a2noc_cfg, NULL },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = SM8450_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
//FIXME where is link
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mnoc_cfg = {
.name = "qns_mnoc_cfg",
- .id = SM8450_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qnm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qns_pcie_anoc_cfg = {
.name = "qns_pcie_anoc_cfg",
- .id = SM8450_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_MASTER_PCIE_ANOC_CFG },
+ .link_nodes = { &qnm_pcie_anoc_cfg, NULL },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
- .id = SM8450_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8450_MASTER_SNOC_CFG },
+ .link_nodes = { &qnm_snoc_cfg, NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM8450_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SM8450_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SM8450_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SM8450_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SM8450_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM8450_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM8450_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SM8450_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM8450_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SM8450_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
- .id = SM8450_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
- .id = SM8450_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
- .id = SM8450_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
- .id = SM8450_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_sysnoc = {
.name = "qns_sysnoc",
- .id = SM8450_SLAVE_LPASS_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_MASTER_LPASS_ANOC },
+ .link_nodes = { &qnm_lpass_noc, NULL },
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
- .id = SM8450_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
- .id = SM8450_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM8450_SLAVE_EBI1,
.channels = 4,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM8450_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SM8450_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM8450_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SM8450_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_nsp_gemnoc, NULL },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
- .id = SM8450_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SM8450_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_pcie_aggre_noc = {
.name = "srvc_pcie_aggre_noc",
- .id = SM8450_SLAVE_SERVICE_PCIE_ANOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM8450_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8450_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM8450_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SM8450_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_llcc_disp = {
.name = "qns_llcc_disp",
- .id = SM8450_SLAVE_LLCC_DISP,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8450_MASTER_LLCC_DISP },
+ .link_nodes = { &llcc_mc_disp, NULL },
};
static struct qcom_icc_node ebi_disp = {
.name = "ebi_disp",
- .id = SM8450_SLAVE_EBI1_DISP,
.channels = 4,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf_disp = {
.name = "qns_mem_noc_hf_disp",
- .id = SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP },
+ .link_nodes = { &qnm_mnoc_hf_disp, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf_disp = {
.name = "qns_mem_noc_sf_disp",
- .id = SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP },
+ .link_nodes = { &qnm_mnoc_sf_disp, NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1529,6 +1442,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1556,6 +1470,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1578,6 +1493,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8450_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1647,6 +1563,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1682,6 +1599,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1704,6 +1622,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1725,6 +1644,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8450_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1760,6 +1680,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1778,6 +1699,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_nsp_noc = {
+ .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1797,6 +1719,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_pcie_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1825,6 +1748,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8450.h b/drivers/interconnect/qcom/sm8450.h
deleted file mode 100644
index a5790ec6767b36e15997d838339d024007f9f7be..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm8450.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * SM8450 interconnect IDs
- *
- * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021, Linaro Limited
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H
-
-#define SM8450_MASTER_GPU_TCU 0
-#define SM8450_MASTER_SYS_TCU 1
-#define SM8450_MASTER_APPSS_PROC 2
-#define SM8450_MASTER_LLCC 3
-#define SM8450_MASTER_CNOC_LPASS_AG_NOC 4
-#define SM8450_MASTER_GIC_AHB 5
-#define SM8450_MASTER_CDSP_NOC_CFG 6
-#define SM8450_MASTER_QDSS_BAM 7
-#define SM8450_MASTER_QSPI_0 8
-#define SM8450_MASTER_QUP_0 9
-#define SM8450_MASTER_QUP_1 10
-#define SM8450_MASTER_QUP_2 11
-#define SM8450_MASTER_A1NOC_CFG 12
-#define SM8450_MASTER_A2NOC_CFG 13
-#define SM8450_MASTER_A1NOC_SNOC 14
-#define SM8450_MASTER_A2NOC_SNOC 15
-#define SM8450_MASTER_CAMNOC_HF 16
-#define SM8450_MASTER_CAMNOC_ICP 17
-#define SM8450_MASTER_CAMNOC_SF 18
-#define SM8450_MASTER_GEM_NOC_CNOC 19
-#define SM8450_MASTER_GEM_NOC_PCIE_SNOC 20
-#define SM8450_MASTER_GFX3D 21
-#define SM8450_MASTER_LPASS_ANOC 22
-#define SM8450_MASTER_MDP 23
-#define SM8450_MASTER_MDP0 SM8450_MASTER_MDP
-#define SM8450_MASTER_MDP1 SM8450_MASTER_MDP
-#define SM8450_MASTER_MSS_PROC 24
-#define SM8450_MASTER_CNOC_MNOC_CFG 25
-#define SM8450_MASTER_MNOC_HF_MEM_NOC 26
-#define SM8450_MASTER_MNOC_SF_MEM_NOC 27
-#define SM8450_MASTER_COMPUTE_NOC 28
-#define SM8450_MASTER_ANOC_PCIE_GEM_NOC 29
-#define SM8450_MASTER_PCIE_ANOC_CFG 30
-#define SM8450_MASTER_ROTATOR 31
-#define SM8450_MASTER_SNOC_CFG 32
-#define SM8450_MASTER_SNOC_GC_MEM_NOC 33
-#define SM8450_MASTER_SNOC_SF_MEM_NOC 34
-#define SM8450_MASTER_CDSP_HCP 35
-#define SM8450_MASTER_VIDEO 36
-#define SM8450_MASTER_VIDEO_P0 SM8450_MASTER_VIDEO
-#define SM8450_MASTER_VIDEO_P1 SM8450_MASTER_VIDEO
-#define SM8450_MASTER_VIDEO_CV_PROC 37
-#define SM8450_MASTER_VIDEO_PROC 38
-#define SM8450_MASTER_VIDEO_V_PROC 39
-#define SM8450_MASTER_QUP_CORE_0 40
-#define SM8450_MASTER_QUP_CORE_1 41
-#define SM8450_MASTER_QUP_CORE_2 42
-#define SM8450_MASTER_CRYPTO 43
-#define SM8450_MASTER_IPA 44
-#define SM8450_MASTER_LPASS_PROC 45
-#define SM8450_MASTER_CDSP_PROC 46
-#define SM8450_MASTER_PIMEM 47
-#define SM8450_MASTER_SENSORS_PROC 48
-#define SM8450_MASTER_SP 49
-#define SM8450_MASTER_GIC 50
-#define SM8450_MASTER_PCIE_0 51
-#define SM8450_MASTER_PCIE_1 52
-#define SM8450_MASTER_QDSS_ETR 53
-#define SM8450_MASTER_QDSS_ETR_1 54
-#define SM8450_MASTER_SDCC_2 55
-#define SM8450_MASTER_SDCC_4 56
-#define SM8450_MASTER_UFS_MEM 57
-#define SM8450_MASTER_USB3_0 58
-#define SM8450_SLAVE_EBI1 512
-#define SM8450_SLAVE_AHB2PHY_SOUTH 513
-#define SM8450_SLAVE_AHB2PHY_NORTH 514
-#define SM8450_SLAVE_AOSS 515
-#define SM8450_SLAVE_CAMERA_CFG 516
-#define SM8450_SLAVE_CLK_CTL 517
-#define SM8450_SLAVE_CDSP_CFG 518
-#define SM8450_SLAVE_RBCPR_CX_CFG 519
-#define SM8450_SLAVE_RBCPR_MMCX_CFG 520
-#define SM8450_SLAVE_RBCPR_MXA_CFG 521
-#define SM8450_SLAVE_RBCPR_MXC_CFG 522
-#define SM8450_SLAVE_CRYPTO_0_CFG 523
-#define SM8450_SLAVE_CX_RDPM 524
-#define SM8450_SLAVE_DISPLAY_CFG 525
-#define SM8450_SLAVE_GFX3D_CFG 526
-#define SM8450_SLAVE_IMEM_CFG 527
-#define SM8450_SLAVE_IPA_CFG 528
-#define SM8450_SLAVE_IPC_ROUTER_CFG 529
-#define SM8450_SLAVE_LPASS 530
-#define SM8450_SLAVE_LPASS_CORE_CFG 531
-#define SM8450_SLAVE_LPASS_LPI_CFG 532
-#define SM8450_SLAVE_LPASS_MPU_CFG 533
-#define SM8450_SLAVE_LPASS_TOP_CFG 534
-#define SM8450_SLAVE_CNOC_MSS 535
-#define SM8450_SLAVE_MX_RDPM 536
-#define SM8450_SLAVE_PCIE_0_CFG 537
-#define SM8450_SLAVE_PCIE_1_CFG 538
-#define SM8450_SLAVE_PDM 539
-#define SM8450_SLAVE_PIMEM_CFG 540
-#define SM8450_SLAVE_PRNG 541
-#define SM8450_SLAVE_QDSS_CFG 542
-#define SM8450_SLAVE_QSPI_0 543
-#define SM8450_SLAVE_QUP_0 544
-#define SM8450_SLAVE_QUP_1 545
-#define SM8450_SLAVE_QUP_2 546
-#define SM8450_SLAVE_SDCC_2 547
-#define SM8450_SLAVE_SDCC_4 548
-#define SM8450_SLAVE_SPSS_CFG 549
-#define SM8450_SLAVE_TCSR 550
-#define SM8450_SLAVE_TLMM 551
-#define SM8450_SLAVE_TME_CFG 552
-#define SM8450_SLAVE_UFS_MEM_CFG 553
-#define SM8450_SLAVE_USB3_0 554
-#define SM8450_SLAVE_VENUS_CFG 555
-#define SM8450_SLAVE_VSENSE_CTRL_CFG 556
-#define SM8450_SLAVE_A1NOC_CFG 557
-#define SM8450_SLAVE_A1NOC_SNOC 558
-#define SM8450_SLAVE_A2NOC_CFG 559
-#define SM8450_SLAVE_A2NOC_SNOC 560
-#define SM8450_SLAVE_DDRSS_CFG 561
-#define SM8450_SLAVE_GEM_NOC_CNOC 562
-#define SM8450_SLAVE_SNOC_GEM_NOC_GC 563
-#define SM8450_SLAVE_SNOC_GEM_NOC_SF 564
-#define SM8450_SLAVE_LLCC 565
-#define SM8450_SLAVE_MNOC_HF_MEM_NOC 566
-#define SM8450_SLAVE_MNOC_SF_MEM_NOC 567
-#define SM8450_SLAVE_CNOC_MNOC_CFG 568
-#define SM8450_SLAVE_CDSP_MEM_NOC 569
-#define SM8450_SLAVE_MEM_NOC_PCIE_SNOC 570
-#define SM8450_SLAVE_PCIE_ANOC_CFG 571
-#define SM8450_SLAVE_ANOC_PCIE_GEM_NOC 572
-#define SM8450_SLAVE_SNOC_CFG 573
-#define SM8450_SLAVE_LPASS_SNOC 574
-#define SM8450_SLAVE_QUP_CORE_0 575
-#define SM8450_SLAVE_QUP_CORE_1 576
-#define SM8450_SLAVE_QUP_CORE_2 577
-#define SM8450_SLAVE_IMEM 578
-#define SM8450_SLAVE_PIMEM 579
-#define SM8450_SLAVE_SERVICE_NSP_NOC 580
-#define SM8450_SLAVE_SERVICE_A1NOC 581
-#define SM8450_SLAVE_SERVICE_A2NOC 582
-#define SM8450_SLAVE_SERVICE_CNOC 583
-#define SM8450_SLAVE_SERVICE_MNOC 584
-#define SM8450_SLAVE_SERVICES_LPASS_AML_NOC 585
-#define SM8450_SLAVE_SERVICE_LPASS_AG_NOC 586
-#define SM8450_SLAVE_SERVICE_PCIE_ANOC 587
-#define SM8450_SLAVE_SERVICE_SNOC 588
-#define SM8450_SLAVE_PCIE_0 589
-#define SM8450_SLAVE_PCIE_1 590
-#define SM8450_SLAVE_QDSS_STM 591
-#define SM8450_SLAVE_TCU 592
-#define SM8450_MASTER_LLCC_DISP 1000
-#define SM8450_MASTER_MDP_DISP 1001
-#define SM8450_MASTER_MDP0_DISP SM8450_MASTER_MDP_DISP
-#define SM8450_MASTER_MDP1_DISP SM8450_MASTER_MDP_DISP
-#define SM8450_MASTER_MNOC_HF_MEM_NOC_DISP 1002
-#define SM8450_MASTER_MNOC_SF_MEM_NOC_DISP 1003
-#define SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP 1004
-#define SM8450_MASTER_ROTATOR_DISP 1005
-#define SM8450_SLAVE_EBI1_DISP 1512
-#define SM8450_SLAVE_LLCC_DISP 1513
-#define SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP 1514
-#define SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP 1515
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 25/28] interconnect: qcom: sm8550: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (23 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 24/28] interconnect: qcom: sm8450: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 26/28] interconnect: qcom: sm8650: " Dmitry Baryshkov
` (3 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on QRD8550
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm8550.c | 640 +++++++++++++++++--------------------
drivers/interconnect/qcom/sm8550.h | 138 --------
2 files changed, 292 insertions(+), 486 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
index 39101b4a423c1bb404a80a83eaf1ff96ccbf2bad..8e3993c189685693d75e184bbaad5692bef6375c 100644
--- a/drivers/interconnect/qcom/sm8550.c
+++ b/drivers/interconnect/qcom/sm8550.c
@@ -18,1103 +18,1033 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
-#include "sm8550.h"
+
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node qxm_sp;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qsm_cfg;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_lpass_gemnoc;
+static struct qcom_icc_node qnm_mdsp;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_nsp_gemnoc;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qnm_lpiaon_noc;
+static struct qcom_icc_node qnm_lpass_lpinoc;
+static struct qcom_icc_node qxm_lpinoc_dsp_axim;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_mdp;
+static struct qcom_icc_node qnm_vapss_hcp;
+static struct qcom_icc_node qnm_video;
+static struct qcom_icc_node qnm_video_cv_cpu;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qsm_mnoc_cfg;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qsm_pcie_anoc_cfg;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node qhm_gic;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mxa;
+static struct qcom_icc_node qhs_cpr_mxc;
+static struct qcom_icc_node qhs_cpr_nspcx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_i2c;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qss_lpass_qtb_cfg;
+static struct qcom_icc_node qss_mnoc_cfg;
+static struct qcom_icc_node qss_nsp_qtb_cfg;
+static struct qcom_icc_node qss_pcie_anoc_cfg;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_tme_cfg;
+static struct qcom_icc_node qss_cfg;
+static struct qcom_icc_node qss_ddrss_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
+static struct qcom_icc_node qns_lpass_aggnoc;
+static struct qcom_icc_node qns_lpi_aon_noc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_pcie_aggre_noc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SM8550_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SM8550_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM8550_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM8550_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM8550_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM8550_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SM8550_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM8550_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM8550_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sp = {
.name = "qxm_sp",
- .id = SM8550_MASTER_SP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = SM8550_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = SM8550_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM8550_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SM8550_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SM8550_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = SM8550_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_QUP_CORE_2 },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qsm_cfg = {
.name = "qsm_cfg",
- .id = SM8550_MASTER_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 44,
- .links = { SM8550_SLAVE_AHB2PHY_SOUTH, SM8550_SLAVE_AHB2PHY_NORTH,
- SM8550_SLAVE_APPSS, SM8550_SLAVE_CAMERA_CFG,
- SM8550_SLAVE_CLK_CTL, SM8550_SLAVE_RBCPR_CX_CFG,
- SM8550_SLAVE_RBCPR_MMCX_CFG, SM8550_SLAVE_RBCPR_MXA_CFG,
- SM8550_SLAVE_RBCPR_MXC_CFG, SM8550_SLAVE_CPR_NSPCX,
- SM8550_SLAVE_CRYPTO_0_CFG, SM8550_SLAVE_CX_RDPM,
- SM8550_SLAVE_DISPLAY_CFG, SM8550_SLAVE_GFX3D_CFG,
- SM8550_SLAVE_I2C, SM8550_SLAVE_IMEM_CFG,
- SM8550_SLAVE_IPA_CFG, SM8550_SLAVE_IPC_ROUTER_CFG,
- SM8550_SLAVE_CNOC_MSS, SM8550_SLAVE_MX_RDPM,
- SM8550_SLAVE_PCIE_0_CFG, SM8550_SLAVE_PCIE_1_CFG,
- SM8550_SLAVE_PDM, SM8550_SLAVE_PIMEM_CFG,
- SM8550_SLAVE_PRNG, SM8550_SLAVE_QDSS_CFG,
- SM8550_SLAVE_QSPI_0, SM8550_SLAVE_QUP_1,
- SM8550_SLAVE_QUP_2, SM8550_SLAVE_SDCC_2,
- SM8550_SLAVE_SDCC_4, SM8550_SLAVE_SPSS_CFG,
- SM8550_SLAVE_TCSR, SM8550_SLAVE_TLMM,
- SM8550_SLAVE_UFS_MEM_CFG, SM8550_SLAVE_USB3_0,
- SM8550_SLAVE_VENUS_CFG, SM8550_SLAVE_VSENSE_CTRL_CFG,
- SM8550_SLAVE_LPASS_QTB_CFG, SM8550_SLAVE_CNOC_MNOC_CFG,
- SM8550_SLAVE_NSP_QTB_CFG, SM8550_SLAVE_PCIE_ANOC_CFG,
- SM8550_SLAVE_QDSS_STM, SM8550_SLAVE_TCU },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_apss, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_cpr_cx,
+ &qhs_cpr_mmcx, &qhs_cpr_mxa,
+ &qhs_cpr_mxc, &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_i2c, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_mss_cfg, &qhs_mx_rdpm,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pdm, &qhs_pimem_cfg,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup1,
+ &qhs_qup2, &qhs_sdc2,
+ &qhs_sdc4, &qhs_spss_cfg,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_ufs_mem_cfg, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
+ &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SM8550_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SM8550_SLAVE_AOSS, SM8550_SLAVE_TME_CFG,
- SM8550_SLAVE_CNOC_CFG, SM8550_SLAVE_DDRSS_CFG,
- SM8550_SLAVE_BOOT_IMEM, SM8550_SLAVE_IMEM },
+ .link_nodes = { &qhs_aoss, &qhs_tme_cfg,
+ &qss_cfg, &qss_ddrss_cfg,
+ &qxs_boot_imem, &qxs_imem, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SM8550_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8550_SLAVE_PCIE_0, SM8550_SLAVE_PCIE_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SM8550_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SM8550_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SM8550_MASTER_APPSS_PROC,
.channels = 3,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
- SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SM8550_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_lpass_gemnoc = {
.name = "qnm_lpass_gemnoc",
- .id = SM8550_MASTER_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
- SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
- .id = SM8550_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
- SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM8550_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM8550_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_nsp_gemnoc = {
.name = "qnm_nsp_gemnoc",
- .id = SM8550_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM8550_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM8550_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
- SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_lpiaon_noc = {
.name = "qnm_lpiaon_noc",
- .id = SM8550_MASTER_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_LPASS_GEM_NOC },
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc, NULL },
};
static struct qcom_icc_node qnm_lpass_lpinoc = {
.name = "qnm_lpass_lpinoc",
- .id = SM8550_MASTER_LPASS_LPINOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
+ .link_nodes = { &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
.name = "qxm_lpinoc_dsp_axim",
- .id = SM8550_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_LPICX_NOC_LPIAON_NOC },
+ .link_nodes = { &qns_lpi_aon_noc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM8550_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SM8550_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = SM8550_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SM8550_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_mdp = {
.name = "qnm_mdp",
- .id = SM8550_MASTER_MDP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_vapss_hcp = {
.name = "qnm_vapss_hcp",
- .id = SM8550_MASTER_CDSP_HCP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video = {
.name = "qnm_video",
- .id = SM8550_MASTER_VIDEO,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cv_cpu = {
.name = "qnm_video_cv_cpu",
- .id = SM8550_MASTER_VIDEO_CV_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SM8550_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = SM8550_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qsm_mnoc_cfg = {
.name = "qsm_mnoc_cfg",
- .id = SM8550_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SM8550_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.name = "qsm_pcie_anoc_cfg",
- .id = SM8550_MASTER_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_SERVICE_PCIE_ANOC },
+ .link_nodes = { &srvc_pcie_aggre_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM8550_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SM8550_MASTER_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
- .id = SM8550_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM8550_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM8550_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM8550_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM8550_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM8550_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SM8550_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SM8550_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = SM8550_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SM8550_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SM8550_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SM8550_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM8550_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM8550_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM8550_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SM8550_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxa = {
.name = "qhs_cpr_mxa",
- .id = SM8550_SLAVE_RBCPR_MXA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxc = {
.name = "qhs_cpr_mxc",
- .id = SM8550_SLAVE_RBCPR_MXC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_nspcx = {
.name = "qhs_cpr_nspcx",
- .id = SM8550_SLAVE_CPR_NSPCX,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM8550_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SM8550_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM8550_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM8550_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_i2c = {
.name = "qhs_i2c",
- .id = SM8550_SLAVE_I2C,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM8550_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM8550_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SM8550_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SM8550_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SM8550_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SM8550_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SM8550_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM8550_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM8550_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM8550_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM8550_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SM8550_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SM8550_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SM8550_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM8550_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM8550_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SM8550_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM8550_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SM8550_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM8550_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM8550_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM8550_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM8550_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_lpass_qtb_cfg = {
.name = "qss_lpass_qtb_cfg",
- .id = SM8550_SLAVE_LPASS_QTB_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_mnoc_cfg = {
.name = "qss_mnoc_cfg",
- .id = SM8550_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qsm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qss_nsp_qtb_cfg = {
.name = "qss_nsp_qtb_cfg",
- .id = SM8550_SLAVE_NSP_QTB_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_pcie_anoc_cfg = {
.name = "qss_pcie_anoc_cfg",
- .id = SM8550_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_MASTER_PCIE_ANOC_CFG },
+ .link_nodes = { &qsm_pcie_anoc_cfg, NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM8550_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM8550_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM8550_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
- .id = SM8550_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_cfg = {
.name = "qss_cfg",
- .id = SM8550_SLAVE_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_MASTER_CNOC_CFG },
+ .link_nodes = { &qsm_cfg, NULL },
};
static struct qcom_icc_node qss_ddrss_cfg = {
.name = "qss_ddrss_cfg",
- .id = SM8550_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = SM8550_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM8550_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SM8550_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SM8550_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SM8550_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM8550_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SM8550_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
.name = "qns_lpass_ag_noc_gemnoc",
- .id = SM8550_SLAVE_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_LPASS_GEM_NOC },
+ .link_nodes = { &qnm_lpass_gemnoc, NULL },
};
static struct qcom_icc_node qns_lpass_aggnoc = {
.name = "qns_lpass_aggnoc",
- .id = SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_LPIAON_NOC },
+ .link_nodes = { &qnm_lpiaon_noc, NULL },
};
static struct qcom_icc_node qns_lpi_aon_noc = {
.name = "qns_lpi_aon_noc",
- .id = SM8550_SLAVE_LPICX_NOC_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_LPASS_LPINOC },
+ .link_nodes = { &qnm_lpass_lpinoc, NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM8550_SLAVE_EBI1,
.channels = 4,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM8550_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SM8550_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM8550_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SM8550_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SM8550_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_pcie_aggre_noc = {
.name = "srvc_pcie_aggre_noc",
- .id = SM8550_SLAVE_SERVICE_PCIE_ANOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM8550_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM8550_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1277,6 +1207,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1300,6 +1231,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1322,6 +1254,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8550_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1382,6 +1315,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1406,6 +1340,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc sm8550_cnoc_main = {
+ .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
@@ -1436,6 +1371,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1451,6 +1387,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1467,6 +1404,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
@@ -1482,6 +1420,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
.bcms = lpass_lpicx_noc_bcms,
@@ -1499,6 +1438,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8550_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1527,6 +1467,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1543,6 +1484,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_nsp_noc = {
+ .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1562,6 +1504,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_pcie_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1585,6 +1528,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8550.h b/drivers/interconnect/qcom/sm8550.h
deleted file mode 100644
index c9b2986e129337c8b8e0dec208b950bea20d213f..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm8550.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * SM8450 interconnect IDs
- *
- * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021, Linaro Limited
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H
-
-#define SM8550_MASTER_A1NOC_SNOC 0
-#define SM8550_MASTER_A2NOC_SNOC 1
-#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2
-#define SM8550_MASTER_APPSS_PROC 3
-#define SM8550_MASTER_CAMNOC_HF 4
-#define SM8550_MASTER_CAMNOC_ICP 5
-#define SM8550_MASTER_CAMNOC_SF 6
-#define SM8550_MASTER_CDSP_HCP 7
-#define SM8550_MASTER_CDSP_PROC 8
-#define SM8550_MASTER_CNOC_CFG 9
-#define SM8550_MASTER_CNOC_MNOC_CFG 10
-#define SM8550_MASTER_COMPUTE_NOC 11
-#define SM8550_MASTER_CRYPTO 12
-#define SM8550_MASTER_GEM_NOC_CNOC 13
-#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14
-#define SM8550_MASTER_GFX3D 15
-#define SM8550_MASTER_GIC 16
-#define SM8550_MASTER_GIC_AHB 17
-#define SM8550_MASTER_GPU_TCU 18
-#define SM8550_MASTER_IPA 19
-#define SM8550_MASTER_LLCC 20
-#define SM8550_MASTER_LPASS_GEM_NOC 21
-#define SM8550_MASTER_LPASS_LPINOC 22
-#define SM8550_MASTER_LPASS_PROC 23
-#define SM8550_MASTER_LPIAON_NOC 24
-#define SM8550_MASTER_MDP 25
-#define SM8550_MASTER_MNOC_HF_MEM_NOC 26
-#define SM8550_MASTER_MNOC_SF_MEM_NOC 27
-#define SM8550_MASTER_MSS_PROC 28
-#define SM8550_MASTER_PCIE_0 29
-#define SM8550_MASTER_PCIE_1 30
-#define SM8550_MASTER_PCIE_ANOC_CFG 31
-#define SM8550_MASTER_QDSS_BAM 32
-#define SM8550_MASTER_QDSS_ETR 33
-#define SM8550_MASTER_QDSS_ETR_1 34
-#define SM8550_MASTER_QSPI_0 35
-#define SM8550_MASTER_QUP_1 36
-#define SM8550_MASTER_QUP_2 37
-#define SM8550_MASTER_QUP_CORE_0 38
-#define SM8550_MASTER_QUP_CORE_1 39
-#define SM8550_MASTER_QUP_CORE_2 40
-#define SM8550_MASTER_SDCC_2 41
-#define SM8550_MASTER_SDCC_4 42
-#define SM8550_MASTER_SNOC_GC_MEM_NOC 43
-#define SM8550_MASTER_SNOC_SF_MEM_NOC 44
-#define SM8550_MASTER_SP 45
-#define SM8550_MASTER_SYS_TCU 46
-#define SM8550_MASTER_UFS_MEM 47
-#define SM8550_MASTER_USB3_0 48
-#define SM8550_MASTER_VIDEO 49
-#define SM8550_MASTER_VIDEO_CV_PROC 50
-#define SM8550_MASTER_VIDEO_PROC 51
-#define SM8550_MASTER_VIDEO_V_PROC 52
-#define SM8550_SLAVE_A1NOC_SNOC 53
-#define SM8550_SLAVE_A2NOC_SNOC 54
-#define SM8550_SLAVE_AHB2PHY_NORTH 55
-#define SM8550_SLAVE_AHB2PHY_SOUTH 56
-#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57
-#define SM8550_SLAVE_AOSS 58
-#define SM8550_SLAVE_APPSS 59
-#define SM8550_SLAVE_BOOT_IMEM 60
-#define SM8550_SLAVE_CAMERA_CFG 61
-#define SM8550_SLAVE_CDSP_MEM_NOC 62
-#define SM8550_SLAVE_CLK_CTL 63
-#define SM8550_SLAVE_CNOC_CFG 64
-#define SM8550_SLAVE_CNOC_MNOC_CFG 65
-#define SM8550_SLAVE_CNOC_MSS 66
-#define SM8550_SLAVE_CPR_NSPCX 67
-#define SM8550_SLAVE_CRYPTO_0_CFG 68
-#define SM8550_SLAVE_CX_RDPM 69
-#define SM8550_SLAVE_DDRSS_CFG 70
-#define SM8550_SLAVE_DISPLAY_CFG 71
-#define SM8550_SLAVE_EBI1 72
-#define SM8550_SLAVE_GEM_NOC_CNOC 73
-#define SM8550_SLAVE_GFX3D_CFG 74
-#define SM8550_SLAVE_I2C 75
-#define SM8550_SLAVE_IMEM 76
-#define SM8550_SLAVE_IMEM_CFG 77
-#define SM8550_SLAVE_IPA_CFG 78
-#define SM8550_SLAVE_IPC_ROUTER_CFG 79
-#define SM8550_SLAVE_LLCC 80
-#define SM8550_SLAVE_LPASS_GEM_NOC 81
-#define SM8550_SLAVE_LPASS_QTB_CFG 82
-#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83
-#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84
-#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85
-#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86
-#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87
-#define SM8550_SLAVE_MX_RDPM 88
-#define SM8550_SLAVE_NSP_QTB_CFG 89
-#define SM8550_SLAVE_PCIE_0 90
-#define SM8550_SLAVE_PCIE_0_CFG 91
-#define SM8550_SLAVE_PCIE_1 92
-#define SM8550_SLAVE_PCIE_1_CFG 93
-#define SM8550_SLAVE_PCIE_ANOC_CFG 94
-#define SM8550_SLAVE_PDM 95
-#define SM8550_SLAVE_PIMEM_CFG 96
-#define SM8550_SLAVE_PRNG 97
-#define SM8550_SLAVE_QDSS_CFG 98
-#define SM8550_SLAVE_QDSS_STM 99
-#define SM8550_SLAVE_QSPI_0 100
-#define SM8550_SLAVE_QUP_1 101
-#define SM8550_SLAVE_QUP_2 102
-#define SM8550_SLAVE_QUP_CORE_0 103
-#define SM8550_SLAVE_QUP_CORE_1 104
-#define SM8550_SLAVE_QUP_CORE_2 105
-#define SM8550_SLAVE_RBCPR_CX_CFG 106
-#define SM8550_SLAVE_RBCPR_MMCX_CFG 107
-#define SM8550_SLAVE_RBCPR_MXA_CFG 108
-#define SM8550_SLAVE_RBCPR_MXC_CFG 109
-#define SM8550_SLAVE_SDCC_2 110
-#define SM8550_SLAVE_SDCC_4 111
-#define SM8550_SLAVE_SERVICE_MNOC 112
-#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113
-#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114
-#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115
-#define SM8550_SLAVE_SPSS_CFG 116
-#define SM8550_SLAVE_TCSR 117
-#define SM8550_SLAVE_TCU 118
-#define SM8550_SLAVE_TLMM 119
-#define SM8550_SLAVE_TME_CFG 120
-#define SM8550_SLAVE_UFS_MEM_CFG 121
-#define SM8550_SLAVE_USB3_0 122
-#define SM8550_SLAVE_VENUS_CFG 123
-#define SM8550_SLAVE_VSENSE_CTRL_CFG 124
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 26/28] interconnect: qcom: sm8650: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (24 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 25/28] interconnect: qcom: sm8550: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 27/28] interconnect: qcom: sm8750: " Dmitry Baryshkov
` (2 subsequent siblings)
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on QRD8650
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm8650.c | 676 +++++++++++++++++--------------------
drivers/interconnect/qcom/sm8650.h | 144 --------
2 files changed, 309 insertions(+), 511 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c
index 9ec2f1308923e5f69c102d2c2d25d25b42711fa0..48b1f9c5e988bebc78f1a724f78664f49e7c1aaa 100644
--- a/drivers/interconnect/qcom/sm8650.c
+++ b/drivers/interconnect/qcom/sm8650.c
@@ -15,8 +15,138 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
-#include "sm8650.h"
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qxm_qup02;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node qxm_sp;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qsm_cfg;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node alm_ubwc_p_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_lpass_gemnoc;
+static struct qcom_icc_node qnm_mdsp;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_nsp_gemnoc;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qnm_ubwc_p;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qnm_lpiaon_noc;
+static struct qcom_icc_node qnm_lpass_lpinoc;
+static struct qcom_icc_node qxm_lpinoc_dsp_axim;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_mdp;
+static struct qcom_icc_node qnm_vapss_hcp;
+static struct qcom_icc_node qnm_video;
+static struct qcom_icc_node qnm_video_cv_cpu;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qsm_mnoc_cfg;
+static struct qcom_icc_node qnm_nsp;
+static struct qcom_icc_node qsm_pcie_anoc_cfg;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_apss_noc;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_hmx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mxa;
+static struct qcom_icc_node qhs_cpr_mxc;
+static struct qcom_icc_node qhs_cpr_nspcx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_i2c;
+static struct qcom_icc_node qhs_i3c_ibi0_cfg;
+static struct qcom_icc_node qhs_i3c_ibi1_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_mx_2_rdpm;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pcie_rscc;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup02;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qss_mnoc_cfg;
+static struct qcom_icc_node qss_nsp_qtb_cfg;
+static struct qcom_icc_node qss_pcie_anoc_cfg;
+static struct qcom_icc_node srvc_cnoc_cfg;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_tme_cfg;
+static struct qcom_icc_node qss_apss;
+static struct qcom_icc_node qss_cfg;
+static struct qcom_icc_node qss_ddrss_cfg;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node srvc_cnoc_main;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
+static struct qcom_icc_node qns_lpass_aggnoc;
+static struct qcom_icc_node qns_lpi_aon_noc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_pcie_aggre_noc;
+static struct qcom_icc_node qns_gemnoc_sf;
static const struct regmap_config icc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -34,12 +164,10 @@ static struct qcom_icc_qosbox qhm_qspi_qos = {
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SM8650_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_qspi_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_qosbox qhm_qup1_qos = {
@@ -52,21 +180,17 @@ static struct qcom_icc_qosbox qhm_qup1_qos = {
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SM8650_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_qup1_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qxm_qup02 = {
.name = "qxm_qup02",
- .id = SM8650_MASTER_QUP_3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8650_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_qosbox xm_sdc4_qos = {
@@ -79,12 +203,10 @@ static struct qcom_icc_qosbox xm_sdc4_qos = {
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM8650_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_sdc4_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_qosbox xm_ufs_mem_qos = {
@@ -97,12 +219,10 @@ static struct qcom_icc_qosbox xm_ufs_mem_qos = {
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM8650_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 16,
.qosbox = &xm_ufs_mem_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_qosbox xm_usb3_0_qos = {
@@ -115,12 +235,10 @@ static struct qcom_icc_qosbox xm_usb3_0_qos = {
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM8650_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_usb3_0_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
@@ -133,12 +251,10 @@ static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM8650_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_qdss_bam_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_qosbox qhm_qup2_qos = {
@@ -151,12 +267,10 @@ static struct qcom_icc_qosbox qhm_qup2_qos = {
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SM8650_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
.qosbox = &qhm_qup2_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_qosbox qxm_crypto_qos = {
@@ -169,12 +283,10 @@ static struct qcom_icc_qosbox qxm_crypto_qos = {
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM8650_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
.qosbox = &qxm_crypto_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_qosbox qxm_ipa_qos = {
@@ -187,21 +299,17 @@ static struct qcom_icc_qosbox qxm_ipa_qos = {
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM8650_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.qosbox = &qxm_ipa_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sp = {
.name = "qxm_sp",
- .id = SM8650_MASTER_SP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8650_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
@@ -214,12 +322,10 @@ static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = SM8650_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_qdss_etr_0_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
@@ -232,12 +338,10 @@ static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = SM8650_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_qdss_etr_1_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_qosbox xm_sdc2_qos = {
@@ -250,92 +354,78 @@ static struct qcom_icc_qosbox xm_sdc2_qos = {
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM8650_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_sdc2_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SM8650_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SM8650_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = SM8650_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_SLAVE_QUP_CORE_2 },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qsm_cfg = {
.name = "qsm_cfg",
- .id = SM8650_MASTER_CNOC_CFG,
- .channels = 1,
- .buswidth = 4,
- .num_links = 46,
- .links = { SM8650_SLAVE_AHB2PHY_SOUTH, SM8650_SLAVE_AHB2PHY_NORTH,
- SM8650_SLAVE_CAMERA_CFG, SM8650_SLAVE_CLK_CTL,
- SM8650_SLAVE_RBCPR_CX_CFG, SM8650_SLAVE_CPR_HMX,
- SM8650_SLAVE_RBCPR_MMCX_CFG, SM8650_SLAVE_RBCPR_MXA_CFG,
- SM8650_SLAVE_RBCPR_MXC_CFG, SM8650_SLAVE_CPR_NSPCX,
- SM8650_SLAVE_CRYPTO_0_CFG, SM8650_SLAVE_CX_RDPM,
- SM8650_SLAVE_DISPLAY_CFG, SM8650_SLAVE_GFX3D_CFG,
- SM8650_SLAVE_I2C, SM8650_SLAVE_I3C_IBI0_CFG,
- SM8650_SLAVE_I3C_IBI1_CFG, SM8650_SLAVE_IMEM_CFG,
- SM8650_SLAVE_CNOC_MSS, SM8650_SLAVE_MX_2_RDPM,
- SM8650_SLAVE_MX_RDPM, SM8650_SLAVE_PCIE_0_CFG,
- SM8650_SLAVE_PCIE_1_CFG, SM8650_SLAVE_PCIE_RSCC,
- SM8650_SLAVE_PDM, SM8650_SLAVE_PRNG,
- SM8650_SLAVE_QDSS_CFG, SM8650_SLAVE_QSPI_0,
- SM8650_SLAVE_QUP_3, SM8650_SLAVE_QUP_1,
- SM8650_SLAVE_QUP_2, SM8650_SLAVE_SDCC_2,
- SM8650_SLAVE_SDCC_4, SM8650_SLAVE_SPSS_CFG,
- SM8650_SLAVE_TCSR, SM8650_SLAVE_TLMM,
- SM8650_SLAVE_UFS_MEM_CFG, SM8650_SLAVE_USB3_0,
- SM8650_SLAVE_VENUS_CFG, SM8650_SLAVE_VSENSE_CTRL_CFG,
- SM8650_SLAVE_CNOC_MNOC_CFG, SM8650_SLAVE_NSP_QTB_CFG,
- SM8650_SLAVE_PCIE_ANOC_CFG, SM8650_SLAVE_SERVICE_CNOC_CFG,
- SM8650_SLAVE_QDSS_STM, SM8650_SLAVE_TCU },
+ .channels = 1,
+ .buswidth = 4,
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_cpr_cx, &qhs_cpr_hmx,
+ &qhs_cpr_mmcx, &qhs_cpr_mxa,
+ &qhs_cpr_mxc, &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_i2c, &qhs_i3c_ibi0_cfg,
+ &qhs_i3c_ibi1_cfg, &qhs_imem_cfg,
+ &qhs_mss_cfg, &qhs_mx_2_rdpm,
+ &qhs_mx_rdpm, &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg, &qhs_pcie_rscc,
+ &qhs_pdm, &qhs_prng,
+ &qhs_qdss_cfg, &qhs_qspi,
+ &qhs_qup02, &qhs_qup1,
+ &qhs_qup2, &qhs_sdc2,
+ &qhs_sdc4, &qhs_spss_cfg,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_ufs_mem_cfg, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qss_mnoc_cfg, &qss_nsp_qtb_cfg,
+ &qss_pcie_anoc_cfg, &srvc_cnoc_cfg,
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SM8650_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 9,
- .links = { SM8650_SLAVE_AOSS, SM8650_SLAVE_IPA_CFG,
- SM8650_SLAVE_IPC_ROUTER_CFG, SM8650_SLAVE_TME_CFG,
- SM8650_SLAVE_APPSS, SM8650_SLAVE_CNOC_CFG,
- SM8650_SLAVE_DDRSS_CFG, SM8650_SLAVE_IMEM,
- SM8650_SLAVE_SERVICE_CNOC },
+ .link_nodes = { &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router, &qhs_tme_cfg,
+ &qss_apss, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem,
+ &srvc_cnoc_main, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SM8650_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
@@ -348,12 +438,10 @@ static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SM8650_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
.qosbox = &alm_gpu_tcu_qos,
- .num_links = 2,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
@@ -366,12 +454,10 @@ static struct qcom_icc_qosbox alm_sys_tcu_qos = {
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SM8650_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.qosbox = &alm_sys_tcu_qos,
- .num_links = 2,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = {
@@ -384,22 +470,18 @@ static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = {
static struct qcom_icc_node alm_ubwc_p_tcu = {
.name = "alm_ubwc_p_tcu",
- .id = SM8650_MASTER_UBWC_P_TCU,
.channels = 1,
.buswidth = 8,
.qosbox = &alm_ubwc_p_tcu_qos,
- .num_links = 2,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SM8650_MASTER_APPSS_PROC,
.channels = 3,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,
- SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_qosbox qnm_gpu_qos = {
@@ -412,12 +494,10 @@ static struct qcom_icc_qosbox qnm_gpu_qos = {
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SM8650_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_gpu_qos,
- .num_links = 2,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
@@ -430,23 +510,19 @@ static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
static struct qcom_icc_node qnm_lpass_gemnoc = {
.name = "qnm_lpass_gemnoc",
- .id = SM8650_MASTER_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
.qosbox = &qnm_lpass_gemnoc_qos,
- .num_links = 3,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,
- SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
- .id = SM8650_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,
- SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
@@ -459,12 +535,10 @@ static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM8650_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_mnoc_hf_qos,
- .num_links = 2,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
@@ -477,12 +551,10 @@ static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM8650_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_mnoc_sf_qos,
- .num_links = 2,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
@@ -495,13 +567,11 @@ static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
static struct qcom_icc_node qnm_nsp_gemnoc = {
.name = "qnm_nsp_gemnoc",
- .id = SM8650_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_nsp_gemnoc_qos,
- .num_links = 3,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,
- SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_qosbox qnm_pcie_qos = {
@@ -514,12 +584,10 @@ static struct qcom_icc_qosbox qnm_pcie_qos = {
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM8650_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
.qosbox = &qnm_pcie_qos,
- .num_links = 2,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
@@ -532,13 +600,11 @@ static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM8650_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.qosbox = &qnm_snoc_sf_qos,
- .num_links = 3,
- .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,
- SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_qosbox qnm_ubwc_p_qos = {
@@ -551,12 +617,10 @@ static struct qcom_icc_qosbox qnm_ubwc_p_qos = {
static struct qcom_icc_node qnm_ubwc_p = {
.name = "qnm_ubwc_p",
- .id = SM8650_MASTER_UBWC_P,
.channels = 1,
.buswidth = 32,
.qosbox = &qnm_ubwc_p_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_qosbox xm_gic_qos = {
@@ -569,48 +633,38 @@ static struct qcom_icc_qosbox xm_gic_qos = {
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM8650_MASTER_GIC,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_gic_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_lpiaon_noc = {
.name = "qnm_lpiaon_noc",
- .id = SM8650_MASTER_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_SLAVE_LPASS_GEM_NOC },
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc, NULL },
};
static struct qcom_icc_node qnm_lpass_lpinoc = {
.name = "qnm_lpass_lpinoc",
- .id = SM8650_MASTER_LPASS_LPINOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
+ .link_nodes = { &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
.name = "qxm_lpinoc_dsp_axim",
- .id = SM8650_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_SLAVE_LPICX_NOC_LPIAON_NOC },
+ .link_nodes = { &qns_lpi_aon_noc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM8650_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
@@ -623,12 +677,10 @@ static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SM8650_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_camnoc_hf_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
@@ -641,12 +693,10 @@ static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = SM8650_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
.qosbox = &qnm_camnoc_icp_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
@@ -659,12 +709,10 @@ static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SM8650_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_camnoc_sf_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_qosbox qnm_mdp_qos = {
@@ -677,21 +725,17 @@ static struct qcom_icc_qosbox qnm_mdp_qos = {
static struct qcom_icc_node qnm_mdp = {
.name = "qnm_mdp",
- .id = SM8650_MASTER_MDP,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_mdp_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_vapss_hcp = {
.name = "qnm_vapss_hcp",
- .id = SM8650_MASTER_CDSP_HCP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_qosbox qnm_video_qos = {
@@ -704,12 +748,10 @@ static struct qcom_icc_qosbox qnm_video_qos = {
static struct qcom_icc_node qnm_video = {
.name = "qnm_video",
- .id = SM8650_MASTER_VIDEO,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_video_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
@@ -722,12 +764,10 @@ static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
static struct qcom_icc_node qnm_video_cv_cpu = {
.name = "qnm_video_cv_cpu",
- .id = SM8650_MASTER_VIDEO_CV_PROC,
.channels = 1,
.buswidth = 8,
.qosbox = &qnm_video_cv_cpu_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_qosbox qnm_video_cvp_qos = {
@@ -740,12 +780,10 @@ static struct qcom_icc_qosbox qnm_video_cvp_qos = {
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SM8650_MASTER_VIDEO_PROC,
.channels = 2,
.buswidth = 32,
.qosbox = &qnm_video_cvp_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
@@ -758,39 +796,31 @@ static struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = SM8650_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
.qosbox = &qnm_video_v_cpu_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qsm_mnoc_cfg = {
.name = "qsm_mnoc_cfg",
- .id = SM8650_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qnm_nsp = {
.name = "qnm_nsp",
- .id = SM8650_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8650_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.name = "qsm_pcie_anoc_cfg",
- .id = SM8650_MASTER_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_SLAVE_SERVICE_PCIE_ANOC },
+ .link_nodes = { &srvc_pcie_aggre_noc, NULL },
};
static struct qcom_icc_qosbox xm_pcie3_0_qos = {
@@ -803,12 +833,10 @@ static struct qcom_icc_qosbox xm_pcie3_0_qos = {
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM8650_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
.qosbox = &xm_pcie3_0_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_qosbox xm_pcie3_1_qos = {
@@ -821,30 +849,24 @@ static struct qcom_icc_qosbox xm_pcie3_1_qos = {
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SM8650_MASTER_PCIE_1,
.channels = 1,
.buswidth = 16,
.qosbox = &xm_pcie3_1_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM8650_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM8650_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_qosbox qnm_apss_noc_qos = {
@@ -857,636 +879,542 @@ static struct qcom_icc_qosbox qnm_apss_noc_qos = {
static struct qcom_icc_node qnm_apss_noc = {
.name = "qnm_apss_noc",
- .id = SM8650_MASTER_APSS_NOC,
.channels = 1,
.buswidth = 4,
.qosbox = &qnm_apss_noc_qos,
- .num_links = 1,
- .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM8650_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM8650_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SM8650_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SM8650_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = SM8650_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SM8650_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SM8650_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM8650_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM8650_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM8650_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_hmx = {
.name = "qhs_cpr_hmx",
- .id = SM8650_SLAVE_CPR_HMX,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SM8650_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxa = {
.name = "qhs_cpr_mxa",
- .id = SM8650_SLAVE_RBCPR_MXA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxc = {
.name = "qhs_cpr_mxc",
- .id = SM8650_SLAVE_RBCPR_MXC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_nspcx = {
.name = "qhs_cpr_nspcx",
- .id = SM8650_SLAVE_CPR_NSPCX,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM8650_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SM8650_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM8650_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM8650_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_i2c = {
.name = "qhs_i2c",
- .id = SM8650_SLAVE_I2C,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_i3c_ibi0_cfg = {
.name = "qhs_i3c_ibi0_cfg",
- .id = SM8650_SLAVE_I3C_IBI0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_i3c_ibi1_cfg = {
.name = "qhs_i3c_ibi1_cfg",
- .id = SM8650_SLAVE_I3C_IBI1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM8650_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SM8650_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_2_rdpm = {
.name = "qhs_mx_2_rdpm",
- .id = SM8650_SLAVE_MX_2_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SM8650_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SM8650_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SM8650_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_rscc = {
.name = "qhs_pcie_rscc",
- .id = SM8650_SLAVE_PCIE_RSCC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM8650_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM8650_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM8650_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SM8650_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup02 = {
.name = "qhs_qup02",
- .id = SM8650_SLAVE_QUP_3,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SM8650_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SM8650_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM8650_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM8650_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SM8650_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM8650_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SM8650_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM8650_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM8650_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM8650_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM8650_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_mnoc_cfg = {
.name = "qss_mnoc_cfg",
- .id = SM8650_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qsm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qss_nsp_qtb_cfg = {
.name = "qss_nsp_qtb_cfg",
- .id = SM8650_SLAVE_NSP_QTB_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_pcie_anoc_cfg = {
.name = "qss_pcie_anoc_cfg",
- .id = SM8650_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_MASTER_PCIE_ANOC_CFG },
+ .link_nodes = { &qsm_pcie_anoc_cfg, NULL },
};
static struct qcom_icc_node srvc_cnoc_cfg = {
.name = "srvc_cnoc_cfg",
- .id = SM8650_SLAVE_SERVICE_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM8650_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM8650_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM8650_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM8650_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SM8650_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
- .id = SM8650_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_apss = {
.name = "qss_apss",
- .id = SM8650_SLAVE_APPSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_cfg = {
.name = "qss_cfg",
- .id = SM8650_SLAVE_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8650_MASTER_CNOC_CFG },
+ .link_nodes = { &qsm_cfg, NULL },
};
static struct qcom_icc_node qss_ddrss_cfg = {
.name = "qss_ddrss_cfg",
- .id = SM8650_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM8650_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_cnoc_main = {
.name = "srvc_cnoc_main",
- .id = SM8650_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SM8650_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SM8650_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SM8650_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM8650_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SM8650_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8650_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
.name = "qns_lpass_ag_noc_gemnoc",
- .id = SM8650_SLAVE_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_LPASS_GEM_NOC },
+ .link_nodes = { &qnm_lpass_gemnoc, NULL },
};
static struct qcom_icc_node qns_lpass_aggnoc = {
.name = "qns_lpass_aggnoc",
- .id = SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_LPIAON_NOC },
+ .link_nodes = { &qnm_lpiaon_noc, NULL },
};
static struct qcom_icc_node qns_lpi_aon_noc = {
.name = "qns_lpi_aon_noc",
- .id = SM8650_SLAVE_LPICX_NOC_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_LPASS_LPINOC },
+ .link_nodes = { &qnm_lpass_lpinoc, NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM8650_SLAVE_EBI1,
.channels = 4,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM8650_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8650_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SM8650_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8650_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM8650_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SM8650_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8650_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SM8650_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_pcie_aggre_noc = {
.name = "srvc_pcie_aggre_noc",
- .id = SM8650_SLAVE_SERVICE_PCIE_ANOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM8650_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8650_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1639,6 +1567,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_aggre1_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
@@ -1661,6 +1590,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_aggre2_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
@@ -1684,6 +1614,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8650_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1745,6 +1676,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_config_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
@@ -1773,6 +1705,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc sm8650_cnoc_main = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
@@ -1806,6 +1739,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_gem_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
@@ -1819,6 +1753,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
@@ -1834,6 +1769,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
@@ -1847,6 +1783,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
@@ -1863,6 +1800,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8650_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1891,6 +1829,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_mmss_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
@@ -1908,6 +1847,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_nsp_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
@@ -1928,6 +1868,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_pcie_anoc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
@@ -1949,6 +1890,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_system_noc = {
+ .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
diff --git a/drivers/interconnect/qcom/sm8650.h b/drivers/interconnect/qcom/sm8650.h
deleted file mode 100644
index b6610225b38acce12c47046769bb0460a1ae4229..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm8650.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * SM8650 interconnect IDs
- *
- * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Linaro Limited
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H
-
-#define SM8650_MASTER_A1NOC_SNOC 0
-#define SM8650_MASTER_A2NOC_SNOC 1
-#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2
-#define SM8650_MASTER_APPSS_PROC 3
-#define SM8650_MASTER_CAMNOC_HF 4
-#define SM8650_MASTER_CAMNOC_ICP 5
-#define SM8650_MASTER_CAMNOC_SF 6
-#define SM8650_MASTER_CDSP_HCP 7
-#define SM8650_MASTER_CDSP_PROC 8
-#define SM8650_MASTER_CNOC_CFG 9
-#define SM8650_MASTER_CNOC_MNOC_CFG 10
-#define SM8650_MASTER_COMPUTE_NOC 11
-#define SM8650_MASTER_CRYPTO 12
-#define SM8650_MASTER_GEM_NOC_CNOC 13
-#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14
-#define SM8650_MASTER_GFX3D 15
-#define SM8650_MASTER_GIC 16
-#define SM8650_MASTER_GPU_TCU 17
-#define SM8650_MASTER_IPA 18
-#define SM8650_MASTER_LLCC 19
-#define SM8650_MASTER_LPASS_GEM_NOC 20
-#define SM8650_MASTER_LPASS_LPINOC 21
-#define SM8650_MASTER_LPASS_PROC 22
-#define SM8650_MASTER_LPIAON_NOC 23
-#define SM8650_MASTER_MDP 24
-#define SM8650_MASTER_MNOC_HF_MEM_NOC 25
-#define SM8650_MASTER_MNOC_SF_MEM_NOC 26
-#define SM8650_MASTER_MSS_PROC 27
-#define SM8650_MASTER_PCIE_0 28
-#define SM8650_MASTER_PCIE_1 29
-#define SM8650_MASTER_PCIE_ANOC_CFG 30
-#define SM8650_MASTER_QDSS_BAM 31
-#define SM8650_MASTER_QDSS_ETR 32
-#define SM8650_MASTER_QDSS_ETR_1 33
-#define SM8650_MASTER_QSPI_0 34
-#define SM8650_MASTER_QUP_1 35
-#define SM8650_MASTER_QUP_2 36
-#define SM8650_MASTER_QUP_3 37
-#define SM8650_MASTER_QUP_CORE_0 38
-#define SM8650_MASTER_QUP_CORE_1 39
-#define SM8650_MASTER_QUP_CORE_2 40
-#define SM8650_MASTER_SDCC_2 41
-#define SM8650_MASTER_SDCC_4 42
-#define SM8650_MASTER_SNOC_SF_MEM_NOC 43
-#define SM8650_MASTER_SP 44
-#define SM8650_MASTER_SYS_TCU 45
-#define SM8650_MASTER_UBWC_P 46
-#define SM8650_MASTER_UBWC_P_TCU 47
-#define SM8650_MASTER_UFS_MEM 48
-#define SM8650_MASTER_USB3_0 49
-#define SM8650_MASTER_VIDEO 50
-#define SM8650_MASTER_VIDEO_CV_PROC 51
-#define SM8650_MASTER_VIDEO_PROC 52
-#define SM8650_MASTER_VIDEO_V_PROC 53
-#define SM8650_SLAVE_A1NOC_SNOC 54
-#define SM8650_SLAVE_A2NOC_SNOC 55
-#define SM8650_SLAVE_AHB2PHY_NORTH 56
-#define SM8650_SLAVE_AHB2PHY_SOUTH 57
-#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58
-#define SM8650_SLAVE_AOSS 59
-#define SM8650_SLAVE_APPSS 60
-#define SM8650_SLAVE_CAMERA_CFG 61
-#define SM8650_SLAVE_CDSP_MEM_NOC 62
-#define SM8650_SLAVE_CLK_CTL 63
-#define SM8650_SLAVE_CNOC_CFG 64
-#define SM8650_SLAVE_CNOC_MNOC_CFG 65
-#define SM8650_SLAVE_CNOC_MSS 66
-#define SM8650_SLAVE_CPR_HMX 67
-#define SM8650_SLAVE_CPR_NSPCX 68
-#define SM8650_SLAVE_CRYPTO_0_CFG 69
-#define SM8650_SLAVE_CX_RDPM 70
-#define SM8650_SLAVE_DDRSS_CFG 71
-#define SM8650_SLAVE_DISPLAY_CFG 72
-#define SM8650_SLAVE_EBI1 73
-#define SM8650_SLAVE_GEM_NOC_CNOC 74
-#define SM8650_SLAVE_GFX3D_CFG 75
-#define SM8650_SLAVE_I2C 76
-#define SM8650_SLAVE_I3C_IBI0_CFG 77
-#define SM8650_SLAVE_I3C_IBI1_CFG 78
-#define SM8650_SLAVE_IMEM 79
-#define SM8650_SLAVE_IMEM_CFG 80
-#define SM8650_SLAVE_IPA_CFG 81
-#define SM8650_SLAVE_IPC_ROUTER_CFG 82
-#define SM8650_SLAVE_LLCC 83
-#define SM8650_SLAVE_LPASS_GEM_NOC 84
-#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85
-#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86
-#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87
-#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88
-#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89
-#define SM8650_SLAVE_MX_2_RDPM 90
-#define SM8650_SLAVE_MX_RDPM 91
-#define SM8650_SLAVE_NSP_QTB_CFG 92
-#define SM8650_SLAVE_PCIE_0 93
-#define SM8650_SLAVE_PCIE_1 94
-#define SM8650_SLAVE_PCIE_0_CFG 95
-#define SM8650_SLAVE_PCIE_1_CFG 96
-#define SM8650_SLAVE_PCIE_ANOC_CFG 97
-#define SM8650_SLAVE_PCIE_RSCC 98
-#define SM8650_SLAVE_PDM 99
-#define SM8650_SLAVE_PRNG 100
-#define SM8650_SLAVE_QDSS_CFG 101
-#define SM8650_SLAVE_QDSS_STM 102
-#define SM8650_SLAVE_QSPI_0 103
-#define SM8650_SLAVE_QUP_1 104
-#define SM8650_SLAVE_QUP_2 105
-#define SM8650_SLAVE_QUP_3 106
-#define SM8650_SLAVE_QUP_CORE_0 107
-#define SM8650_SLAVE_QUP_CORE_1 108
-#define SM8650_SLAVE_QUP_CORE_2 109
-#define SM8650_SLAVE_RBCPR_CX_CFG 110
-#define SM8650_SLAVE_RBCPR_MMCX_CFG 111
-#define SM8650_SLAVE_RBCPR_MXA_CFG 112
-#define SM8650_SLAVE_RBCPR_MXC_CFG 113
-#define SM8650_SLAVE_SDCC_2 114
-#define SM8650_SLAVE_SDCC_4 115
-#define SM8650_SLAVE_SERVICE_CNOC 116
-#define SM8650_SLAVE_SERVICE_CNOC_CFG 117
-#define SM8650_SLAVE_SERVICE_MNOC 118
-#define SM8650_SLAVE_SERVICE_PCIE_ANOC 119
-#define SM8650_SLAVE_SNOC_GEM_NOC_SF 120
-#define SM8650_SLAVE_SPSS_CFG 121
-#define SM8650_SLAVE_TCSR 122
-#define SM8650_SLAVE_TCU 123
-#define SM8650_SLAVE_TLMM 124
-#define SM8650_SLAVE_TME_CFG 125
-#define SM8650_SLAVE_UFS_MEM_CFG 126
-#define SM8650_SLAVE_USB3_0 127
-#define SM8650_SLAVE_VENUS_CFG 128
-#define SM8650_SLAVE_VSENSE_CTRL_CFG 129
-#define SM8650_MASTER_APSS_NOC 130
-
-#endif
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 27/28] interconnect: qcom: sm8750: convert to dynamic IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (25 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 26/28] interconnect: qcom: sm8650: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-04 16:35 ` [PATCH v2 28/28] interconnect: qcom: icc-rpmh: drop support for non-dynamic IDS Dmitry Baryshkov
2025-07-16 15:22 ` [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/sm8750.c | 736 ++++++++++++++-----------------------
1 file changed, 280 insertions(+), 456 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom/sm8750.c
index eba39bf966c27254ca5df43c9acd7435a69726a2..0c9b39ea4f9ec970112f2a9117d16e70a6f41c93 100644
--- a/drivers/interconnect/qcom/sm8750.c
+++ b/drivers/interconnect/qcom/sm8750.c
@@ -14,1181 +14,991 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#define SM8750_MASTER_GPU_TCU 0
-#define SM8750_MASTER_SYS_TCU 1
-#define SM8750_MASTER_APPSS_PROC 2
-#define SM8750_MASTER_LLCC 3
-#define SM8750_MASTER_QDSS_BAM 4
-#define SM8750_MASTER_QSPI_0 5
-#define SM8750_MASTER_QUP_1 6
-#define SM8750_MASTER_QUP_2 7
-#define SM8750_MASTER_A1NOC_SNOC 8
-#define SM8750_MASTER_A2NOC_SNOC 9
-#define SM8750_MASTER_CAMNOC_HF 10
-#define SM8750_MASTER_CAMNOC_NRT_ICP_SF 11
-#define SM8750_MASTER_CAMNOC_RT_CDM_SF 12
-#define SM8750_MASTER_CAMNOC_SF 13
-#define SM8750_MASTER_GEM_NOC_CNOC 14
-#define SM8750_MASTER_GEM_NOC_PCIE_SNOC 15
-#define SM8750_MASTER_GFX3D 16
-#define SM8750_MASTER_LPASS_GEM_NOC 17
-#define SM8750_MASTER_LPASS_LPINOC 18
-#define SM8750_MASTER_LPIAON_NOC 19
-#define SM8750_MASTER_LPASS_PROC 20
-#define SM8750_MASTER_MDP 21
-#define SM8750_MASTER_MSS_PROC 22
-#define SM8750_MASTER_MNOC_HF_MEM_NOC 23
-#define SM8750_MASTER_MNOC_SF_MEM_NOC 24
-#define SM8750_MASTER_CDSP_PROC 25
-#define SM8750_MASTER_COMPUTE_NOC 26
-#define SM8750_MASTER_ANOC_PCIE_GEM_NOC 27
-#define SM8750_MASTER_SNOC_SF_MEM_NOC 28
-#define SM8750_MASTER_UBWC_P 29
-#define SM8750_MASTER_CDSP_HCP 30
-#define SM8750_MASTER_VIDEO_CV_PROC 31
-#define SM8750_MASTER_VIDEO_EVA 32
-#define SM8750_MASTER_VIDEO_MVP 33
-#define SM8750_MASTER_VIDEO_V_PROC 34
-#define SM8750_MASTER_CNOC_CFG 35
-#define SM8750_MASTER_CNOC_MNOC_CFG 36
-#define SM8750_MASTER_PCIE_ANOC_CFG 37
-#define SM8750_MASTER_QUP_CORE_0 38
-#define SM8750_MASTER_QUP_CORE_1 39
-#define SM8750_MASTER_QUP_CORE_2 40
-#define SM8750_MASTER_CRYPTO 41
-#define SM8750_MASTER_IPA 42
-#define SM8750_MASTER_QUP_3 43
-#define SM8750_MASTER_SOCCP_AGGR_NOC 44
-#define SM8750_MASTER_SP 45
-#define SM8750_MASTER_GIC 46
-#define SM8750_MASTER_PCIE_0 47
-#define SM8750_MASTER_QDSS_ETR 48
-#define SM8750_MASTER_QDSS_ETR_1 49
-#define SM8750_MASTER_SDCC_2 50
-#define SM8750_MASTER_SDCC_4 51
-#define SM8750_MASTER_UFS_MEM 52
-#define SM8750_MASTER_USB3_0 53
-#define SM8750_SLAVE_UBWC_P 54
-#define SM8750_SLAVE_EBI1 55
-#define SM8750_SLAVE_AHB2PHY_SOUTH 56
-#define SM8750_SLAVE_AHB2PHY_NORTH 57
-#define SM8750_SLAVE_AOSS 58
-#define SM8750_SLAVE_CAMERA_CFG 59
-#define SM8750_SLAVE_CLK_CTL 60
-#define SM8750_SLAVE_CRYPTO_0_CFG 61
-#define SM8750_SLAVE_DISPLAY_CFG 62
-#define SM8750_SLAVE_EVA_CFG 63
-#define SM8750_SLAVE_GFX3D_CFG 64
-#define SM8750_SLAVE_I2C 65
-#define SM8750_SLAVE_I3C_IBI0_CFG 66
-#define SM8750_SLAVE_I3C_IBI1_CFG 67
-#define SM8750_SLAVE_IMEM_CFG 68
-#define SM8750_SLAVE_IPA_CFG 69
-#define SM8750_SLAVE_IPC_ROUTER_CFG 70
-#define SM8750_SLAVE_CNOC_MSS 71
-#define SM8750_SLAVE_PCIE_CFG 72
-#define SM8750_SLAVE_PRNG 73
-#define SM8750_SLAVE_QDSS_CFG 74
-#define SM8750_SLAVE_QSPI_0 75
-#define SM8750_SLAVE_QUP_3 76
-#define SM8750_SLAVE_QUP_1 77
-#define SM8750_SLAVE_QUP_2 78
-#define SM8750_SLAVE_SDCC_2 79
-#define SM8750_SLAVE_SDCC_4 80
-#define SM8750_SLAVE_SOCCP 81
-#define SM8750_SLAVE_SPSS_CFG 82
-#define SM8750_SLAVE_TCSR 83
-#define SM8750_SLAVE_TLMM 84
-#define SM8750_SLAVE_TME_CFG 85
-#define SM8750_SLAVE_UFS_MEM_CFG 86
-#define SM8750_SLAVE_USB3_0 87
-#define SM8750_SLAVE_VENUS_CFG 88
-#define SM8750_SLAVE_VSENSE_CTRL_CFG 89
-#define SM8750_SLAVE_A1NOC_SNOC 90
-#define SM8750_SLAVE_A2NOC_SNOC 91
-#define SM8750_SLAVE_APPSS 92
-#define SM8750_SLAVE_GEM_NOC_CNOC 93
-#define SM8750_SLAVE_SNOC_GEM_NOC_SF 94
-#define SM8750_SLAVE_LLCC 95
-#define SM8750_SLAVE_LPASS_GEM_NOC 96
-#define SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC 97
-#define SM8750_SLAVE_LPICX_NOC_LPIAON_NOC 98
-#define SM8750_SLAVE_MNOC_HF_MEM_NOC 99
-#define SM8750_SLAVE_MNOC_SF_MEM_NOC 100
-#define SM8750_SLAVE_CDSP_MEM_NOC 101
-#define SM8750_SLAVE_MEM_NOC_PCIE_SNOC 102
-#define SM8750_SLAVE_ANOC_PCIE_GEM_NOC 103
-#define SM8750_SLAVE_CNOC_CFG 104
-#define SM8750_SLAVE_DDRSS_CFG 105
-#define SM8750_SLAVE_CNOC_MNOC_CFG 106
-#define SM8750_SLAVE_PCIE_ANOC_CFG 107
-#define SM8750_SLAVE_QUP_CORE_0 108
-#define SM8750_SLAVE_QUP_CORE_1 109
-#define SM8750_SLAVE_QUP_CORE_2 110
-#define SM8750_SLAVE_BOOT_IMEM 111
-#define SM8750_SLAVE_IMEM 112
-#define SM8750_SLAVE_BOOT_IMEM_2 113
-#define SM8750_SLAVE_SERVICE_CNOC 114
-#define SM8750_SLAVE_SERVICE_MNOC 115
-#define SM8750_SLAVE_SERVICE_PCIE_ANOC 116
-#define SM8750_SLAVE_PCIE_0 117
-#define SM8750_SLAVE_QDSS_STM 118
-#define SM8750_SLAVE_TCU 119
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qxm_qup02;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node qxm_soccp;
+static struct qcom_icc_node qxm_sp;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qsm_cfg;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_lpass_gemnoc;
+static struct qcom_icc_node qnm_mdsp;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_nsp_gemnoc;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qnm_ubwc_p;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qnm_lpiaon_noc;
+static struct qcom_icc_node qnm_lpass_lpinoc;
+static struct qcom_icc_node qnm_lpinoc_dsp_qns4m;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_nrt_icp_sf;
+static struct qcom_icc_node qnm_camnoc_rt_cdm_sf;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_mdp;
+static struct qcom_icc_node qnm_vapss_hcp;
+static struct qcom_icc_node qnm_video_cv_cpu;
+static struct qcom_icc_node qnm_video_eva;
+static struct qcom_icc_node qnm_video_mvp;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qsm_mnoc_cfg;
+static struct qcom_icc_node qnm_nsp;
+static struct qcom_icc_node qsm_pcie_anoc_cfg;
+static struct qcom_icc_node xm_pcie3;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_eva_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_i2c;
+static struct qcom_icc_node qhs_i3c_ibi0_cfg;
+static struct qcom_icc_node qhs_i3c_ibi1_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_pcie_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup02;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qss_mnoc_cfg;
+static struct qcom_icc_node qss_pcie_anoc_cfg;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_soccp;
+static struct qcom_icc_node qhs_tme_cfg;
+static struct qcom_icc_node qns_apss;
+static struct qcom_icc_node qss_cfg;
+static struct qcom_icc_node qss_ddrss_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_modem_boot_imem;
+static struct qcom_icc_node srvc_cnoc_main;
+static struct qcom_icc_node xs_pcie;
+static struct qcom_icc_node chs_ubwc_p;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
+static struct qcom_icc_node qns_lpass_aggnoc;
+static struct qcom_icc_node qns_lpi_aon_noc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_pcie_aggre_noc;
+static struct qcom_icc_node qns_gemnoc_sf;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SM8750_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SM8750_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qxm_qup02 = {
.name = "qxm_qup02",
- .id = SM8750_MASTER_QUP_3,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM8750_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM8750_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM8750_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM8750_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SM8750_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM8750_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM8750_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_soccp = {
.name = "qxm_soccp",
- .id = SM8750_MASTER_SOCCP_AGGR_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sp = {
.name = "qxm_sp",
- .id = SM8750_MASTER_SP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = SM8750_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = SM8750_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM8750_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SM8750_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SM8750_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = SM8750_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_QUP_CORE_2 },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qsm_cfg = {
.name = "qsm_cfg",
- .id = SM8750_MASTER_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 33,
- .links = { SM8750_SLAVE_AHB2PHY_SOUTH, SM8750_SLAVE_AHB2PHY_NORTH,
- SM8750_SLAVE_CAMERA_CFG, SM8750_SLAVE_CLK_CTL,
- SM8750_SLAVE_CRYPTO_0_CFG, SM8750_SLAVE_DISPLAY_CFG,
- SM8750_SLAVE_EVA_CFG, SM8750_SLAVE_GFX3D_CFG,
- SM8750_SLAVE_I2C, SM8750_SLAVE_I3C_IBI0_CFG,
- SM8750_SLAVE_I3C_IBI1_CFG, SM8750_SLAVE_IMEM_CFG,
- SM8750_SLAVE_CNOC_MSS, SM8750_SLAVE_PCIE_CFG,
- SM8750_SLAVE_PRNG, SM8750_SLAVE_QDSS_CFG,
- SM8750_SLAVE_QSPI_0, SM8750_SLAVE_QUP_3,
- SM8750_SLAVE_QUP_1, SM8750_SLAVE_QUP_2,
- SM8750_SLAVE_SDCC_2, SM8750_SLAVE_SDCC_4,
- SM8750_SLAVE_SPSS_CFG, SM8750_SLAVE_TCSR,
- SM8750_SLAVE_TLMM, SM8750_SLAVE_UFS_MEM_CFG,
- SM8750_SLAVE_USB3_0, SM8750_SLAVE_VENUS_CFG,
- SM8750_SLAVE_VSENSE_CTRL_CFG, SM8750_SLAVE_CNOC_MNOC_CFG,
- SM8750_SLAVE_PCIE_ANOC_CFG, SM8750_SLAVE_QDSS_STM,
- SM8750_SLAVE_TCU },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_crypto0_cfg, &qhs_display_cfg,
+ &qhs_eva_cfg, &qhs_gpuss_cfg,
+ &qhs_i2c, &qhs_i3c_ibi0_cfg,
+ &qhs_i3c_ibi1_cfg, &qhs_imem_cfg,
+ &qhs_mss_cfg, &qhs_pcie_cfg,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup02,
+ &qhs_qup1, &qhs_qup2,
+ &qhs_sdc2, &qhs_sdc4,
+ &qhs_spss_cfg, &qhs_tcsr,
+ &qhs_tlmm, &qhs_ufs_mem_cfg,
+ &qhs_usb3_0, &qhs_venus_cfg,
+ &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg,
+ &qss_pcie_anoc_cfg, &xs_qdss_stm,
+ &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SM8750_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 12,
- .links = { SM8750_SLAVE_AOSS, SM8750_SLAVE_IPA_CFG,
- SM8750_SLAVE_IPC_ROUTER_CFG, SM8750_SLAVE_SOCCP,
- SM8750_SLAVE_TME_CFG, SM8750_SLAVE_APPSS,
- SM8750_SLAVE_CNOC_CFG, SM8750_SLAVE_DDRSS_CFG,
- SM8750_SLAVE_BOOT_IMEM, SM8750_SLAVE_IMEM,
- SM8750_SLAVE_BOOT_IMEM_2, SM8750_SLAVE_SERVICE_CNOC },
+ .link_nodes = { &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router, &qhs_soccp,
+ &qhs_tme_cfg, &qns_apss,
+ &qss_cfg, &qss_ddrss_cfg,
+ &qxs_boot_imem, &qxs_imem,
+ &qxs_modem_boot_imem, &srvc_cnoc_main, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SM8750_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_PCIE_0 },
+ .link_nodes = { &xs_pcie, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SM8750_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SM8750_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SM8750_MASTER_APPSS_PROC,
.channels = 4,
.buswidth = 32,
- .num_links = 4,
- .links = { SM8750_SLAVE_UBWC_P, SM8750_SLAVE_GEM_NOC_CNOC,
- SM8750_SLAVE_LLCC, SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &chs_ubwc_p, &qns_gem_noc_cnoc,
+ &qns_llcc, &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SM8750_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_lpass_gemnoc = {
.name = "qnm_lpass_gemnoc",
- .id = SM8750_MASTER_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC,
- SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
- .id = SM8750_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC,
- SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM8750_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM8750_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_nsp_gemnoc = {
.name = "qnm_nsp_gemnoc",
- .id = SM8750_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC,
- SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM8750_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM8750_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC,
- SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_ubwc_p = {
.name = "qnm_ubwc_p",
- .id = SM8750_MASTER_UBWC_P,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM8750_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_lpiaon_noc = {
.name = "qnm_lpiaon_noc",
- .id = SM8750_MASTER_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_SLAVE_LPASS_GEM_NOC },
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc, NULL },
};
static struct qcom_icc_node qnm_lpass_lpinoc = {
.name = "qnm_lpass_lpinoc",
- .id = SM8750_MASTER_LPASS_LPINOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
+ .link_nodes = { &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
.name = "qnm_lpinoc_dsp_qns4m",
- .id = SM8750_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_SLAVE_LPICX_NOC_LPIAON_NOC },
+ .link_nodes = { &qns_lpi_aon_noc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM8750_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SM8750_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
.name = "qnm_camnoc_nrt_icp_sf",
- .id = SM8750_MASTER_CAMNOC_NRT_ICP_SF,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
.name = "qnm_camnoc_rt_cdm_sf",
- .id = SM8750_MASTER_CAMNOC_RT_CDM_SF,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SM8750_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_mdp = {
.name = "qnm_mdp",
- .id = SM8750_MASTER_MDP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_vapss_hcp = {
.name = "qnm_vapss_hcp",
- .id = SM8750_MASTER_CDSP_HCP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cv_cpu = {
.name = "qnm_video_cv_cpu",
- .id = SM8750_MASTER_VIDEO_CV_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_eva = {
.name = "qnm_video_eva",
- .id = SM8750_MASTER_VIDEO_EVA,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_mvp = {
.name = "qnm_video_mvp",
- .id = SM8750_MASTER_VIDEO_MVP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = SM8750_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qsm_mnoc_cfg = {
.name = "qsm_mnoc_cfg",
- .id = SM8750_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qnm_nsp = {
.name = "qnm_nsp",
- .id = SM8750_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.name = "qsm_pcie_anoc_cfg",
- .id = SM8750_MASTER_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_SLAVE_SERVICE_PCIE_ANOC },
+ .link_nodes = { &srvc_pcie_aggre_noc, NULL },
};
static struct qcom_icc_node xm_pcie3 = {
.name = "xm_pcie3",
- .id = SM8750_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM8750_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM8750_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM8750_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM8750_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SM8750_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SM8750_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = SM8750_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SM8750_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SM8750_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM8750_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM8750_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM8750_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM8750_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_eva_cfg = {
.name = "qhs_eva_cfg",
- .id = SM8750_SLAVE_EVA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM8750_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_i2c = {
.name = "qhs_i2c",
- .id = SM8750_SLAVE_I2C,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_i3c_ibi0_cfg = {
.name = "qhs_i3c_ibi0_cfg",
- .id = SM8750_SLAVE_I3C_IBI0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_i3c_ibi1_cfg = {
.name = "qhs_i3c_ibi1_cfg",
- .id = SM8750_SLAVE_I3C_IBI1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM8750_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SM8750_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie_cfg = {
.name = "qhs_pcie_cfg",
- .id = SM8750_SLAVE_PCIE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM8750_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM8750_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SM8750_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup02 = {
.name = "qhs_qup02",
- .id = SM8750_SLAVE_QUP_3,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SM8750_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SM8750_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM8750_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM8750_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SM8750_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM8750_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SM8750_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM8750_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM8750_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM8750_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM8750_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_mnoc_cfg = {
.name = "qss_mnoc_cfg",
- .id = SM8750_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qsm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qss_pcie_anoc_cfg = {
.name = "qss_pcie_anoc_cfg",
- .id = SM8750_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_MASTER_PCIE_ANOC_CFG },
+ .link_nodes = { &qsm_pcie_anoc_cfg, NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM8750_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM8750_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM8750_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM8750_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SM8750_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_soccp = {
.name = "qhs_soccp",
- .id = SM8750_SLAVE_SOCCP,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
- .id = SM8750_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_apss = {
.name = "qns_apss",
- .id = SM8750_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_cfg = {
.name = "qss_cfg",
- .id = SM8750_SLAVE_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8750_MASTER_CNOC_CFG },
+ .link_nodes = { &qsm_cfg, NULL },
};
static struct qcom_icc_node qss_ddrss_cfg = {
.name = "qss_ddrss_cfg",
- .id = SM8750_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = SM8750_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM8750_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_modem_boot_imem = {
.name = "qxs_modem_boot_imem",
- .id = SM8750_SLAVE_BOOT_IMEM_2,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node srvc_cnoc_main = {
.name = "srvc_cnoc_main",
- .id = SM8750_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
- .id = SM8750_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node chs_ubwc_p = {
.name = "chs_ubwc_p",
- .id = SM8750_SLAVE_UBWC_P,
.channels = 1,
.buswidth = 32,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SM8750_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM8750_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SM8750_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
.name = "qns_lpass_ag_noc_gemnoc",
- .id = SM8750_SLAVE_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_MASTER_LPASS_GEM_NOC },
+ .link_nodes = { &qnm_lpass_gemnoc, NULL },
};
static struct qcom_icc_node qns_lpass_aggnoc = {
.name = "qns_lpass_aggnoc",
- .id = SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_MASTER_LPIAON_NOC },
+ .link_nodes = { &qnm_lpiaon_noc, NULL },
};
static struct qcom_icc_node qns_lpi_aon_noc = {
.name = "qns_lpi_aon_noc",
- .id = SM8750_SLAVE_LPICX_NOC_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_MASTER_LPASS_LPINOC },
+ .link_nodes = { &qnm_lpass_lpinoc, NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM8750_SLAVE_EBI1,
.channels = 4,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM8750_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SM8750_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM8750_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SM8750_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8750_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SM8750_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8750_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_pcie_aggre_noc = {
.name = "srvc_pcie_aggre_noc",
- .id = SM8750_SLAVE_SERVICE_PCIE_ANOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM8750_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8750_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1345,6 +1155,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
};
@@ -1367,6 +1178,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1389,6 +1201,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8750_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1438,6 +1251,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1467,6 +1281,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc sm8750_cnoc_main = {
+ .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
@@ -1500,6 +1315,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1512,6 +1328,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
};
@@ -1526,6 +1343,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
@@ -1538,6 +1356,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_lpass_lpicx_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
};
@@ -1553,6 +1372,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8750_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1582,6 +1402,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1598,6 +1419,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_nsp_noc = {
+ .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1616,6 +1438,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_pcie_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1635,6 +1458,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v2 28/28] interconnect: qcom: icc-rpmh: drop support for non-dynamic IDS
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (26 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 27/28] interconnect: qcom: sm8750: " Dmitry Baryshkov
@ 2025-07-04 16:35 ` Dmitry Baryshkov
2025-07-08 16:44 ` Konrad Dybcio
2025-07-16 15:22 ` [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
28 siblings, 1 reply; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-04 16:35 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson; +Cc: linux-arm-msm, linux-pm, linux-kernel
Now as all RPMh interconnect drivers were converted to using the dynamic
IDs, drop support for non-dynamic ID allocation.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/interconnect/qcom/icc-rpmh.c | 19 +++++--------------
drivers/interconnect/qcom/icc-rpmh.h | 7 -------
drivers/interconnect/qcom/qcs615.c | 9 ---------
drivers/interconnect/qcom/qcs8300.c | 13 -------------
drivers/interconnect/qcom/qdu1000.c | 4 ----
drivers/interconnect/qcom/sa8775p.c | 14 --------------
drivers/interconnect/qcom/sar2130p.c | 9 ---------
drivers/interconnect/qcom/sc7180.c | 12 ------------
drivers/interconnect/qcom/sc7280.c | 12 ------------
drivers/interconnect/qcom/sc8180x.c | 11 -----------
drivers/interconnect/qcom/sc8280xp.c | 12 ------------
drivers/interconnect/qcom/sdm670.c | 8 --------
drivers/interconnect/qcom/sdm845.c | 8 --------
drivers/interconnect/qcom/sdx55.c | 3 ---
drivers/interconnect/qcom/sdx65.c | 3 ---
drivers/interconnect/qcom/sdx75.c | 6 ------
drivers/interconnect/qcom/sm6350.c | 10 ----------
drivers/interconnect/qcom/sm7150.c | 10 ----------
drivers/interconnect/qcom/sm8150.c | 10 ----------
drivers/interconnect/qcom/sm8350.c | 10 ----------
drivers/interconnect/qcom/sm8450.c | 11 -----------
drivers/interconnect/qcom/sm8550.c | 14 --------------
drivers/interconnect/qcom/sm8650.c | 14 --------------
drivers/interconnect/qcom/sm8750.c | 14 --------------
drivers/interconnect/qcom/x1e80100.c | 19 -------------------
25 files changed, 5 insertions(+), 257 deletions(-)
diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
index 941692cbaf208c66a27dda2e6902b2f26f605840..796fba9fb316cf58ae2eb77af1607d6d00c38438 100644
--- a/drivers/interconnect/qcom/icc-rpmh.c
+++ b/drivers/interconnect/qcom/icc-rpmh.c
@@ -280,14 +280,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
if (!qn)
continue;
- if (desc->alloc_dyn_id) {
- if (!qn->node)
- qn->node = icc_node_create_dyn();
- node = qn->node;
- } else {
- node = icc_node_create(qn->id);
- }
+ if (!qn->node)
+ qn->node = icc_node_create_dyn();
+ node = qn->node;
if (IS_ERR(node)) {
ret = PTR_ERR(node);
goto err_remove_nodes;
@@ -302,13 +298,8 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
node->data = qn;
icc_node_add(node, provider);
- if (desc->alloc_dyn_id) {
- for (j = 0; qn->link_nodes[j]; j++)
- icc_link_nodes(node, &qn->link_nodes[j]->node);
- } else {
- for (j = 0; j < qn->num_links; j++)
- icc_link_create(node, qn->links[j]);
- }
+ for (j = 0; qn->link_nodes[j]; j++)
+ icc_link_nodes(node, &qn->link_nodes[j]->node);
data->nodes[i] = node;
}
diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
index 742941a296ac0a2e3d3e7147c25f750965a36647..5eb76da081df024e1f84069ce54f5da5fbb19699 100644
--- a/drivers/interconnect/qcom/icc-rpmh.h
+++ b/drivers/interconnect/qcom/icc-rpmh.h
@@ -81,10 +81,7 @@ struct qcom_icc_qosbox {
/**
* struct qcom_icc_node - Qualcomm specific interconnect nodes
* @name: the node name used in debugfs
- * @links: an array of nodes where we can go next while traversing
- * @id: a unique node identifier
* @node: icc_node associated with this node
- * @num_links: the total number of @links
* @channels: num of channels at this node
* @buswidth: width of the interconnect between a node and the bus
* @sum_avg: current sum aggregate value of all avg bw requests
@@ -96,10 +93,7 @@ struct qcom_icc_qosbox {
*/
struct qcom_icc_node {
const char *name;
- u16 links[MAX_LINKS];
- u16 id;
struct icc_node *node;
- u16 num_links;
u16 channels;
u16 buswidth;
u64 sum_avg[QCOM_ICC_NUM_BUCKETS];
@@ -156,7 +150,6 @@ struct qcom_icc_desc {
struct qcom_icc_bcm * const *bcms;
size_t num_bcms;
bool qos_requires_clocks;
- bool alloc_dyn_id;
};
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom/qcs615.c
index 4fc58de384e9dec2364d78e89630ef61d0338155..bb9c9c0b6fe5b0c402fd9b8cda3ee392839287cb 100644
--- a/drivers/interconnect/qcom/qcs615.c
+++ b/drivers/interconnect/qcom/qcs615.c
@@ -1194,7 +1194,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1213,7 +1212,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs615_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1272,7 +1270,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1286,7 +1283,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@@ -1316,7 +1312,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1333,7 +1328,6 @@ static struct qcom_icc_node * const ipa_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs615_ipa_virt = {
- .alloc_dyn_id = true,
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
@@ -1351,7 +1345,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs615_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1380,7 +1373,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1423,7 +1415,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs615_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qcom/qcs8300.c
index ebe9a2eab554bcb199497e4efbfbebeec3bb2c53..d490f8dc1d0120b46d474dae4f7cb9c603aba57f 100644
--- a/drivers/interconnect/qcom/qcs8300.c
+++ b/drivers/interconnect/qcom/qcs8300.c
@@ -1582,7 +1582,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1608,7 +1607,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1631,7 +1629,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1726,7 +1723,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1740,7 +1736,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@@ -1774,7 +1769,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1792,7 +1786,6 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_gpdsp_anoc = {
- .alloc_dyn_id = true,
.nodes = gpdsp_anoc_nodes,
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
.bcms = gpdsp_anoc_bcms,
@@ -1816,7 +1809,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1834,7 +1826,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1864,7 +1855,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1885,7 +1875,6 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_nspa_noc = {
- .alloc_dyn_id = true,
.nodes = nspa_noc_nodes,
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
@@ -1903,7 +1892,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1932,7 +1920,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc qcs8300_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c
index 6bd7b16f8129758eca38ed9d348ac745226897dd..0e2f3b19de405989ca60019e6aabc9352cc1c607 100644
--- a/drivers/interconnect/qcom/qdu1000.c
+++ b/drivers/interconnect/qcom/qdu1000.c
@@ -816,7 +816,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc qdu1000_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -844,7 +843,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc qdu1000_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -862,7 +860,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc qdu1000_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -949,7 +946,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc qdu1000_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
index a7049eb22d1e064afea17812637b720f907de90e..910116bc8b3a7a15f5906473af7018777b122afc 100644
--- a/drivers/interconnect/qcom/sa8775p.c
+++ b/drivers/interconnect/qcom/sa8775p.c
@@ -1820,7 +1820,6 @@ static const struct qcom_icc_desc sa8775p_aggre1_noc = {
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
@@ -1848,7 +1847,6 @@ static const struct qcom_icc_desc sa8775p_aggre2_noc = {
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
@@ -1873,7 +1871,6 @@ static const struct qcom_icc_desc sa8775p_clk_virt = {
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const config_noc_bcms[] = {
@@ -1979,7 +1976,6 @@ static const struct qcom_icc_desc sa8775p_config_noc = {
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
.num_bcms = ARRAY_SIZE(config_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
@@ -1996,7 +1992,6 @@ static const struct qcom_icc_desc sa8775p_dc_noc = {
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
@@ -2033,7 +2028,6 @@ static const struct qcom_icc_desc sa8775p_gem_noc = {
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
@@ -2052,7 +2046,6 @@ static const struct qcom_icc_desc sa8775p_gpdsp_anoc = {
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
.bcms = gpdsp_anoc_bcms,
.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
@@ -2076,7 +2069,6 @@ static const struct qcom_icc_desc sa8775p_lpass_ag_noc = {
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
@@ -2094,7 +2086,6 @@ static const struct qcom_icc_desc sa8775p_mc_virt = {
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
@@ -2127,7 +2118,6 @@ static const struct qcom_icc_desc sa8775p_mmss_noc = {
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
@@ -2148,7 +2138,6 @@ static const struct qcom_icc_desc sa8775p_nspa_noc = {
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
@@ -2169,7 +2158,6 @@ static const struct qcom_icc_desc sa8775p_nspb_noc = {
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
.bcms = nspb_noc_bcms,
.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
@@ -2187,7 +2175,6 @@ static const struct qcom_icc_desc sa8775p_pcie_anoc = {
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
@@ -2216,7 +2203,6 @@ static const struct qcom_icc_desc sa8775p_system_noc = {
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
- .alloc_dyn_id = true,
};
static const struct of_device_id qnoc_of_match[] = {
diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qcom/sar2130p.c
index df9bd10ffe0589f135a0c6199162b7f33233598f..cb978aae8c8cc1f333eaa91e7277e437fd788acd 100644
--- a/drivers/interconnect/qcom/sar2130p.c
+++ b/drivers/interconnect/qcom/sar2130p.c
@@ -1447,7 +1447,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1510,7 +1509,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_config_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
@@ -1541,7 +1539,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_gem_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
@@ -1565,7 +1562,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_lpass_ag_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
@@ -1584,7 +1580,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1613,7 +1608,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_mmss_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
@@ -1633,7 +1627,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_nsp_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
@@ -1652,7 +1645,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_pcie_anoc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
@@ -1692,7 +1684,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sar2130p_system_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c
index 2d9099e909bb9fbc9b82370e488d014391324637..9c2ae0056183918ccc2aa3f55be7febc6f254628 100644
--- a/drivers/interconnect/qcom/sc7180.c
+++ b/drivers/interconnect/qcom/sc7180.c
@@ -1449,7 +1449,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1473,7 +1472,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1492,7 +1490,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = {
};
static const struct qcom_icc_desc sc7180_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1512,7 +1509,6 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1581,7 +1577,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1595,7 +1590,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@@ -1624,7 +1618,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1642,7 +1635,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sc7180_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1670,7 +1662,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1692,7 +1683,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_npu_noc = {
- .alloc_dyn_id = true,
.nodes = npu_noc_nodes,
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
};
@@ -1709,7 +1699,6 @@ static struct qcom_icc_node * const qup_virt_nodes[] = {
};
static const struct qcom_icc_desc sc7180_qup_virt = {
- .alloc_dyn_id = true,
.nodes = qup_virt_nodes,
.num_nodes = ARRAY_SIZE(qup_virt_nodes),
.bcms = qup_virt_bcms,
@@ -1745,7 +1734,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7180_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c
index c39e79d82b482ae3e35b292fe1a2d4cfc911d969..1ca2e8f55d6fcb0bc8818848a929c25ffe102427 100644
--- a/drivers/interconnect/qcom/sc7280.c
+++ b/drivers/interconnect/qcom/sc7280.c
@@ -1585,7 +1585,6 @@ static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_aggre1_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
@@ -1618,7 +1617,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7280_aggre2_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
@@ -1640,7 +1638,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sc7280_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1711,7 +1708,6 @@ static const struct regmap_config sc7280_cnoc2_regmap_config = {
};
static const struct qcom_icc_desc sc7280_cnoc2 = {
- .alloc_dyn_id = true,
.config = &sc7280_cnoc2_regmap_config,
.nodes = cnoc2_nodes,
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
@@ -1753,7 +1749,6 @@ static const struct regmap_config sc7280_cnoc3_regmap_config = {
};
static const struct qcom_icc_desc sc7280_cnoc3 = {
- .alloc_dyn_id = true,
.config = &sc7280_cnoc3_regmap_config,
.nodes = cnoc3_nodes,
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
@@ -1779,7 +1774,6 @@ static const struct regmap_config sc7280_dc_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_dc_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_dc_noc_regmap_config,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
@@ -1825,7 +1819,6 @@ static const struct regmap_config sc7280_gem_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_gem_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_gem_noc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
@@ -1855,7 +1848,6 @@ static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
@@ -1882,7 +1874,6 @@ static const struct regmap_config sc7280_mc_virt_regmap_config = {
};
static const struct qcom_icc_desc sc7280_mc_virt = {
- .alloc_dyn_id = true,
.config = &sc7280_mc_virt_regmap_config,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
@@ -1919,7 +1910,6 @@ static const struct regmap_config sc7280_mmss_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_mmss_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_mmss_noc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
@@ -1948,7 +1938,6 @@ static const struct regmap_config sc7280_nsp_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_nsp_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_nsp_noc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
@@ -1983,7 +1972,6 @@ static const struct regmap_config sc7280_system_noc_regmap_config = {
};
static const struct qcom_icc_desc sc7280_system_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_system_noc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c
index e68bc35b691276375349585ac03b279e30568c68..5a04126994b4e8bb5501ffb313d96e7794d3e096 100644
--- a/drivers/interconnect/qcom/sc8180x.c
+++ b/drivers/interconnect/qcom/sc8180x.c
@@ -1761,7 +1761,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8180x_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1769,7 +1768,6 @@ static const struct qcom_icc_desc sc8180x_aggre1_noc = {
};
static const struct qcom_icc_desc sc8180x_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1777,7 +1775,6 @@ static const struct qcom_icc_desc sc8180x_aggre2_noc = {
};
static const struct qcom_icc_desc sc8180x_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1785,7 +1782,6 @@ static const struct qcom_icc_desc sc8180x_camnoc_virt = {
};
static const struct qcom_icc_desc sc8180x_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1793,7 +1789,6 @@ static const struct qcom_icc_desc sc8180x_compute_noc = {
};
static const struct qcom_icc_desc sc8180x_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1801,13 +1796,11 @@ static const struct qcom_icc_desc sc8180x_config_noc = {
};
static const struct qcom_icc_desc sc8180x_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
static const struct qcom_icc_desc sc8180x_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1815,7 +1808,6 @@ static const struct qcom_icc_desc sc8180x_gem_noc = {
};
static const struct qcom_icc_desc sc8180x_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1823,7 +1815,6 @@ static const struct qcom_icc_desc sc8180x_mc_virt = {
};
static const struct qcom_icc_desc sc8180x_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1831,7 +1822,6 @@ static const struct qcom_icc_desc sc8180x_mmss_noc = {
};
static const struct qcom_icc_desc sc8180x_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
@@ -1852,7 +1842,6 @@ static struct qcom_icc_node * const qup_virt_nodes[] = {
};
static const struct qcom_icc_desc sc8180x_qup_virt = {
- .alloc_dyn_id = true,
.nodes = qup_virt_nodes,
.num_nodes = ARRAY_SIZE(qup_virt_nodes),
.bcms = qup_virt_bcms,
diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c
index d9fd67ae6258d66ab3e78e06863a5a42da3ac131..2c0f760edee725f5cb0a9de8eb03308c0f98c854 100644
--- a/drivers/interconnect/qcom/sc8280xp.c
+++ b/drivers/interconnect/qcom/sc8280xp.c
@@ -1957,7 +1957,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1994,7 +1993,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -2017,7 +2015,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -2122,7 +2119,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -2139,7 +2135,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -2174,7 +2169,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -2198,7 +2192,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -2216,7 +2209,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -2248,7 +2240,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -2269,7 +2260,6 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_nspa_noc = {
- .alloc_dyn_id = true,
.nodes = nspa_noc_nodes,
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
@@ -2290,7 +2280,6 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_nspb_noc = {
- .alloc_dyn_id = true,
.nodes = nspb_noc_nodes,
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
.bcms = nspb_noc_bcms,
@@ -2320,7 +2309,6 @@ static struct qcom_icc_node * const system_noc_main_nodes[] = {
};
static const struct qcom_icc_desc sc8280xp_system_noc_main = {
- .alloc_dyn_id = true,
.nodes = system_noc_main_nodes,
.num_nodes = ARRAY_SIZE(system_noc_main_nodes),
.bcms = system_noc_main_bcms,
diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c
index d1aa6e3532821659d06373c4082cc6bd77e420ab..6bf641c95d85f0049cf3b69a1878b18d6921c255 100644
--- a/drivers/interconnect/qcom/sdm670.c
+++ b/drivers/interconnect/qcom/sdm670.c
@@ -1222,7 +1222,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1249,7 +1248,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1305,7 +1303,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1322,7 +1319,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1341,7 +1337,6 @@ static struct qcom_icc_node * const gladiator_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_gladiator_noc = {
- .alloc_dyn_id = true,
.nodes = gladiator_noc_nodes,
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
.bcms = gladiator_noc_bcms,
@@ -1377,7 +1372,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_mem_noc = {
- .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
@@ -1408,7 +1402,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1453,7 +1446,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm670_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c
index b37de30a9e8f309510818e2619aab2c451f50fe0..8d77e6d00fe03c7b13f932e6f7136336535eaa21 100644
--- a/drivers/interconnect/qcom/sdm845.c
+++ b/drivers/interconnect/qcom/sdm845.c
@@ -1464,7 +1464,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1494,7 +1493,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1556,7 +1554,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1573,7 +1570,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1592,7 +1588,6 @@ static struct qcom_icc_node * const gladiator_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_gladiator_noc = {
- .alloc_dyn_id = true,
.nodes = gladiator_noc_nodes,
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
.bcms = gladiator_noc_bcms,
@@ -1628,7 +1623,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_mem_noc = {
- .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
@@ -1663,7 +1657,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1710,7 +1703,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdm845_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c
index 5d85c1e6ec58d3949b30c143440bb6dd0779a605..350fbfbfcba5fae70d2f4e9ecf2d2f064d7adbd0 100644
--- a/drivers/interconnect/qcom/sdx55.c
+++ b/drivers/interconnect/qcom/sdx55.c
@@ -766,7 +766,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sdx55_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -789,7 +788,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx55_mem_noc = {
- .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
@@ -869,7 +867,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx55_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c
index 267eeeec0e655e13c9643c432139f4b94542d959..a8aaab3fc3eaacfc717f9cb2a98bc854e7721311 100644
--- a/drivers/interconnect/qcom/sdx65.c
+++ b/drivers/interconnect/qcom/sdx65.c
@@ -751,7 +751,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sdx65_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -774,7 +773,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx65_mem_noc = {
- .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
@@ -851,7 +849,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx65_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c
index bfd0ec87f68020ea1e832c405237d29054117f70..49d0a14512e9edf5bc5a9524dc70d24485b4389f 100644
--- a/drivers/interconnect/qcom/sdx75.c
+++ b/drivers/interconnect/qcom/sdx75.c
@@ -854,7 +854,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sdx75_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -870,7 +869,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx75_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@@ -897,7 +895,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx75_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -914,7 +911,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sdx75_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -934,7 +930,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sdx75_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1013,7 +1008,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sdx75_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c
index 92a33c307c960157bf537bc5fe28b0348fbb9918..b1df16edff9d71ab2b7284e1a97e6f15bcb1f887 100644
--- a/drivers/interconnect/qcom/sm6350.c
+++ b/drivers/interconnect/qcom/sm6350.c
@@ -1360,7 +1360,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1386,7 +1385,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1414,7 +1412,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm6350_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1434,7 +1431,6 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1495,7 +1491,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1512,7 +1507,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1544,7 +1538,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1572,7 +1565,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1597,7 +1589,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_npu_noc = {
- .alloc_dyn_id = true,
.nodes = npu_noc_nodes,
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
.bcms = npu_noc_bcms,
@@ -1634,7 +1625,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm6350_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom/sm7150.c
index 5e2b77f3e1d2245ded149add1548e603a1358295..9857c86f2e45a7e62307e9b6f74fbd6e2c95b6f2 100644
--- a/drivers/interconnect/qcom/sm7150.c
+++ b/drivers/interconnect/qcom/sm7150.c
@@ -1384,7 +1384,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1414,7 +1413,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1434,7 +1432,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm7150_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1452,7 +1449,6 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1518,7 +1514,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1535,7 +1530,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1567,7 +1561,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1585,7 +1578,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm7150_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1617,7 +1609,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1654,7 +1645,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm7150_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c
index a545e780cacd77b0e8834c879d62c1fc1b3a433d..75093a2704fed883b9ea1d2ece6b01e469d2658c 100644
--- a/drivers/interconnect/qcom/sm8150.c
+++ b/drivers/interconnect/qcom/sm8150.c
@@ -1494,7 +1494,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1530,7 +1529,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1549,7 +1547,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8150_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
@@ -1567,7 +1564,6 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
@@ -1636,7 +1632,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1653,7 +1648,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1689,7 +1683,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1707,7 +1700,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8150_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1738,7 +1730,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1780,7 +1771,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8150_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c
index d268bb68b18cd7e9b06bd060f905b4f22e565e5e..be5a1752b81388549143796f2b4d103a11034090 100644
--- a/drivers/interconnect/qcom/sm8350.c
+++ b/drivers/interconnect/qcom/sm8350.c
@@ -1484,7 +1484,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1516,7 +1515,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1596,7 +1594,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1613,7 +1610,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1650,7 +1646,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1671,7 +1666,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1689,7 +1683,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8350_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1720,7 +1713,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1740,7 +1732,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_compute_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1766,7 +1757,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8350_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c
index eb3c2bb5499da9aaa6cd84b14d3917ab5e119a5f..fdec76e242574d096f834b252ac8bf65f0050d5c 100644
--- a/drivers/interconnect/qcom/sm8450.c
+++ b/drivers/interconnect/qcom/sm8450.c
@@ -1442,7 +1442,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1470,7 +1469,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1493,7 +1491,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8450_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1563,7 +1560,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1599,7 +1595,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1622,7 +1617,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1644,7 +1638,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8450_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1680,7 +1673,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1699,7 +1691,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_nsp_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1719,7 +1710,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1748,7 +1738,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8450_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
index 8e3993c189685693d75e184bbaad5692bef6375c..4fad11c369dfce113a2aca65ac7ec694158efde1 100644
--- a/drivers/interconnect/qcom/sm8550.c
+++ b/drivers/interconnect/qcom/sm8550.c
@@ -1207,7 +1207,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1231,7 +1230,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1254,7 +1252,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8550_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1315,7 +1312,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1340,7 +1336,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc sm8550_cnoc_main = {
- .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
@@ -1371,7 +1366,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1387,7 +1381,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1404,7 +1397,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
@@ -1420,7 +1412,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
.bcms = lpass_lpicx_noc_bcms,
@@ -1438,7 +1429,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8550_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1467,7 +1457,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1484,7 +1473,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_nsp_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1504,7 +1492,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1528,7 +1515,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c
index 48b1f9c5e988bebc78f1a724f78664f49e7c1aaa..5282b8ac1658a7933ae5d528c2b88a72d67cbf8b 100644
--- a/drivers/interconnect/qcom/sm8650.c
+++ b/drivers/interconnect/qcom/sm8650.c
@@ -1567,7 +1567,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_aggre1_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
@@ -1590,7 +1589,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_aggre2_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
@@ -1614,7 +1612,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8650_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1676,7 +1673,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_config_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
@@ -1705,7 +1701,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc sm8650_cnoc_main = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
@@ -1739,7 +1734,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_gem_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
@@ -1753,7 +1747,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_ag_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
@@ -1769,7 +1762,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
@@ -1783,7 +1775,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
@@ -1800,7 +1791,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8650_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1829,7 +1819,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_mmss_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
@@ -1847,7 +1836,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_nsp_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
@@ -1868,7 +1856,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_pcie_anoc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
@@ -1890,7 +1877,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_system_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom/sm8750.c
index 0c9b39ea4f9ec970112f2a9117d16e70a6f41c93..e2605b68bb2c05c6d1170f9fc387c5a3f4c30335 100644
--- a/drivers/interconnect/qcom/sm8750.c
+++ b/drivers/interconnect/qcom/sm8750.c
@@ -1155,7 +1155,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
};
@@ -1178,7 +1177,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1201,7 +1199,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8750_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1251,7 +1248,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1281,7 +1277,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc sm8750_cnoc_main = {
- .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
@@ -1315,7 +1310,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1328,7 +1322,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
};
@@ -1343,7 +1336,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
@@ -1356,7 +1348,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_lpass_lpicx_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
};
@@ -1372,7 +1363,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8750_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1402,7 +1392,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1419,7 +1408,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_nsp_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1438,7 +1426,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1458,7 +1445,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8750_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
index 8f2a912f403a48826a9ee89df57933f746e4bed6..a4b18f1905dcfe5d7fb59d5a0044624921417f44 100644
--- a/drivers/interconnect/qcom/x1e80100.c
+++ b/drivers/interconnect/qcom/x1e80100.c
@@ -1424,7 +1424,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1447,7 +1446,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1470,7 +1468,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1534,7 +1531,6 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_cnoc_cfg = {
- .alloc_dyn_id = true,
.nodes = cnoc_cfg_nodes,
.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
.bcms = cnoc_cfg_bcms,
@@ -1565,7 +1561,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_cnoc_main = {
- .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
@@ -1596,7 +1591,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1612,7 +1606,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1629,7 +1622,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
@@ -1645,7 +1637,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
.bcms = lpass_lpicx_noc_bcms,
@@ -1663,7 +1654,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1692,7 +1682,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1709,7 +1698,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_nsp_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1727,7 +1715,6 @@ static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_center_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes),
.bcms = pcie_center_anoc_bcms,
@@ -1745,7 +1732,6 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_north_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes),
.bcms = pcie_north_anoc_bcms,
@@ -1765,7 +1751,6 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_south_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes),
.bcms = pcie_south_anoc_bcms,
@@ -1788,7 +1773,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
@@ -1805,7 +1789,6 @@ static struct qcom_icc_node * const usb_center_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_usb_center_anoc = {
- .alloc_dyn_id = true,
.nodes = usb_center_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_center_anoc_nodes),
.bcms = usb_center_anoc_bcms,
@@ -1822,7 +1805,6 @@ static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_usb_north_anoc = {
- .alloc_dyn_id = true,
.nodes = usb_north_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_north_anoc_nodes),
.bcms = usb_north_anoc_bcms,
@@ -1843,7 +1825,6 @@ static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
};
static const struct qcom_icc_desc x1e80100_usb_south_anoc = {
- .alloc_dyn_id = true,
.nodes = usb_south_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_south_anoc_nodes),
.bcms = usb_south_anoc_bcms,
--
2.39.5
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [PATCH v2 28/28] interconnect: qcom: icc-rpmh: drop support for non-dynamic IDS
2025-07-04 16:35 ` [PATCH v2 28/28] interconnect: qcom: icc-rpmh: drop support for non-dynamic IDS Dmitry Baryshkov
@ 2025-07-08 16:44 ` Konrad Dybcio
0 siblings, 0 replies; 38+ messages in thread
From: Konrad Dybcio @ 2025-07-08 16:44 UTC (permalink / raw)
To: Dmitry Baryshkov, Georgi Djakov, Bjorn Andersson
Cc: linux-arm-msm, linux-pm, linux-kernel
On 7/4/25 6:35 PM, Dmitry Baryshkov wrote:
> Now as all RPMh interconnect drivers were converted to using the dynamic
> IDs, drop support for non-dynamic ID allocation.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
[...]
> diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
> index 941692cbaf208c66a27dda2e6902b2f26f605840..796fba9fb316cf58ae2eb77af1607d6d00c38438 100644
> --- a/drivers/interconnect/qcom/icc-rpmh.c
> +++ b/drivers/interconnect/qcom/icc-rpmh.c
> @@ -280,14 +280,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
> if (!qn)
> continue;
>
> - if (desc->alloc_dyn_id) {
> - if (!qn->node)
> - qn->node = icc_node_create_dyn();
> - node = qn->node;
> - } else {
> - node = icc_node_create(qn->id);
> - }
> + if (!qn->node)
> + qn->node = icc_node_create_dyn();
>
> + node = qn->node;
we can drop the 'node' binding now, I think
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs
2025-07-04 16:35 [PATCH v2 00/28] interconnect: qcom: icc-rpmh: use NULL-terminated arrays and drop static IDs Dmitry Baryshkov
` (27 preceding siblings ...)
2025-07-04 16:35 ` [PATCH v2 28/28] interconnect: qcom: icc-rpmh: drop support for non-dynamic IDS Dmitry Baryshkov
@ 2025-07-16 15:22 ` Dmitry Baryshkov
28 siblings, 0 replies; 38+ messages in thread
From: Dmitry Baryshkov @ 2025-07-16 15:22 UTC (permalink / raw)
To: Georgi Djakov, Bjorn Andersson
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
On Fri, Jul 04, 2025 at 07:35:12PM +0300, Dmitry Baryshkov wrote:
> Qualcomm interconnect code has been using .num_foo fields together with
> the arrays embedded in the structure, which results in hard-to-notice
> mistakes if .num_foo gets omitted or incorrect.
>
> Rework RPMh interconnect code to use NULL-terminated arrays for the
> dynamic IDs case (as now all the arrays contain only pointers) and,
> while we are at it, rework all the drivers to use dynamic IDs and drop
> static IDs code.
>
> This series touches only RPMh interconnect drivers. Corresponding series
> for RPM drivers will follow up shortly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> Changes in v2:
> - Rebased on linux-next, dropping applied dependency
> - Link to v1: https://lore.kernel.org/r/20250616-rework-icc-v1-0-bc1326294d71@oss.qualcomm.com
>
Georgi, gracious ping.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 38+ messages in thread