* [PATCH v3 0/2] RISC-V: add support for restartable sequence @ 2022-03-02 2:30 Vincent Chen 2022-03-02 2:30 ` [PATCH v3 1/2] RISC-V: Add " Vincent Chen 2022-03-02 2:30 ` [PATCH v3 2/2] rseq/selftests: Add support for RISC-V Vincent Chen 0 siblings, 2 replies; 12+ messages in thread From: Vincent Chen @ 2022-03-02 2:30 UTC (permalink / raw) To: palmer, mathieu.desnoyers; +Cc: linux-riscv, paul.walmsley, Vincent Chen Add RSEQ, restartable sequence, support and related selftest to RISCV. The relevant RSEQ tests in kselftest require the binutils patch "RISC-V: Fix linker problems with TLS copy relocs" to avoid placing PREINIT_ARRAY and TLS variable of librseq.so at the same address. https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=3e7bd7f24146f162565edf878840449f36a8d974 A segmental fault will happen if binutils misses this patch. Changes since v2: 1. Move rseq_signal_deliver() after syscall restart handling. 2. Add rseq_offset_deref_addv() to support memory barrier tests. Vincent Chen (2): RISC-V: Add support for restartable sequence rseq/selftests: Add support for RISC-V arch/riscv/Kconfig | 1 + arch/riscv/kernel/entry.S | 4 + arch/riscv/kernel/signal.c | 2 + tools/testing/selftests/rseq/param_test.c | 23 + tools/testing/selftests/rseq/rseq-riscv.h | 676 ++++++++++++++++++++++ tools/testing/selftests/rseq/rseq.h | 2 + 6 files changed, 708 insertions(+) create mode 100644 tools/testing/selftests/rseq/rseq-riscv.h -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/2] RISC-V: Add support for restartable sequence 2022-03-02 2:30 [PATCH v3 0/2] RISC-V: add support for restartable sequence Vincent Chen @ 2022-03-02 2:30 ` Vincent Chen 2022-03-02 16:29 ` Mathieu Desnoyers 2022-03-02 2:30 ` [PATCH v3 2/2] rseq/selftests: Add support for RISC-V Vincent Chen 1 sibling, 1 reply; 12+ messages in thread From: Vincent Chen @ 2022-03-02 2:30 UTC (permalink / raw) To: palmer, mathieu.desnoyers; +Cc: linux-riscv, paul.walmsley, Vincent Chen Add calls to rseq_signal_deliver() and rseq_syscall() to introduce RSEQ support. 1. Call the rseq_signal_deliver() function to fixup on the pre-signal frame when a signal is delivered on top of a restartable sequence critical section. 2. Check that system calls are not invoked from within rseq critical sections by invoking rseq_signal() from ret_from_syscall(). With CONFIG_DEBUG_RSEQ, such behavior results in termination of the process with SIGSEGV. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/entry.S | 4 ++++ arch/riscv/kernel/signal.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 5adcbd9b5e88..67a671b099b6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -101,6 +101,7 @@ config RISCV select HAVE_FUNCTION_ARG_ACCESS_API select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS + select HAVE_RSEQ select IRQ_DOMAIN select IRQ_FORCED_THREADING select MODULES_USE_ELF_RELA if MODULES diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index ed29e9c8f660..56ada2a583fa 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -225,6 +225,10 @@ ret_from_syscall: * (If it was configured with SECCOMP_RET_ERRNO/TRACE) */ ret_from_syscall_rejected: +#ifdef CONFIG_DEBUG_RSEQ + move a0, sp + call rseq_syscall +#endif /* Trace syscalls, but only if requested by the user. */ REG_L t0, TASK_TI_FLAGS(tp) andi t0, t0, _TIF_SYSCALL_WORK diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index c2d5ecbe5526..16da3c3b53a1 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -258,6 +258,8 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) } } + rseq_signal_deliver(ksig, regs); + /* Set up the stack frame */ ret = setup_rt_frame(ksig, oldset, regs); -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] RISC-V: Add support for restartable sequence 2022-03-02 2:30 ` [PATCH v3 1/2] RISC-V: Add " Vincent Chen @ 2022-03-02 16:29 ` Mathieu Desnoyers 2022-03-03 3:32 ` Vincent Chen 0 siblings, 1 reply; 12+ messages in thread From: Mathieu Desnoyers @ 2022-03-02 16:29 UTC (permalink / raw) To: Vincent Chen; +Cc: Palmer Dabbelt, linux-riscv, Paul Walmsley, Peter Zijlstra ----- On Mar 1, 2022, at 9:30 PM, Vincent Chen vincent.chen@sifive.com wrote: > Add calls to rseq_signal_deliver() and rseq_syscall() to introduce RSEQ > support. > > 1. Call the rseq_signal_deliver() function to fixup on the pre-signal > frame when a signal is delivered on top of a restartable sequence > critical section. > > 2. Check that system calls are not invoked from within rseq critical > sections by invoking rseq_signal() from ret_from_syscall(). With > CONFIG_DEBUG_RSEQ, such behavior results in termination of the > process with SIGSEGV. > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Will it be picked by by riscv maintainers ? Thanks, Mathieu > --- > arch/riscv/Kconfig | 1 + > arch/riscv/kernel/entry.S | 4 ++++ > arch/riscv/kernel/signal.c | 2 ++ > 3 files changed, 7 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 5adcbd9b5e88..67a671b099b6 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -101,6 +101,7 @@ config RISCV > select HAVE_FUNCTION_ARG_ACCESS_API > select HAVE_STACKPROTECTOR > select HAVE_SYSCALL_TRACEPOINTS > + select HAVE_RSEQ > select IRQ_DOMAIN > select IRQ_FORCED_THREADING > select MODULES_USE_ELF_RELA if MODULES > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > index ed29e9c8f660..56ada2a583fa 100644 > --- a/arch/riscv/kernel/entry.S > +++ b/arch/riscv/kernel/entry.S > @@ -225,6 +225,10 @@ ret_from_syscall: > * (If it was configured with SECCOMP_RET_ERRNO/TRACE) > */ > ret_from_syscall_rejected: > +#ifdef CONFIG_DEBUG_RSEQ > + move a0, sp > + call rseq_syscall > +#endif > /* Trace syscalls, but only if requested by the user. */ > REG_L t0, TASK_TI_FLAGS(tp) > andi t0, t0, _TIF_SYSCALL_WORK > diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c > index c2d5ecbe5526..16da3c3b53a1 100644 > --- a/arch/riscv/kernel/signal.c > +++ b/arch/riscv/kernel/signal.c > @@ -258,6 +258,8 @@ static void handle_signal(struct ksignal *ksig, struct > pt_regs *regs) > } > } > > + rseq_signal_deliver(ksig, regs); > + > /* Set up the stack frame */ > ret = setup_rt_frame(ksig, oldset, regs); > > -- > 2.17.1 -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] RISC-V: Add support for restartable sequence 2022-03-02 16:29 ` Mathieu Desnoyers @ 2022-03-03 3:32 ` Vincent Chen 0 siblings, 0 replies; 12+ messages in thread From: Vincent Chen @ 2022-03-03 3:32 UTC (permalink / raw) To: Mathieu Desnoyers Cc: Palmer Dabbelt, linux-riscv, Paul Walmsley, Peter Zijlstra On Thu, Mar 3, 2022 at 12:29 AM Mathieu Desnoyers <mathieu.desnoyers@efficios.com> wrote: > > ----- On Mar 1, 2022, at 9:30 PM, Vincent Chen vincent.chen@sifive.com wrote: > > > Add calls to rseq_signal_deliver() and rseq_syscall() to introduce RSEQ > > support. > > > > 1. Call the rseq_signal_deliver() function to fixup on the pre-signal > > frame when a signal is delivered on top of a restartable sequence > > critical section. > > > > 2. Check that system calls are not invoked from within rseq critical > > sections by invoking rseq_signal() from ret_from_syscall(). With > > CONFIG_DEBUG_RSEQ, such behavior results in termination of the > > process with SIGSEGV. > > > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > > Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> > > Will it be picked by by riscv maintainers ? > Hi Mathieu, Thank you very much for reviewing it. Yes, I hope it can be picked up by riscv maintainers. Thanks, Vincent > Thanks, > > Mathieu > > > --- > > arch/riscv/Kconfig | 1 + > > arch/riscv/kernel/entry.S | 4 ++++ > > arch/riscv/kernel/signal.c | 2 ++ > > 3 files changed, 7 insertions(+) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 5adcbd9b5e88..67a671b099b6 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -101,6 +101,7 @@ config RISCV > > select HAVE_FUNCTION_ARG_ACCESS_API > > select HAVE_STACKPROTECTOR > > select HAVE_SYSCALL_TRACEPOINTS > > + select HAVE_RSEQ > > select IRQ_DOMAIN > > select IRQ_FORCED_THREADING > > select MODULES_USE_ELF_RELA if MODULES > > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > > index ed29e9c8f660..56ada2a583fa 100644 > > --- a/arch/riscv/kernel/entry.S > > +++ b/arch/riscv/kernel/entry.S > > @@ -225,6 +225,10 @@ ret_from_syscall: > > * (If it was configured with SECCOMP_RET_ERRNO/TRACE) > > */ > > ret_from_syscall_rejected: > > +#ifdef CONFIG_DEBUG_RSEQ > > + move a0, sp > > + call rseq_syscall > > +#endif > > /* Trace syscalls, but only if requested by the user. */ > > REG_L t0, TASK_TI_FLAGS(tp) > > andi t0, t0, _TIF_SYSCALL_WORK > > diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c > > index c2d5ecbe5526..16da3c3b53a1 100644 > > --- a/arch/riscv/kernel/signal.c > > +++ b/arch/riscv/kernel/signal.c > > @@ -258,6 +258,8 @@ static void handle_signal(struct ksignal *ksig, struct > > pt_regs *regs) > > } > > } > > > > + rseq_signal_deliver(ksig, regs); > > + > > /* Set up the stack frame */ > > ret = setup_rt_frame(ksig, oldset, regs); > > > > -- > > 2.17.1 > > -- > Mathieu Desnoyers > EfficiOS Inc. > http://www.efficios.com _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/2] rseq/selftests: Add support for RISC-V 2022-03-02 2:30 [PATCH v3 0/2] RISC-V: add support for restartable sequence Vincent Chen 2022-03-02 2:30 ` [PATCH v3 1/2] RISC-V: Add " Vincent Chen @ 2022-03-02 2:30 ` Vincent Chen 2022-03-02 16:38 ` Mathieu Desnoyers 2022-03-08 7:30 ` Eric Lin 1 sibling, 2 replies; 12+ messages in thread From: Vincent Chen @ 2022-03-02 2:30 UTC (permalink / raw) To: palmer, mathieu.desnoyers; +Cc: linux-riscv, paul.walmsley, Vincent Chen Add support for RISC-V in the rseq selftests, which covers both 64-bit and 32-bit ISA with little endian mode. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- tools/testing/selftests/rseq/param_test.c | 23 + tools/testing/selftests/rseq/rseq-riscv.h | 676 ++++++++++++++++++++++ tools/testing/selftests/rseq/rseq.h | 2 + 3 files changed, 701 insertions(+) create mode 100644 tools/testing/selftests/rseq/rseq-riscv.h diff --git a/tools/testing/selftests/rseq/param_test.c b/tools/testing/selftests/rseq/param_test.c index 699ad5f93c34..0a6b8eafd444 100644 --- a/tools/testing/selftests/rseq/param_test.c +++ b/tools/testing/selftests/rseq/param_test.c @@ -207,6 +207,29 @@ unsigned int yield_mod_cnt, nr_abort; "addiu " INJECT_ASM_REG ", -1\n\t" \ "bnez " INJECT_ASM_REG ", 222b\n\t" \ "333:\n\t" +#elif defined(__riscv) + +#define RSEQ_INJECT_INPUT \ + , [loop_cnt_1]"m"(loop_cnt[1]) \ + , [loop_cnt_2]"m"(loop_cnt[2]) \ + , [loop_cnt_3]"m"(loop_cnt[3]) \ + , [loop_cnt_4]"m"(loop_cnt[4]) \ + , [loop_cnt_5]"m"(loop_cnt[5]) \ + , [loop_cnt_6]"m"(loop_cnt[6]) + +#define INJECT_ASM_REG "t1" + +#define RSEQ_INJECT_CLOBBER \ + , INJECT_ASM_REG + +#define RSEQ_INJECT_ASM(n) \ + "lw " INJECT_ASM_REG ", %[loop_cnt_" #n "]\n\t" \ + "beqz " INJECT_ASM_REG ", 333f\n\t" \ + "222:\n\t" \ + "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \ + "bnez " INJECT_ASM_REG ", 222b\n\t" \ + "333:\n\t" + #else #error unsupported target diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h new file mode 100644 index 000000000000..845ec7d0f2ed --- /dev/null +++ b/tools/testing/selftests/rseq/rseq-riscv.h @@ -0,0 +1,676 @@ +/* SPDX-License-Identifier: LGPL-2.1 OR MIT */ +/* + * Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike + * other architecture, the ebreak instruction has no immediate field for + * distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG. + * "csrw mhartid, x0" can also satisfy the RSEQ requirement because it + * is an uncommon instruction and will raise an illegal instruction + * exception when executed in all modes. + */ + +#if __ORDER_LITTLE_ENDIAN__ == 1234 +#define RSEQ_SIG 0xf1401073 /* csrr mhartid, x0 */ +#else +#error "Currently, RSEQ only supports Little-Endian version" +#endif + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b) a +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b) b +#endif + +#define REG_L __REG_SEL("ld ", "lw ") +#define REG_S __REG_SEL("sd ", "sw ") + +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") +#define rseq_smp_mb() RISCV_FENCE(rw, rw) +#define rseq_smp_rmb() RISCV_FENCE(r, r) +#define rseq_smp_wmb() RISCV_FENCE(w, w) +#define RSEQ_ASM_TMP_REG_1 "t6" +#define RSEQ_ASM_TMP_REG_2 "t5" +#define RSEQ_ASM_TMP_REG_3 "t4" +#define RSEQ_ASM_TMP_REG_4 "t3" + +#define rseq_smp_load_acquire(p) \ +__extension__ ({ \ + __typeof(*(p)) ____p1 = RSEQ_READ_ONCE(*(p)); \ + RISCV_FENCE(r, rw) \ + ____p1; \ +}) + +#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb() + +#define rseq_smp_store_release(p, v) \ +do { \ + RISCV_FENCE(rw, w); \ + RSEQ_WRITE_ONCE(*(p), v); \ +} while (0) + +#ifdef RSEQ_SKIP_FASTPATH +#include "rseq-skip.h" +#else /* !RSEQ_SKIP_FASTPATH */ + +#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \ + post_commit_offset, abort_ip) \ + ".pushsection __rseq_cs, \"aw\"\n" \ + ".balign 32\n" \ + __rseq_str(label) ":\n" \ + ".long " __rseq_str(version) ", " __rseq_str(flags) "\n" \ + ".quad " __rseq_str(start_ip) ", " \ + __rseq_str(post_commit_offset) ", " \ + __rseq_str(abort_ip) "\n" \ + ".popsection\n\t" \ + ".pushsection __rseq_cs_ptr_array, \"aw\"\n" \ + ".quad " __rseq_str(label) "b\n" \ + ".popsection\n" + +#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \ + __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \ + ((post_commit_ip) - (start_ip)), abort_ip) + +/* + * Exit points of a rseq critical section consist of all instructions outside + * of the critical section where a critical section can either branch to or + * reach through the normal course of its execution. The abort IP and the + * post-commit IP are already part of the __rseq_cs section and should not be + * explicitly defined as additional exit points. Knowing all exit points is + * useful to assist debuggers stepping over the critical section. + */ +#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \ + ".pushsection __rseq_exit_point_array, \"aw\"\n" \ + ".quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n" \ + ".popsection\n" + +#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \ + RSEQ_INJECT_ASM(1) \ + "la "RSEQ_ASM_TMP_REG_1 ", " __rseq_str(cs_label) "\n" \ + REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(rseq_cs) "]\n" \ + __rseq_str(label) ":\n" + +#define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \ + "j 222f\n" \ + ".balign 4\n" \ + ".long " __rseq_str(RSEQ_SIG) "\n" \ + __rseq_str(label) ":\n" \ + "j %l[" __rseq_str(abort_label) "]\n" \ + "222:\n" + +#define RSEQ_ASM_OP_STORE(value, var) \ + REG_S "%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_CMPEQ(var, expect, label) \ + REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ + "bne "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ + __rseq_str(label) "\n" + +#define RSEQ_ASM_OP_CMPEQ32(var, expect, label) \ + "lw "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ + "bne "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ + __rseq_str(label) "\n" + +#define RSEQ_ASM_OP_CMPNE(var, expect, label) \ + REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ + "beq "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ + __rseq_str(label) "\n" + +#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \ + RSEQ_INJECT_ASM(2) \ + RSEQ_ASM_OP_CMPEQ32(current_cpu_id, cpu_id, label) + +#define RSEQ_ASM_OP_R_LOAD(var) \ + REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_R_STORE(var) \ + REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \ + "add "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(offset) "], " \ + RSEQ_ASM_TMP_REG_1 "\n" \ + REG_L RSEQ_ASM_TMP_REG_1 ", (" RSEQ_ASM_TMP_REG_1 ")\n" + +#define RSEQ_ASM_OP_R_ADD(count) \ + "add "RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 \ + ", %[" __rseq_str(count) "]\n" + +#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \ + RSEQ_ASM_OP_STORE(value, var) \ + __rseq_str(post_commit_label) ":\n" + +#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \ + "fence rw, w\n" \ + RSEQ_ASM_OP_STORE(value, var) \ + __rseq_str(post_commit_label) ":\n" + +#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \ + REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ + __rseq_str(post_commit_label) ":\n" + +#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \ + "beqz %[" __rseq_str(len) "], 333f\n" \ + "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(len) "]\n" \ + "mv " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(src) "]\n" \ + "mv " RSEQ_ASM_TMP_REG_3 ", %[" __rseq_str(dst) "]\n" \ + "222:\n" \ + "lb " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_2 ")\n" \ + "sb " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_3 ")\n" \ + "addi " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 ", -1\n" \ + "addi " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", 1\n" \ + "addi " RSEQ_ASM_TMP_REG_3 ", " RSEQ_ASM_TMP_REG_3 ", 1\n" \ + "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \ + "333:\n" + +#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label) \ + "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \ + RSEQ_ASM_OP_R_ADD(off) \ + "ld " RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \ + RSEQ_ASM_OP_R_ADD(inc) \ + __rseq_str(post_commit_label) ":\n" + +static inline __always_inline +int rseq_cmpeqv_storev(intptr_t *v, intptr_t expect, intptr_t newv, int cpu) +{ + RSEQ_INJECT_C(9) + + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") + RSEQ_INJECT_ASM(4) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") +#endif + RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) + RSEQ_INJECT_ASM(5) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [v] "m" (*v), + [expect] "r" (expect), + [newv] "r" (newv) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1 + RSEQ_INJECT_CLOBBER + : abort, cmpfail +#ifdef RSEQ_COMPARE_TWICE + , error1, error2 +#endif + ); + + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +cmpfail: + return 1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +error2: + rseq_bug("expected value comparison failed"); +#endif +} + +static inline __always_inline +int rseq_cmpnev_storeoffp_load(intptr_t *v, intptr_t expectnot, + off_t voffp, intptr_t *load, int cpu) +{ + RSEQ_INJECT_C(9) + + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) + RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[cmpfail]") + RSEQ_INJECT_ASM(4) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") + RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[error2]") +#endif + RSEQ_ASM_OP_R_LOAD(v) + RSEQ_ASM_OP_R_STORE(load) + RSEQ_ASM_OP_R_LOAD_OFF(voffp) + RSEQ_ASM_OP_R_FINAL_STORE(v, 3) + RSEQ_INJECT_ASM(5) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [v] "m" (*v), + [expectnot] "r" (expectnot), + [load] "m" (*load), + [voffp] "r" (voffp) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1 + RSEQ_INJECT_CLOBBER + : abort, cmpfail +#ifdef RSEQ_COMPARE_TWICE + , error1, error2 +#endif + ); + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +cmpfail: + return 1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +error2: + rseq_bug("expected value comparison failed"); +#endif +} + +static inline __always_inline +int rseq_addv(intptr_t *v, intptr_t count, int cpu) +{ + RSEQ_INJECT_C(9) + + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") +#endif + RSEQ_ASM_OP_R_LOAD(v) + RSEQ_ASM_OP_R_ADD(count) + RSEQ_ASM_OP_R_FINAL_STORE(v, 3) + RSEQ_INJECT_ASM(4) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [v] "m" (*v), + [count] "r" (count) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1 + RSEQ_INJECT_CLOBBER + : abort +#ifdef RSEQ_COMPARE_TWICE + , error1 +#endif + ); + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +#endif +} + +static inline __always_inline +int rseq_cmpeqv_trystorev_storev(intptr_t *v, intptr_t expect, + intptr_t *v2, intptr_t newv2, + intptr_t newv, int cpu) +{ + RSEQ_INJECT_C(9) + + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") + RSEQ_INJECT_ASM(4) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") +#endif + RSEQ_ASM_OP_STORE(newv2, v2) + RSEQ_INJECT_ASM(5) + RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) + RSEQ_INJECT_ASM(6) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [expect] "r" (expect), + [v] "m" (*v), + [newv] "r" (newv), + [v2] "m" (*v2), + [newv2] "r" (newv2) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1 + RSEQ_INJECT_CLOBBER + : abort, cmpfail +#ifdef RSEQ_COMPARE_TWICE + , error1, error2 +#endif + ); + + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +cmpfail: + return 1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +error2: + rseq_bug("expected value comparison failed"); +#endif +} + +static inline __always_inline +int rseq_cmpeqv_trystorev_storev_release(intptr_t *v, intptr_t expect, + intptr_t *v2, intptr_t newv2, + intptr_t newv, int cpu) +{ + RSEQ_INJECT_C(9) + + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") + RSEQ_INJECT_ASM(4) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") +#endif + RSEQ_ASM_OP_STORE(newv2, v2) + RSEQ_INJECT_ASM(5) + RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3) + RSEQ_INJECT_ASM(6) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [expect] "r" (expect), + [v] "m" (*v), + [newv] "r" (newv), + [v2] "m" (*v2), + [newv2] "r" (newv2) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1 + RSEQ_INJECT_CLOBBER + : abort, cmpfail +#ifdef RSEQ_COMPARE_TWICE + , error1, error2 +#endif + ); + + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +cmpfail: + return 1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +error2: + rseq_bug("expected value comparison failed"); +#endif +} + +static inline __always_inline +int rseq_cmpeqv_cmpeqv_storev(intptr_t *v, intptr_t expect, + intptr_t *v2, intptr_t expect2, + intptr_t newv, int cpu) +{ + RSEQ_INJECT_C(9) + + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error3]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") + RSEQ_INJECT_ASM(4) + RSEQ_ASM_OP_CMPEQ(v2, expect2, "%l[cmpfail]") + RSEQ_INJECT_ASM(5) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") + RSEQ_ASM_OP_CMPEQ(v2, expect2, "%l[error3]") +#endif + RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) + RSEQ_INJECT_ASM(6) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [v] "m" (*v), + [expect] "r" (expect), + [v2] "m" (*v2), + [expect2] "r" (expect2), + [newv] "r" (newv) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1 + RSEQ_INJECT_CLOBBER + : abort, cmpfail +#ifdef RSEQ_COMPARE_TWICE + , error1, error2, error3 +#endif + ); + + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +cmpfail: + return 1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +error2: + rseq_bug("expected value comparison failed"); +error3: + rseq_bug("2nd expected value comparison failed"); +#endif +} + +static inline __always_inline +int rseq_cmpeqv_trymemcpy_storev(intptr_t *v, intptr_t expect, + void *dst, void *src, size_t len, + intptr_t newv, int cpu) +{ + RSEQ_INJECT_C(9) + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") + RSEQ_INJECT_ASM(4) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") +#endif + RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) + RSEQ_INJECT_ASM(5) + RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) + RSEQ_INJECT_ASM(6) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [expect] "r" (expect), + [v] "m" (*v), + [newv] "r" (newv), + [dst] "r" (dst), + [src] "r" (src), + [len] "r" (len) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1, RSEQ_ASM_TMP_REG_2, + RSEQ_ASM_TMP_REG_3, RSEQ_ASM_TMP_REG_4 + RSEQ_INJECT_CLOBBER + : abort, cmpfail +#ifdef RSEQ_COMPARE_TWICE + , error1, error2 +#endif + ); + + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +cmpfail: + return 1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +error2: + rseq_bug("expected value comparison failed"); +#endif +} + +static inline __always_inline +int rseq_cmpeqv_trymemcpy_storev_release(intptr_t *v, intptr_t expect, + void *dst, void *src, size_t len, + intptr_t newv, int cpu) +{ + RSEQ_INJECT_C(9) + + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") + RSEQ_INJECT_ASM(4) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") +#endif + RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) + RSEQ_INJECT_ASM(5) + RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3) + RSEQ_INJECT_ASM(6) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [expect] "r" (expect), + [v] "m" (*v), + [newv] "r" (newv), + [dst] "r" (dst), + [src] "r" (src), + [len] "r" (len) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1, RSEQ_ASM_TMP_REG_2, + RSEQ_ASM_TMP_REG_3, RSEQ_ASM_TMP_REG_4 + RSEQ_INJECT_CLOBBER + : abort, cmpfail +#ifdef RSEQ_COMPARE_TWICE + , error1, error2 +#endif + ); + + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +cmpfail: + return 1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +error2: + rseq_bug("expected value comparison failed"); +#endif +} + +#define RSEQ_ARCH_HAS_OFFSET_DEREF_ADDV + +/* + * pval = *(ptr+off) + * *pval += inc; + */ +static inline __always_inline +int rseq_offset_deref_addv(intptr_t *ptr, off_t off, intptr_t inc, int cpu) +{ + RSEQ_INJECT_C(9) + + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") +#endif + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) + RSEQ_INJECT_ASM(3) +#ifdef RSEQ_COMPARE_TWICE + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") +#endif + RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3) + RSEQ_INJECT_ASM(4) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [cpu_id] "r" (cpu), + [current_cpu_id] "m" (__rseq_abi.cpu_id), + [rseq_cs] "m" (__rseq_abi.rseq_cs), + [ptr] "r" (ptr), + [off] "er" (off), + [inc] "er" (inc) + RSEQ_INJECT_INPUT + : "memory", RSEQ_ASM_TMP_REG_1 + RSEQ_INJECT_CLOBBER + : abort +#ifdef RSEQ_COMPARE_TWICE + , error1 +#endif + ); + return 0; +abort: + RSEQ_INJECT_FAILED + return -1; +#ifdef RSEQ_COMPARE_TWICE +error1: + rseq_bug("cpu_id comparison failed"); +#endif +} + +#endif /* !RSEQ_SKIP_FASTPATH */ diff --git a/tools/testing/selftests/rseq/rseq.h b/tools/testing/selftests/rseq/rseq.h index 3f63eb362b92..72efb6d3d84e 100644 --- a/tools/testing/selftests/rseq/rseq.h +++ b/tools/testing/selftests/rseq/rseq.h @@ -79,6 +79,8 @@ extern int __rseq_handled; #include <rseq-mips.h> #elif defined(__s390__) #include <rseq-s390.h> +#elif defined(__riscv) +#include <rseq-riscv.h> #else #error unsupported target #endif -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] rseq/selftests: Add support for RISC-V 2022-03-02 2:30 ` [PATCH v3 2/2] rseq/selftests: Add support for RISC-V Vincent Chen @ 2022-03-02 16:38 ` Mathieu Desnoyers 2022-03-03 7:16 ` Vincent Chen 2022-03-08 7:30 ` Eric Lin 1 sibling, 1 reply; 12+ messages in thread From: Mathieu Desnoyers @ 2022-03-02 16:38 UTC (permalink / raw) To: Vincent Chen, Peter Zijlstra; +Cc: Palmer Dabbelt, linux-riscv, Paul Walmsley ----- On Mar 1, 2022, at 9:30 PM, Vincent Chen vincent.chen@sifive.com wrote: > Add support for RISC-V in the rseq selftests, which covers both > 64-bit and 32-bit ISA with little endian mode. > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> If you also ran those tests on riscv, can you state so with a "Tested-by" ? Small nits below, > --- > tools/testing/selftests/rseq/param_test.c | 23 + > tools/testing/selftests/rseq/rseq-riscv.h | 676 ++++++++++++++++++++++ > tools/testing/selftests/rseq/rseq.h | 2 + > 3 files changed, 701 insertions(+) > create mode 100644 tools/testing/selftests/rseq/rseq-riscv.h > > diff --git a/tools/testing/selftests/rseq/param_test.c > b/tools/testing/selftests/rseq/param_test.c > index 699ad5f93c34..0a6b8eafd444 100644 > --- a/tools/testing/selftests/rseq/param_test.c > +++ b/tools/testing/selftests/rseq/param_test.c > @@ -207,6 +207,29 @@ unsigned int yield_mod_cnt, nr_abort; > "addiu " INJECT_ASM_REG ", -1\n\t" \ > "bnez " INJECT_ASM_REG ", 222b\n\t" \ > "333:\n\t" > +#elif defined(__riscv) > + > +#define RSEQ_INJECT_INPUT \ > + , [loop_cnt_1]"m"(loop_cnt[1]) \ > + , [loop_cnt_2]"m"(loop_cnt[2]) \ > + , [loop_cnt_3]"m"(loop_cnt[3]) \ > + , [loop_cnt_4]"m"(loop_cnt[4]) \ > + , [loop_cnt_5]"m"(loop_cnt[5]) \ > + , [loop_cnt_6]"m"(loop_cnt[6]) > + > +#define INJECT_ASM_REG "t1" > + > +#define RSEQ_INJECT_CLOBBER \ > + , INJECT_ASM_REG > + > +#define RSEQ_INJECT_ASM(n) \ > + "lw " INJECT_ASM_REG ", %[loop_cnt_" #n "]\n\t" \ > + "beqz " INJECT_ASM_REG ", 333f\n\t" \ > + "222:\n\t" \ > + "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \ > + "bnez " INJECT_ASM_REG ", 222b\n\t" \ > + "333:\n\t" > + > > #else > #error unsupported target > diff --git a/tools/testing/selftests/rseq/rseq-riscv.h > b/tools/testing/selftests/rseq/rseq-riscv.h > new file mode 100644 > index 000000000000..845ec7d0f2ed > --- /dev/null > +++ b/tools/testing/selftests/rseq/rseq-riscv.h > @@ -0,0 +1,676 @@ > +/* SPDX-License-Identifier: LGPL-2.1 OR MIT */ > +/* > + * Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike > + * other architecture, the ebreak instruction has no immediate field for architecture -> architectures > + * distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG. > + * "csrw mhartid, x0" can also satisfy the RSEQ requirement because it > + * is an uncommon instruction and will raise an illegal instruction > + * exception when executed in all modes. > + */ > + > +#if __ORDER_LITTLE_ENDIAN__ == 1234 I think we'll want to standardize on this for endianness checking (same as the updated uapi rseq.h): #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : defined(__LITTLE_ENDIAN) We may have to change rseq-mips.h in the rseq selftests to do the same as well rather than using "# ifdef __BIG_ENDIAN". > +#define RSEQ_SIG 0xf1401073 /* csrr mhartid, x0 */ > +#else > +#error "Currently, RSEQ only supports Little-Endian version" > +#endif > + [...] Thanks, Mathieu -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] rseq/selftests: Add support for RISC-V 2022-03-02 16:38 ` Mathieu Desnoyers @ 2022-03-03 7:16 ` Vincent Chen 2022-03-03 21:50 ` Mathieu Desnoyers 0 siblings, 1 reply; 12+ messages in thread From: Vincent Chen @ 2022-03-03 7:16 UTC (permalink / raw) To: Mathieu Desnoyers Cc: Peter Zijlstra, Palmer Dabbelt, linux-riscv, Paul Walmsley On Thu, Mar 3, 2022 at 12:38 AM Mathieu Desnoyers <mathieu.desnoyers@efficios.com> wrote: > > ----- On Mar 1, 2022, at 9:30 PM, Vincent Chen vincent.chen@sifive.com wrote: > > > Add support for RISC-V in the rseq selftests, which covers both > > 64-bit and 32-bit ISA with little endian mode. > > > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > > If you also ran those tests on riscv, can you state so with a "Tested-by" ? > Yes, I ran all the tests under the selftests/rseq folder. Maybe I can ask my colleagues to give it a test as well and give me a "Tested-by". > Small nits below, > > > --- > > tools/testing/selftests/rseq/param_test.c | 23 + > > tools/testing/selftests/rseq/rseq-riscv.h | 676 ++++++++++++++++++++++ > > tools/testing/selftests/rseq/rseq.h | 2 + > > 3 files changed, 701 insertions(+) > > create mode 100644 tools/testing/selftests/rseq/rseq-riscv.h > > > > diff --git a/tools/testing/selftests/rseq/param_test.c > > b/tools/testing/selftests/rseq/param_test.c > > index 699ad5f93c34..0a6b8eafd444 100644 > > --- a/tools/testing/selftests/rseq/param_test.c > > +++ b/tools/testing/selftests/rseq/param_test.c > > @@ -207,6 +207,29 @@ unsigned int yield_mod_cnt, nr_abort; > > "addiu " INJECT_ASM_REG ", -1\n\t" \ > > "bnez " INJECT_ASM_REG ", 222b\n\t" \ > > "333:\n\t" > > +#elif defined(__riscv) > > + > > +#define RSEQ_INJECT_INPUT \ > > + , [loop_cnt_1]"m"(loop_cnt[1]) \ > > + , [loop_cnt_2]"m"(loop_cnt[2]) \ > > + , [loop_cnt_3]"m"(loop_cnt[3]) \ > > + , [loop_cnt_4]"m"(loop_cnt[4]) \ > > + , [loop_cnt_5]"m"(loop_cnt[5]) \ > > + , [loop_cnt_6]"m"(loop_cnt[6]) > > + > > +#define INJECT_ASM_REG "t1" > > + > > +#define RSEQ_INJECT_CLOBBER \ > > + , INJECT_ASM_REG > > + > > +#define RSEQ_INJECT_ASM(n) \ > > + "lw " INJECT_ASM_REG ", %[loop_cnt_" #n "]\n\t" \ > > + "beqz " INJECT_ASM_REG ", 333f\n\t" \ > > + "222:\n\t" \ > > + "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \ > > + "bnez " INJECT_ASM_REG ", 222b\n\t" \ > > + "333:\n\t" > > + > > > > #else > > #error unsupported target > > diff --git a/tools/testing/selftests/rseq/rseq-riscv.h > > b/tools/testing/selftests/rseq/rseq-riscv.h > > new file mode 100644 > > index 000000000000..845ec7d0f2ed > > --- /dev/null > > +++ b/tools/testing/selftests/rseq/rseq-riscv.h > > @@ -0,0 +1,676 @@ > > +/* SPDX-License-Identifier: LGPL-2.1 OR MIT */ > > +/* > > + * Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike > > + * other architecture, the ebreak instruction has no immediate field for > > architecture -> architectures Thanks. I will correct it in my next version patch. > > > + * distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG. > > + * "csrw mhartid, x0" can also satisfy the RSEQ requirement because it > > + * is an uncommon instruction and will raise an illegal instruction > > + * exception when executed in all modes. > > + */ > > + > > +#if __ORDER_LITTLE_ENDIAN__ == 1234 > > I think we'll want to standardize on this for endianness checking (same as > the updated uapi rseq.h): > > #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : defined(__LITTLE_ENDIAN) > > We may have to change rseq-mips.h in the rseq selftests to do the same as well rather than > using "# ifdef __BIG_ENDIAN". > OK, I can follow it. However, I found the endianness checking in include/uapi/linux/rseq.h is #if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || defined(__BIG_ENDIAN) It is a little different than what you mentioned early. Should I follow the format in include/uapi/linux/rseq.h? or both formats are OK? Thanks, Vincent > > +#define RSEQ_SIG 0xf1401073 /* csrr mhartid, x0 */ > > +#else > > +#error "Currently, RSEQ only supports Little-Endian version" > > +#endif > > + > > [...] > > Thanks, > > Mathieu > > > -- > Mathieu Desnoyers > EfficiOS Inc. > http://www.efficios.com _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] rseq/selftests: Add support for RISC-V 2022-03-03 7:16 ` Vincent Chen @ 2022-03-03 21:50 ` Mathieu Desnoyers 2022-03-04 6:50 ` Vincent Chen 0 siblings, 1 reply; 12+ messages in thread From: Mathieu Desnoyers @ 2022-03-03 21:50 UTC (permalink / raw) To: Vincent Chen; +Cc: Peter Zijlstra, Palmer Dabbelt, linux-riscv, Paul Walmsley ----- On Mar 3, 2022, at 2:16 AM, Vincent Chen vincent.chen@sifive.com wrote: > On Thu, Mar 3, 2022 at 12:38 AM Mathieu Desnoyers > <mathieu.desnoyers@efficios.com> wrote: >> [...] >> > +#if __ORDER_LITTLE_ENDIAN__ == 1234 >> >> I think we'll want to standardize on this for endianness checking (same as >> the updated uapi rseq.h): >> >> #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : >> defined(__LITTLE_ENDIAN) >> >> We may have to change rseq-mips.h in the rseq selftests to do the same as well >> rather than >> using "# ifdef __BIG_ENDIAN". >> > > OK, I can follow it. However, I found the endianness checking in > include/uapi/linux/rseq.h is > #if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || > defined(__BIG_ENDIAN) > > It is a little different than what you mentioned early. Should I > follow the format in include/uapi/linux/rseq.h? or both formats are > OK? > The form "#if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || defined(__BIG_ENDIAN) is completely buggy. Don't use that. I've sent the fix to Peter to remove the offending #if here: https://lore.kernel.org/lkml/1445357149.71067.1643137248305.JavaMail.zimbra@efficios.com/T/#mbbad3961494feefb98cb6d092879e3ea41b33df8 Please use the correct non-bogus form instead: #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : defined(__LITTLE_ENDIAN) Thanks, Mathieu -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] rseq/selftests: Add support for RISC-V 2022-03-03 21:50 ` Mathieu Desnoyers @ 2022-03-04 6:50 ` Vincent Chen 2022-03-07 2:45 ` Vincent Chen 0 siblings, 1 reply; 12+ messages in thread From: Vincent Chen @ 2022-03-04 6:50 UTC (permalink / raw) To: Mathieu Desnoyers Cc: Peter Zijlstra, Palmer Dabbelt, linux-riscv, Paul Walmsley On Fri, Mar 4, 2022 at 5:50 AM Mathieu Desnoyers <mathieu.desnoyers@efficios.com> wrote: > > ----- On Mar 3, 2022, at 2:16 AM, Vincent Chen vincent.chen@sifive.com wrote: > > > On Thu, Mar 3, 2022 at 12:38 AM Mathieu Desnoyers > > <mathieu.desnoyers@efficios.com> wrote: > >> > [...] > > >> > +#if __ORDER_LITTLE_ENDIAN__ == 1234 > >> > >> I think we'll want to standardize on this for endianness checking (same as > >> the updated uapi rseq.h): > >> > >> #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : > >> defined(__LITTLE_ENDIAN) > >> > >> We may have to change rseq-mips.h in the rseq selftests to do the same as well > >> rather than > >> using "# ifdef __BIG_ENDIAN". > >> > > > > OK, I can follow it. However, I found the endianness checking in > > include/uapi/linux/rseq.h is > > #if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || > > defined(__BIG_ENDIAN) > > > > It is a little different than what you mentioned early. Should I > > follow the format in include/uapi/linux/rseq.h? or both formats are > > OK? > > > > The form "#if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || defined(__BIG_ENDIAN) > is completely buggy. Don't use that. > > I've sent the fix to Peter to remove the offending #if here: > > https://lore.kernel.org/lkml/1445357149.71067.1643137248305.JavaMail.zimbra@efficios.com/T/#mbbad3961494feefb98cb6d092879e3ea41b33df8 > > Please use the correct non-bogus form instead: > > #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : defined(__LITTLE_ENDIAN) > > Thanks, > > Mathieu > I understood. By the way, IIUC, the __BYTE_ORDER and __LITTLE_ENDIAN are defined in the glibc endian.h. However, I find that no file in the rseq folder includes the endian.h. Does it means I should include <endian.h> in the rseq-riscv.h? Thanks, Vincent > > -- > Mathieu Desnoyers > EfficiOS Inc. > http://www.efficios.com _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] rseq/selftests: Add support for RISC-V 2022-03-04 6:50 ` Vincent Chen @ 2022-03-07 2:45 ` Vincent Chen 2022-03-07 13:40 ` Mathieu Desnoyers 0 siblings, 1 reply; 12+ messages in thread From: Vincent Chen @ 2022-03-07 2:45 UTC (permalink / raw) To: Mathieu Desnoyers Cc: Peter Zijlstra, Palmer Dabbelt, linux-riscv, Paul Walmsley On Fri, Mar 4, 2022 at 2:50 PM Vincent Chen <vincent.chen@sifive.com> wrote: > > On Fri, Mar 4, 2022 at 5:50 AM Mathieu Desnoyers > <mathieu.desnoyers@efficios.com> wrote: > > > > ----- On Mar 3, 2022, at 2:16 AM, Vincent Chen vincent.chen@sifive.com wrote: > > > > > On Thu, Mar 3, 2022 at 12:38 AM Mathieu Desnoyers > > > <mathieu.desnoyers@efficios.com> wrote: > > >> > > [...] > > > > >> > +#if __ORDER_LITTLE_ENDIAN__ == 1234 > > >> > > >> I think we'll want to standardize on this for endianness checking (same as > > >> the updated uapi rseq.h): > > >> > > >> #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : > > >> defined(__LITTLE_ENDIAN) > > >> > > >> We may have to change rseq-mips.h in the rseq selftests to do the same as well > > >> rather than > > >> using "# ifdef __BIG_ENDIAN". > > >> > > > > > > OK, I can follow it. However, I found the endianness checking in > > > include/uapi/linux/rseq.h is > > > #if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || > > > defined(__BIG_ENDIAN) > > > > > > It is a little different than what you mentioned early. Should I > > > follow the format in include/uapi/linux/rseq.h? or both formats are > > > OK? > > > > > > > The form "#if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || defined(__BIG_ENDIAN) > > is completely buggy. Don't use that. > > > > I've sent the fix to Peter to remove the offending #if here: > > > > https://lore.kernel.org/lkml/1445357149.71067.1643137248305.JavaMail.zimbra@efficios.com/T/#mbbad3961494feefb98cb6d092879e3ea41b33df8 > > > > Please use the correct non-bogus form instead: > > > > #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : defined(__LITTLE_ENDIAN) > > > > Thanks, > > > > Mathieu > > > > I understood. By the way, IIUC, the __BYTE_ORDER and __LITTLE_ENDIAN > are defined in the glibc endian.h. However, I find that no file in the > rseq folder includes the endian.h. Does it means I should include > <endian.h> in the rseq-riscv.h? After tracing the hierarchy of include files, I found that endian.h is included by pthread.h, and pthread.h is included by param_test.c. Therefore, rseq-riscv.h can exclude endian.h. I will follow your suggestions to modify my next version patch. Thank you. > > Thanks, > Vincent > > > > -- > > Mathieu Desnoyers > > EfficiOS Inc. > > http://www.efficios.com _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] rseq/selftests: Add support for RISC-V 2022-03-07 2:45 ` Vincent Chen @ 2022-03-07 13:40 ` Mathieu Desnoyers 0 siblings, 0 replies; 12+ messages in thread From: Mathieu Desnoyers @ 2022-03-07 13:40 UTC (permalink / raw) To: Vincent Chen; +Cc: Peter Zijlstra, Palmer Dabbelt, linux-riscv, Paul Walmsley ----- Vincent Chen <vincent.chen@sifive.com> wrote: > On Fri, Mar 4, 2022 at 2:50 PM Vincent Chen <vincent.chen@sifive.com> wrote: > > > > On Fri, Mar 4, 2022 at 5:50 AM Mathieu Desnoyers > > <mathieu.desnoyers@efficios.com> wrote: > > > > > > ----- On Mar 3, 2022, at 2:16 AM, Vincent Chen vincent.chen@sifive.com wrote: > > > > > > > On Thu, Mar 3, 2022 at 12:38 AM Mathieu Desnoyers > > > > <mathieu.desnoyers@efficios.com> wrote: > > > >> > > > [...] > > > > > > >> > +#if __ORDER_LITTLE_ENDIAN__ == 1234 > > > >> > > > >> I think we'll want to standardize on this for endianness checking (same as > > > >> the updated uapi rseq.h): > > > >> > > > >> #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : > > > >> defined(__LITTLE_ENDIAN) > > > >> > > > >> We may have to change rseq-mips.h in the rseq selftests to do the same as well > > > >> rather than > > > >> using "# ifdef __BIG_ENDIAN". > > > >> > > > > > > > > OK, I can follow it. However, I found the endianness checking in > > > > include/uapi/linux/rseq.h is > > > > #if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || > > > > defined(__BIG_ENDIAN) > > > > > > > > It is a little different than what you mentioned early. Should I > > > > follow the format in include/uapi/linux/rseq.h? or both formats are > > > > OK? > > > > > > > > > > The form "#if (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) || defined(__BIG_ENDIAN) > > > is completely buggy. Don't use that. > > > > > > I've sent the fix to Peter to remove the offending #if here: > > > > > > https://lore.kernel.org/lkml/1445357149.71067.1643137248305.JavaMail.zimbra@efficios.com/T/#mbbad3961494feefb98cb6d092879e3ea41b33df8 > > > > > > Please use the correct non-bogus form instead: > > > > > > #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : defined(__LITTLE_ENDIAN) > > > > > > Thanks, > > > > > > Mathieu > > > > > > > I understood. By the way, IIUC, the __BYTE_ORDER and __LITTLE_ENDIAN > > are defined in the glibc endian.h. However, I find that no file in the > > rseq folder includes the endian.h. Does it means I should include > > <endian.h> in the rseq-riscv.h? > > After tracing the hierarchy of include files, I found that endian.h is > included by pthread.h, and pthread.h is included by param_test.c. > Therefore, rseq-riscv.h can exclude endian.h. I will follow your > suggestions to modify my next version patch. Thank you. You should include what you use. Please include endian.h from the riscv header as well. Thanks, Mathieu > > > > > Thanks, > > Vincent > > > > > > -- > > > Mathieu Desnoyers > > > EfficiOS Inc. > > > http://www.efficios.com -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] rseq/selftests: Add support for RISC-V 2022-03-02 2:30 ` [PATCH v3 2/2] rseq/selftests: Add support for RISC-V Vincent Chen 2022-03-02 16:38 ` Mathieu Desnoyers @ 2022-03-08 7:30 ` Eric Lin 1 sibling, 0 replies; 12+ messages in thread From: Eric Lin @ 2022-03-08 7:30 UTC (permalink / raw) To: Vincent Chen; +Cc: palmer, mathieu.desnoyers, linux-riscv, Paul Walmsley Hi Vincent, On Wed, Mar 2, 2022 at 10:33 AM Vincent Chen <vincent.chen@sifive.com> wrote: > > Add support for RISC-V in the rseq selftests, which covers both > 64-bit and 32-bit ISA with little endian mode. > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > --- > tools/testing/selftests/rseq/param_test.c | 23 + > tools/testing/selftests/rseq/rseq-riscv.h | 676 ++++++++++++++++++++++ > tools/testing/selftests/rseq/rseq.h | 2 + > 3 files changed, 701 insertions(+) > create mode 100644 tools/testing/selftests/rseq/rseq-riscv.h > > diff --git a/tools/testing/selftests/rseq/param_test.c b/tools/testing/selftests/rseq/param_test.c > index 699ad5f93c34..0a6b8eafd444 100644 > --- a/tools/testing/selftests/rseq/param_test.c > +++ b/tools/testing/selftests/rseq/param_test.c > @@ -207,6 +207,29 @@ unsigned int yield_mod_cnt, nr_abort; > "addiu " INJECT_ASM_REG ", -1\n\t" \ > "bnez " INJECT_ASM_REG ", 222b\n\t" \ > "333:\n\t" > +#elif defined(__riscv) > + > +#define RSEQ_INJECT_INPUT \ > + , [loop_cnt_1]"m"(loop_cnt[1]) \ > + , [loop_cnt_2]"m"(loop_cnt[2]) \ > + , [loop_cnt_3]"m"(loop_cnt[3]) \ > + , [loop_cnt_4]"m"(loop_cnt[4]) \ > + , [loop_cnt_5]"m"(loop_cnt[5]) \ > + , [loop_cnt_6]"m"(loop_cnt[6]) > + > +#define INJECT_ASM_REG "t1" > + > +#define RSEQ_INJECT_CLOBBER \ > + , INJECT_ASM_REG > + > +#define RSEQ_INJECT_ASM(n) \ > + "lw " INJECT_ASM_REG ", %[loop_cnt_" #n "]\n\t" \ > + "beqz " INJECT_ASM_REG ", 333f\n\t" \ > + "222:\n\t" \ > + "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \ > + "bnez " INJECT_ASM_REG ", 222b\n\t" \ > + "333:\n\t" > + > > #else > #error unsupported target > diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h > new file mode 100644 > index 000000000000..845ec7d0f2ed > --- /dev/null > +++ b/tools/testing/selftests/rseq/rseq-riscv.h > @@ -0,0 +1,676 @@ > +/* SPDX-License-Identifier: LGPL-2.1 OR MIT */ > +/* > + * Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike > + * other architecture, the ebreak instruction has no immediate field for > + * distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG. > + * "csrw mhartid, x0" can also satisfy the RSEQ requirement because it > + * is an uncommon instruction and will raise an illegal instruction > + * exception when executed in all modes. > + */ > + > +#if __ORDER_LITTLE_ENDIAN__ == 1234 > +#define RSEQ_SIG 0xf1401073 /* csrr mhartid, x0 */ > +#else > +#error "Currently, RSEQ only supports Little-Endian version" > +#endif > + > +#if __riscv_xlen == 64 > +#define __REG_SEL(a, b) a > +#elif __riscv_xlen == 32 > +#define __REG_SEL(a, b) b > +#endif > + > +#define REG_L __REG_SEL("ld ", "lw ") > +#define REG_S __REG_SEL("sd ", "sw ") > + > +#define RISCV_FENCE(p, s) \ > + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") > +#define rseq_smp_mb() RISCV_FENCE(rw, rw) > +#define rseq_smp_rmb() RISCV_FENCE(r, r) > +#define rseq_smp_wmb() RISCV_FENCE(w, w) > +#define RSEQ_ASM_TMP_REG_1 "t6" > +#define RSEQ_ASM_TMP_REG_2 "t5" > +#define RSEQ_ASM_TMP_REG_3 "t4" > +#define RSEQ_ASM_TMP_REG_4 "t3" > + > +#define rseq_smp_load_acquire(p) \ > +__extension__ ({ \ > + __typeof(*(p)) ____p1 = RSEQ_READ_ONCE(*(p)); \ > + RISCV_FENCE(r, rw) \ > + ____p1; \ > +}) > + > +#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb() > + > +#define rseq_smp_store_release(p, v) \ > +do { \ > + RISCV_FENCE(rw, w); \ > + RSEQ_WRITE_ONCE(*(p), v); \ > +} while (0) > + > +#ifdef RSEQ_SKIP_FASTPATH > +#include "rseq-skip.h" > +#else /* !RSEQ_SKIP_FASTPATH */ > + > +#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \ > + post_commit_offset, abort_ip) \ > + ".pushsection __rseq_cs, \"aw\"\n" \ > + ".balign 32\n" \ > + __rseq_str(label) ":\n" \ > + ".long " __rseq_str(version) ", " __rseq_str(flags) "\n" \ > + ".quad " __rseq_str(start_ip) ", " \ > + __rseq_str(post_commit_offset) ", " \ > + __rseq_str(abort_ip) "\n" \ > + ".popsection\n\t" \ > + ".pushsection __rseq_cs_ptr_array, \"aw\"\n" \ > + ".quad " __rseq_str(label) "b\n" \ > + ".popsection\n" > + > +#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \ > + __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \ > + ((post_commit_ip) - (start_ip)), abort_ip) > + > +/* > + * Exit points of a rseq critical section consist of all instructions outside > + * of the critical section where a critical section can either branch to or > + * reach through the normal course of its execution. The abort IP and the > + * post-commit IP are already part of the __rseq_cs section and should not be > + * explicitly defined as additional exit points. Knowing all exit points is > + * useful to assist debuggers stepping over the critical section. > + */ > +#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \ > + ".pushsection __rseq_exit_point_array, \"aw\"\n" \ > + ".quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n" \ > + ".popsection\n" > + > +#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \ > + RSEQ_INJECT_ASM(1) \ > + "la "RSEQ_ASM_TMP_REG_1 ", " __rseq_str(cs_label) "\n" \ > + REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(rseq_cs) "]\n" \ > + __rseq_str(label) ":\n" > + > +#define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \ > + "j 222f\n" \ > + ".balign 4\n" \ > + ".long " __rseq_str(RSEQ_SIG) "\n" \ > + __rseq_str(label) ":\n" \ > + "j %l[" __rseq_str(abort_label) "]\n" \ > + "222:\n" > + > +#define RSEQ_ASM_OP_STORE(value, var) \ > + REG_S "%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" > + > +#define RSEQ_ASM_OP_CMPEQ(var, expect, label) \ > + REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ > + "bne "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ > + __rseq_str(label) "\n" > + > +#define RSEQ_ASM_OP_CMPEQ32(var, expect, label) \ > + "lw "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ > + "bne "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ > + __rseq_str(label) "\n" > + > +#define RSEQ_ASM_OP_CMPNE(var, expect, label) \ > + REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ > + "beq "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ > + __rseq_str(label) "\n" > + > +#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \ > + RSEQ_INJECT_ASM(2) \ > + RSEQ_ASM_OP_CMPEQ32(current_cpu_id, cpu_id, label) > + > +#define RSEQ_ASM_OP_R_LOAD(var) \ > + REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" > + > +#define RSEQ_ASM_OP_R_STORE(var) \ > + REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" > + > +#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \ > + "add "RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(offset) "], " \ > + RSEQ_ASM_TMP_REG_1 "\n" \ > + REG_L RSEQ_ASM_TMP_REG_1 ", (" RSEQ_ASM_TMP_REG_1 ")\n" > + > +#define RSEQ_ASM_OP_R_ADD(count) \ > + "add "RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 \ > + ", %[" __rseq_str(count) "]\n" > + > +#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \ > + RSEQ_ASM_OP_STORE(value, var) \ > + __rseq_str(post_commit_label) ":\n" > + > +#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \ > + "fence rw, w\n" \ > + RSEQ_ASM_OP_STORE(value, var) \ > + __rseq_str(post_commit_label) ":\n" > + > +#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \ > + REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ > + __rseq_str(post_commit_label) ":\n" > + > +#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \ > + "beqz %[" __rseq_str(len) "], 333f\n" \ > + "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(len) "]\n" \ > + "mv " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(src) "]\n" \ > + "mv " RSEQ_ASM_TMP_REG_3 ", %[" __rseq_str(dst) "]\n" \ > + "222:\n" \ > + "lb " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_2 ")\n" \ > + "sb " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_3 ")\n" \ > + "addi " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 ", -1\n" \ > + "addi " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", 1\n" \ > + "addi " RSEQ_ASM_TMP_REG_3 ", " RSEQ_ASM_TMP_REG_3 ", 1\n" \ > + "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \ > + "333:\n" > + > +#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label) \ > + "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \ > + RSEQ_ASM_OP_R_ADD(off) \ > + "ld " RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \ > + RSEQ_ASM_OP_R_ADD(inc) \ > + __rseq_str(post_commit_label) ":\n" > + > +static inline __always_inline > +int rseq_cmpeqv_storev(intptr_t *v, intptr_t expect, intptr_t newv, int cpu) > +{ > + RSEQ_INJECT_C(9) > + > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") > + RSEQ_INJECT_ASM(4) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") > +#endif > + RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) > + RSEQ_INJECT_ASM(5) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [v] "m" (*v), > + [expect] "r" (expect), > + [newv] "r" (newv) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1 > + RSEQ_INJECT_CLOBBER > + : abort, cmpfail > +#ifdef RSEQ_COMPARE_TWICE > + , error1, error2 > +#endif > + ); > + > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +cmpfail: > + return 1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +error2: > + rseq_bug("expected value comparison failed"); > +#endif > +} > + > +static inline __always_inline > +int rseq_cmpnev_storeoffp_load(intptr_t *v, intptr_t expectnot, > + off_t voffp, intptr_t *load, int cpu) > +{ > + RSEQ_INJECT_C(9) > + > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > + RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[cmpfail]") > + RSEQ_INJECT_ASM(4) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > + RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[error2]") > +#endif > + RSEQ_ASM_OP_R_LOAD(v) > + RSEQ_ASM_OP_R_STORE(load) > + RSEQ_ASM_OP_R_LOAD_OFF(voffp) > + RSEQ_ASM_OP_R_FINAL_STORE(v, 3) > + RSEQ_INJECT_ASM(5) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [v] "m" (*v), > + [expectnot] "r" (expectnot), > + [load] "m" (*load), > + [voffp] "r" (voffp) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1 > + RSEQ_INJECT_CLOBBER > + : abort, cmpfail > +#ifdef RSEQ_COMPARE_TWICE > + , error1, error2 > +#endif > + ); > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +cmpfail: > + return 1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +error2: > + rseq_bug("expected value comparison failed"); > +#endif > +} > + > +static inline __always_inline > +int rseq_addv(intptr_t *v, intptr_t count, int cpu) > +{ > + RSEQ_INJECT_C(9) > + > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > +#endif > + RSEQ_ASM_OP_R_LOAD(v) > + RSEQ_ASM_OP_R_ADD(count) > + RSEQ_ASM_OP_R_FINAL_STORE(v, 3) > + RSEQ_INJECT_ASM(4) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [v] "m" (*v), > + [count] "r" (count) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1 > + RSEQ_INJECT_CLOBBER > + : abort > +#ifdef RSEQ_COMPARE_TWICE > + , error1 > +#endif > + ); > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +#endif > +} > + > +static inline __always_inline > +int rseq_cmpeqv_trystorev_storev(intptr_t *v, intptr_t expect, > + intptr_t *v2, intptr_t newv2, > + intptr_t newv, int cpu) > +{ > + RSEQ_INJECT_C(9) > + > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") > + RSEQ_INJECT_ASM(4) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") > +#endif > + RSEQ_ASM_OP_STORE(newv2, v2) > + RSEQ_INJECT_ASM(5) > + RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) > + RSEQ_INJECT_ASM(6) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [expect] "r" (expect), > + [v] "m" (*v), > + [newv] "r" (newv), > + [v2] "m" (*v2), > + [newv2] "r" (newv2) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1 > + RSEQ_INJECT_CLOBBER > + : abort, cmpfail > +#ifdef RSEQ_COMPARE_TWICE > + , error1, error2 > +#endif > + ); > + > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +cmpfail: > + return 1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +error2: > + rseq_bug("expected value comparison failed"); > +#endif > +} > + > +static inline __always_inline > +int rseq_cmpeqv_trystorev_storev_release(intptr_t *v, intptr_t expect, > + intptr_t *v2, intptr_t newv2, > + intptr_t newv, int cpu) > +{ > + RSEQ_INJECT_C(9) > + > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") > + RSEQ_INJECT_ASM(4) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") > +#endif > + RSEQ_ASM_OP_STORE(newv2, v2) > + RSEQ_INJECT_ASM(5) > + RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3) > + RSEQ_INJECT_ASM(6) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [expect] "r" (expect), > + [v] "m" (*v), > + [newv] "r" (newv), > + [v2] "m" (*v2), > + [newv2] "r" (newv2) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1 > + RSEQ_INJECT_CLOBBER > + : abort, cmpfail > +#ifdef RSEQ_COMPARE_TWICE > + , error1, error2 > +#endif > + ); > + > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +cmpfail: > + return 1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +error2: > + rseq_bug("expected value comparison failed"); > +#endif > +} > + > +static inline __always_inline > +int rseq_cmpeqv_cmpeqv_storev(intptr_t *v, intptr_t expect, > + intptr_t *v2, intptr_t expect2, > + intptr_t newv, int cpu) > +{ > + RSEQ_INJECT_C(9) > + > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error3]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") > + RSEQ_INJECT_ASM(4) > + RSEQ_ASM_OP_CMPEQ(v2, expect2, "%l[cmpfail]") > + RSEQ_INJECT_ASM(5) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") > + RSEQ_ASM_OP_CMPEQ(v2, expect2, "%l[error3]") > +#endif > + RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) > + RSEQ_INJECT_ASM(6) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [v] "m" (*v), > + [expect] "r" (expect), > + [v2] "m" (*v2), > + [expect2] "r" (expect2), > + [newv] "r" (newv) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1 > + RSEQ_INJECT_CLOBBER > + : abort, cmpfail > +#ifdef RSEQ_COMPARE_TWICE > + , error1, error2, error3 > +#endif > + ); > + > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +cmpfail: > + return 1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +error2: > + rseq_bug("expected value comparison failed"); > +error3: > + rseq_bug("2nd expected value comparison failed"); > +#endif > +} > + > +static inline __always_inline > +int rseq_cmpeqv_trymemcpy_storev(intptr_t *v, intptr_t expect, > + void *dst, void *src, size_t len, > + intptr_t newv, int cpu) > +{ > + RSEQ_INJECT_C(9) > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") > + RSEQ_INJECT_ASM(4) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") > +#endif > + RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) > + RSEQ_INJECT_ASM(5) > + RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) > + RSEQ_INJECT_ASM(6) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [expect] "r" (expect), > + [v] "m" (*v), > + [newv] "r" (newv), > + [dst] "r" (dst), > + [src] "r" (src), > + [len] "r" (len) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1, RSEQ_ASM_TMP_REG_2, > + RSEQ_ASM_TMP_REG_3, RSEQ_ASM_TMP_REG_4 > + RSEQ_INJECT_CLOBBER > + : abort, cmpfail > +#ifdef RSEQ_COMPARE_TWICE > + , error1, error2 > +#endif > + ); > + > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +cmpfail: > + return 1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +error2: > + rseq_bug("expected value comparison failed"); > +#endif > +} > + > +static inline __always_inline > +int rseq_cmpeqv_trymemcpy_storev_release(intptr_t *v, intptr_t expect, > + void *dst, void *src, size_t len, > + intptr_t newv, int cpu) > +{ > + RSEQ_INJECT_C(9) > + > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]") > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") > + RSEQ_INJECT_ASM(4) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > + RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") > +#endif > + RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) > + RSEQ_INJECT_ASM(5) > + RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3) > + RSEQ_INJECT_ASM(6) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [expect] "r" (expect), > + [v] "m" (*v), > + [newv] "r" (newv), > + [dst] "r" (dst), > + [src] "r" (src), > + [len] "r" (len) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1, RSEQ_ASM_TMP_REG_2, > + RSEQ_ASM_TMP_REG_3, RSEQ_ASM_TMP_REG_4 > + RSEQ_INJECT_CLOBBER > + : abort, cmpfail > +#ifdef RSEQ_COMPARE_TWICE > + , error1, error2 > +#endif > + ); > + > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +cmpfail: > + return 1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +error2: > + rseq_bug("expected value comparison failed"); > +#endif > +} > + > +#define RSEQ_ARCH_HAS_OFFSET_DEREF_ADDV > + > +/* > + * pval = *(ptr+off) > + * *pval += inc; > + */ > +static inline __always_inline > +int rseq_offset_deref_addv(intptr_t *ptr, off_t off, intptr_t inc, int cpu) > +{ > + RSEQ_INJECT_C(9) > + > + __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") > +#endif > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) > + RSEQ_INJECT_ASM(3) > +#ifdef RSEQ_COMPARE_TWICE > + RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") > +#endif > + RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3) > + RSEQ_INJECT_ASM(4) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [cpu_id] "r" (cpu), > + [current_cpu_id] "m" (__rseq_abi.cpu_id), > + [rseq_cs] "m" (__rseq_abi.rseq_cs), > + [ptr] "r" (ptr), > + [off] "er" (off), > + [inc] "er" (inc) > + RSEQ_INJECT_INPUT > + : "memory", RSEQ_ASM_TMP_REG_1 > + RSEQ_INJECT_CLOBBER > + : abort > +#ifdef RSEQ_COMPARE_TWICE > + , error1 > +#endif > + ); > + return 0; > +abort: > + RSEQ_INJECT_FAILED > + return -1; > +#ifdef RSEQ_COMPARE_TWICE > +error1: > + rseq_bug("cpu_id comparison failed"); > +#endif > +} > + > +#endif /* !RSEQ_SKIP_FASTPATH */ > diff --git a/tools/testing/selftests/rseq/rseq.h b/tools/testing/selftests/rseq/rseq.h > index 3f63eb362b92..72efb6d3d84e 100644 > --- a/tools/testing/selftests/rseq/rseq.h > +++ b/tools/testing/selftests/rseq/rseq.h > @@ -79,6 +79,8 @@ extern int __rseq_handled; > #include <rseq-mips.h> > #elif defined(__s390__) > #include <rseq-s390.h> > +#elif defined(__riscv) > +#include <rseq-riscv.h> > #else > #error unsupported target > #endif > -- I've run tests on riscv qemu32 and qemu64. It passed with no error and warning message. # bash run_param_test.sh Default parameters Running test spinlock Running compare-twice test spinlock Running test list Running compare-twice test list Running test buffer Running compare-twice test buffer Running test buffer with barrier Running compare-twice test buffer with barrier Running test memcpy Running compare-twice test memcpy .... Running test buffer with barrier Running compare-twice test buffer with barrier Running test memcpy Running compare-twice test memcpy Running test memcpy with barrier Running compare-twice test memcpy with barrier Running test increment Running compare-twice test increment Running test membarrier Running compare-twice test membarrier # echo $? 0 Thanks. Tested-by: Eric Lin <eric.lin@sifive.com> Best regards, Eric Lin > 2.17.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-03-08 7:31 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-03-02 2:30 [PATCH v3 0/2] RISC-V: add support for restartable sequence Vincent Chen 2022-03-02 2:30 ` [PATCH v3 1/2] RISC-V: Add " Vincent Chen 2022-03-02 16:29 ` Mathieu Desnoyers 2022-03-03 3:32 ` Vincent Chen 2022-03-02 2:30 ` [PATCH v3 2/2] rseq/selftests: Add support for RISC-V Vincent Chen 2022-03-02 16:38 ` Mathieu Desnoyers 2022-03-03 7:16 ` Vincent Chen 2022-03-03 21:50 ` Mathieu Desnoyers 2022-03-04 6:50 ` Vincent Chen 2022-03-07 2:45 ` Vincent Chen 2022-03-07 13:40 ` Mathieu Desnoyers 2022-03-08 7:30 ` Eric Lin
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